74HC05D,118

74HC05 Hex inverter with open-drain outputs Rev. 02 — 18 June 2009 Product data sheet 1. General description The 74HC05 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A. The 74HC05 contains six inverters.The outputs of the 74HC05 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly. 2. Features n Wide operating voltage 2.0 V to 6.0 V n Input levels: u For 74HC05: CMOS level n Latch-up performance exceeds 100 mA per JESD 78 Class II level A n ESD protection: u HBM JESD22-A114E exceeds 2000 V u CDM JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC05D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC05PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HC05BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 4. Functional diagram 1 1A 1Y 2 3 2A 2Y 4 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 VCC Y A GND mna525 Fig 1. 001aaj979 Logic symbol Fig 2. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74HC05 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 GND 7 9 4A 8 4Y 001aaj980 Fig 3. Pin configuration SOT108-1 (SO14) 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 2 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 1 1A terminal 1 index area 74HC05 2 13 6A 2A 3 12 6Y 2Y 4 5 6 11 5A 2A 3 12 6Y 3A 2Y 4 11 5A 3Y 3A 5 10 5Y 8 1Y 13 6A 3Y 6 9 4A 4Y 14 VCC 2 7 1 1Y GND 7 8 4Y GND 1A 14 VCC 74HC05 GND(1) 10 5Y 9 4A 001aak277 Transparent top view 001aak276 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SOT402-1 (TSSOP14) Fig 5. Pin configuration SOT762-1 (DHVQFN14) 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 6A 1, 3, 5, 9, 11, 13 data input 1Y to 6Y 2, 4, 6, 8, 10, 12 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nY L Z H L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +7 V IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] - 20 mA [1] −0.5 VCC + 0.5 V V VO output voltage 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 3 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit IO output current VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C - 500 mW [2] total power dissipation Ptot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 - +125 °C ∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions Min VIH VIL VOL HIGH-level input voltage −40 °C to +85 °C −40 °C to +125 °C Unit Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC05_2 Product data sheet - © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 4 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions Min II input leakage current VI = VCC or GND; VCC = 6.0 V IOZ OFF-state output current per input pin; VI = VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 6.0 V; IO = 0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V CI input capacitance - −40 °C to +85 °C −40 °C to +125 °C Unit Typ Max - 0.1 - - Min - 0.5 Max 1 Min - - Max µA 1 5.0 - 10 µA - - 2.0 - 20 - 40 µA - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit see Figure 7. Symbol Parameter 25 °C Conditions Min Typ Max Max (85 °C) Max (125 °C) - 20 90 115 135 ns VCC = 4.5 V - 11 18 23 27 ns VCC = 6.0 V - 10 15 20 23 ns - 22 90 115 135 ns VCC = 4.5 V - 9 18 23 27 ns VCC = 6.0 V - 8 15 20 23 ns VCC = 2.0 V - 18 75 95 110 ns VCC = 4.5 V - 6 15 19 22 ns - 5 13 16 19 ns - 4 - - - pF LOW to OFF-state nA to nY; see Figure 6 propagation delay VCC = 2.0 V tPLZ OFF-state to LOW nA to nY; see Figure 6 propagation delay VCC = 2.0 V tPZL HIGH to LOW output transition time tTHL see Figure 6 VCC = 6.0 V power dissipation capacitance CPD [1] −40 °C to +125 °C Unit per inverter; VI = GND to VCC; VCC = 5.0 V [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(0.5 × CL × VO2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; VO = output voltage in V (output HIGH); VCC = supply voltage in V; N = number of inputs switching; RL = load resistance in MΩ; CL = load capacitance in pF; 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 5 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 11. Waveforms VI nA input VM GND tPLZ tPZL VCC 90 % nY output VM VOL 10 % VX tTHL 001aaj981 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. The input nA to output nY propagation delays and output transition times Measurement points Input Output VM VM VX 0.5VCC 0.5VCC 0.1VCC 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 6 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL RT S1 open DUT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = Load resistance. Fig 7. Table 9. Test circuit for measuring switching times Test data Input Load S1 position VI tr, tf CL RL tPZL, tPLZ VCC 6 ns 50 pF 1 kΩ VCC 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 7 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 8 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 9. Package outline SOT402-1 (TSSOP14) 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 9 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 (DHVQFN14) 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 10 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC05_2 20090618 Product data sheet - 74HC05_1 Modifications: 74HC05_1 • Added type numbers 74HC05PW (TSSOP14 package) and 74HC05BQ (DHVQFN14 package) 20090427 Product data sheet 74HC05_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 11 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC05_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 18 June 2009 12 of 13 74HC05 NXP Semiconductors Hex inverter with open-drain outputs 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 June 2009 Document identifier: 74HC05_2