74VHCT16374A

74VHCT16374A 16-BIT D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING s s s s s s s s s s HIGH SPEED: fMAX = 185 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH =2V (MIN.) VIL = 0.8 (MAX.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 16374 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.) TSSOP ORDER CODES PACKAGE TSSOP TUBE T&R PIN CONNECTION bs O DESCRIPTION The 74VHCT16374A is an advanced high-speed CMOS 16 D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 16 bit D-TYPE flip-flop is controlled by two clock inputs (CK) and two output enable inputs (nOE). The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the outputs will be in a normal logic state (high or low logic level); while OE is high, the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. let o Pr e du o (s) ct so Ob - te le ro P uc d 74VHCT16374ATTR s) t( February 2003 1/10 74VHCT16374A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 24 SYMBOL 1OE 1Q0 to 1Q7 2Q0 to 2Q7 2OE NAME AND FUNCTION 3 State Output Enable Input (Active LOW) 3-State Outputs 3-State Outputs IEC LOGIC SYMBOLS 3 State Output Enable Input (Active LOW) 25 2CK Clock Input (LOW-to-HIGH Edge Trigger) 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input (LOW-to-HIGH Edge Trigger) 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 VCC Positive Supply Voltage TRUTH TABLE INPUTS OE O bs L L L H let o CK X Pr e du o D X X L H (s) ct Q Z so Ob - te le ro P uc d s) t( OUTPUTS NO CHANGE L H X : Don’t Care Z : High Impedance 2/10 74VHCT16374A LOGIC DIAGRAM This logic diagram has not to be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Parameter ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol bs O VI VCC VO let o Supply Voltage Input Voltage Output Voltage ro P e uc d (s) t Ob - so te le ro P Value uc d s) t( Unit V V V mA mA mA mA °C °C -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 75 -65 to +150 300 Parameter Value 4.5 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V °C ns/V Top Operating Temperature Input Rise and Fall Time (note 1) (Vcc= 5.0±0.5V) dt/dv 1) VIN from 0.8V to 2.0V 3/10 74VHCT16374A DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 0 to 5.5 5.5 IO=-50 µA IO=-8 mA IO=50 µA IO=8 mA VI = VIH or VIL VO = VCC or GND VI = 5.5V or GND VI = VCC or GND TA = 25°C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 ±0.25 ± 0.1 4 4.5 4.4 3.8 0.1 0.44 ± 2.5 ±1 40 Typ. Max. Value -40 to 85°C Min. 2 0.8 4.4 3.7 0.1 0.55 ± 2.5 ±1 40 Max. -55 to 125°C Min. 2 0.8 Max. V V V V µA µA µA Unit VIH VIL VOH VOL IOZ High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current II ICC AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0 (*) CL (pF) 15 50 15 50 50 TA = 25°C tPLH tPHL tPZL tPZH tPLZ tPHZ tw ts th Propagation Delay Time CK to Q Output Enable Time Output Disable Time O bs fMAX let o Clock Pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Maximum Clock Frequency Output to Output Skew time (note 1) od Pr e 5.0 5.0(*) 5.0(*) 5.0(*) 5.0(*) 5.0(*) (*) ct u 15 50 50 (s) RL = 1KΩ RL = 1KΩ Ob 6.5 2.5 2.5 90 85 Min. so 5.6 6.4 6.2 7.3 7.0 Typ. eP let Value Max. 9.4 10.4 10.2 11.2 11.2 Min. 1.0 1.0 1.0 1.0 1.0 6.5 2.5 2.5 od r Max. 10.5 11.5 11.5 12.5 12.0 uc s) t( -40 to 85°C -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 6.5 2.5 2.5 80 75 Max. 10.5 11.5 11.5 12.5 12.0 Unit ns ns ns ns ns ns MHz 140 130 1.0 110 75 1.0 tOSLH tOSHL 5.0(*) 1.0 ns (*) Voltage range is 5.0V ± 0.5V (Note 1 : Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn| 4/10 74VHCT16374A CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) TA = 25°C Min. Typ. 4 6 5.0 fIN = 10MHz 21 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF pF Unit CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per Latch) DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 TA = 25°C Min. Typ. 0.6 -0.9 CL = 50 pF 3.5 -0.6 Max. 0.9 Value -40 to 85°C Min. Max. VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 5.0 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ILD), 0V to threshold (VIHD), f=1MHz. bs O let o Pr e du o (s) ct so Ob - te le 1.5 ro P uc d Min. -55 to 125°C Max. s) t( Unit V V V 5/10 74VHCT16374A TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK FREQUENCY (f=1MHz; 50% duty cycle) bs O let o Pr e du o (s) ct so Ob - te le ro P uc d Open VCC GND SWITCH s) t( 6/10 74VHCT16374A WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle) bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 7/10 74VHCT16374A TSSOP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.50 6.0 0.5 BSC 8˚ 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 MIN. TYP. MAX. 0.047 0.006 inch A A2 A1 b bs O let o ro P e du (s) ct e D so Ob c 0.75 te le 0˚ 0.020 ro P 0.0197 BSC uc d s) t( 0.496 0.244 8˚ 0.030 K L E E1 PIN 1 IDENTIFICATION 1 7065588C 8/10 74VHCT16374A Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 MIN. TYP. MAX. 12.992 0.519 inch bs O let o Pr e du o (s) ct so Ob - eP let ro uc d s) t( 0.524 0.067 0.161 0.476 9/10 74VHCT16374A bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( Information furnished is believed to be accurate and reliable. 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