A6986F
Automotive 38 V, 1.5 A synchronous step-down switching regulator
with 30 μA quiescent current
Datasheet - production data
Description
HTSSOP16 (RTH = 40 °C/W)
Features
AEC-Q100 qualified
1.5 A DC output current
4 V to 38 V operating input voltage
Low consumption mode or low noise mode
30 µA IQ at light-load (LCM VOUT = 3.3 V)
8 µA IQ-SHTDWN
Adjustable fSW (250 kHz - 2 MHz)
Fixed output voltage (3.3 V and 5 V) or
adjustable from 0.85 V to VIN
Embedded output voltage supervisor
Synchronization
Adjustable soft-start time
The A6986F automotive grade device is a stepdown monolithic switching regulator able to
deliver up to 1.5 A DC. The output voltage
adjustability ranges from 0.85 V to VIN. The 100%
duty cycle capability and the wide input voltage
range meet the cold crank and load dump
specifications for automotive systems. The “Low
Consumption Mode” (LCM) is designed for
applications active during car parking, so it
maximizes the efficiency at light-load with
controlled output voltage ripple. The “Low Noise
Mode” (LNM) makes the switching frequency
constant and minimizes the output voltage ripple
overload current range, meeting the low noise
application specification like car audio. The output
voltage supervisor manages the reset phase for
any digital load (µC, FPGA). The RST open
collector output can also implement output
voltage sequencing during the power-up phase.
The synchronous rectification, designed for high
efficiency at medium - heavy load, and the high
switching frequency capability make the size of
the application compact. Pulse by pulse current
sensing on both power elements implements an
effective constant current protection.
Internal current limiting
Overvoltage protection
Output voltage sequencing
Peak current mode architecture
RDSON HS = 180 m, RDSON LS = 150 m
Thermal shutdown
Applications
Designed for automotive systems
Battery powered applications
Car body applications (LCM)
Car audio and low noise applications (LNM)
August 2020
This is information on a product in full production.
DocID027739 Rev 6
1/79
www.st.com
Contents
A6986F
Contents
1
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Datasheet parameters over the temperature range . . . . . . . . . . . . . . . 13
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1
Ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.2
Output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4
Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5
Output voltage line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6
Output voltage load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.7
High-side switch resistance vs. input voltage . . . . . . . . . . . . . . . . . . . . . . 26
5.8
Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9
5.10
5.8.1
Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8.2
Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.8.3
Quiescent current in LCM with switchover . . . . . . . . . . . . . . . . . . . . . . . 34
Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.9.1
LCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.9.2
LNM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
OCP and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2/79
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A6986F
6
7
Contents
5.11
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.12
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1
GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2
Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3
Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.4
Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5
Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.1
Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.3
MLF pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.4
Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.5
Synchronization (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.6
Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.6.1
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.6.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.6.3
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8
Application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9
Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10
EMC testing results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.1
HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DocID027739 Rev 6
3/79
79
Application schematic
1
A6986F
Application schematic
Figure 1. Application schematic
5
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4/79
DocID027739 Rev 6
A6986F
Pin settings
2
Pin settings
2.1
Pin connection
Figure 2. Pin connection (top view)
2.2
345
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Pin description
Table 1. Pin description
No.
Pin
Description
1
RST
The RST open collector output is driven low when the output voltage is out of regulation. The RST
is released after an adjustable time DELAY once the output voltage is over the active delay
threshold.
2
VCC
Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the
embedded analog circuitry.
3
SS/INH
An open collector stage can disable the device clamping this pin to GND (INH mode). An internal
current generator (4 A typ.) charges the external capacitor to implement the soft-start.
4
SYNCH/
ISKP
The pin features Master / Slave synchronization in LNM (see Section 5.8.1 on page 26) and skip
current level selection in LCM (see Section 5.8.2 on page 27). In LNM, leave this pin floating when
not used.
5
FSW
A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency.
Pinstrapping is active only before the soft-start phase to minimize the IC consumption.
6
MLF
A pull up resistor (E24 series only) to VCC or pull down to GND selects the low noise mode/low
consumption mode and the active RST threshold. Pinstrapping is active only before the soft-start
phase to minimize the IC consumption.
7
COMP
Output of the error amplifier. The designed compensation network is connected at this pin.
8
DELAY
An external capacitor connected at this pin sets the time DELAY to assert the rising edge of the
RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like
a Power Good.
9
VOUT
Output voltage sensing
10
SGND
Signal GND
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79
Pin settings
A6986F
Table 1. Pin description (continued)
No.
Pin
11
PGND
Power GND
12
PGND
Power GND
13
LX
Switching node
14
LX
Switching node
15
VIN
DC input voltage
16
VBIAS
Typically connected to the regulated output voltage. An external voltage reference can be used to
supply part of the analog circuitry to increase the efficiency at light-load. Connect to GND if not
used.
-
E. p.
Exposed pad must be connected to SGND, PGND
2.3
Description
Maximum ratings
Stressing the device above the rating listed in Table 2: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2. Absolute maximum ratings
Symbol
Min.
Max.
Unit
VIN
-0.3
40
V
DELAY
-0.3
VCC + 0.3
V
PGND
SGND - 0.3
SGND + 0.3
V
SGND
-
-
V
VCC
-0.3
(VIN + 0.3) or (max. 4)
V
SS / INH
-0.3
VIN + 0.3
V
-0.3
VCC + 0.3
V
-0.3
VCC + 0.3
V
VOUT
-0.3
10
V
FSW
-0.3
VCC + 0.3
V
SYNCH
-0.3
VIN + 0.3
V
VBIAS
-0.3
(VIN + 0.3) or (max. 6)
V
RST
-0.3
VIN + 0.3
V
LX
-0.3
VIN + 0.3
V
MLF
COMP
Description
See Table 1
TJ
Operating temperature range
-40
150
°C
TSTG
Storage temperature range
-
-65 to 150
°C
TLEAD
Lead temperature (soldering 10 sec.)
-
260
°C
IHS, ILS
High-side / low-side switch current
-
2
A
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A6986F
2.4
Pin settings
Thermal data
Table 3. Thermal data
Symbol
2.5
Parameter
Value
Unit
Rth JA
Thermal resistance junction ambient (device soldered on the
STMicroelectronics demonstration board)
40
°C/W
Rth JC
Thermal resistance junction to exposed pad for board design
(not suggested to estimate TJ from power losses).
5
°C/W
ESD protection
Table 4. ESD protection
Symbol
ESD
Test condition
Value
Unit
HBM
2
kV
MM
200
CDM non-corner pins
500
CDM corner pins
750
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79
Electrical characteristics
3
A6986F
Electrical characteristics
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
Test condition
Note Min.
Typ.
Max.
VIN
Operating input voltage range -
-
4
-
38
VINH
VCC UVLO rising threshold
-
-
2.7
-
3.5
VINL
VCC UVLO falling threshold
-
-
2.4
-
3.5
Duty cycle < 20%
-
2.3
-
-
Duty cycle = 100%
closed loop operation
-
1.8
-
-
IPK
IVY
Peak current limit
A
-
2.4
-
-
LCM, VSYNCH = GND
0.2
0.4
0.6
LCM, VSYNCH = VCC
(2)
-
0.2
-
-
LNM or VOUT overvoltage
-
0.5
1
2
-
RDSON HS High-side RDSON
ISW = 1 A
-
-
0.18
0.360
Low-side RDSON
ISW = 1 A
-
-
0.15
0.300
ISKIPL
IVY_SNK
RDSON LS
Programmable skip current
limit
Reverse current limit
-
V
(1)
ISKIPH
Valley current limit
Unit
fSW
Selected switching frequency FSW pinstrapping before SS
-
IFSW
FSW biasing current
SS ended
-
MLF pinstrapping before SS
-
Low noise mode /
LCM/LNM Low consumption mode
selection
IMLF
D
TON MIN
MLF biasing current
SS ended
See Table 6: fSW selection
-
0
500
nA
See Table 7 on page 11,
Table 8 on page 12, Table 9
on page 12
-
-
0
500
nA
0
-
100
%
ns
Duty cycle
-
(2)
Minimum On time
-
-
-
80
-
VBIAS = GND (no switchover)
-
2.9
3.3
3.6
VBIAS = 5 V (switchover)
-
2.9
3.3
3.6
Switch internal supply from VIN
to VBIAS
-
2.85
-
3.2
Switch internal supply from
VBIAS to VIN
-
2.78
-
3.15
VCC regulator
VCC
SWO
8/79
LDO output voltage
VBIAS threshold
(3 V< VBIAS < 5.5 V)
DocID027739 Rev 6
V
A6986F
Electrical characteristics
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Note Min.
Typ.
Max.
Unit
A
Power consumption
ISHTDWN
Shutdown current from VIN
VSS/INH = GND
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
IQ OPVIN
Quiescent current from VIN
IQ OPVBIAS Quiescent current from VBIAS
LCM - NO SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = GND
-
4
8
15
(3)
4
10
15
A
(3)
35
70
120
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
-
0.5
1.5
5
LNM - NO SWO
VFB = GND (NO SLEEP)
VBIAS = GND
-
2
2.8
6
(3)
25
50
115
A
-
0.5
1.2
5
mA
SS rising
-
200
460
700
-
-
-
100
140
(2)
-
1
-
LCM - SWO
VREF < VFB < VOVP (SLEEP)
VBIAS = 3.3 V
LNM - SWO
VFB = GND (NO SLEEP)
VBIAS = 3.3 V
mA
Soft-start
VINH
VSS threshold
VINH HYST VSS hysteresis
ISS CH
CSS charging current
VSS < VINH OR
t < TSS SETUP OR
VEA+ > VFB
t > TSS SETUP AND
VEA+ < VFB
VSS START
SSGAIN
mV
A
(2)
-
4
-
Start of internal error amplifier
ramp
-
0.995
1.1
1.150
V
SS/INH to internal error
amplifier gain
-
-
-
3
-
-
3.3 V (A6986F3V3)
-
3.25
3.3
3.35
5 V (A6986F5V)
-
4.925
5.0.
5.075
A6986F
-
0.841
0.85
0.859
3.3 V (A6986F3V3)
-
4
6
8.5
5 V (A6986F5V)
-
7.5
10
13.5
A6986F
-
-
50
500
Error amplifier
VOUT
IVOUT
Voltage feedback
VOUT biasing current
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79
Electrical characteristics
A6986F
Table 5. Electrical characteristics (continued)
Symbol
AV
ICOMP
Parameter
Test condition
Note Min.
Typ.
Max.
Unit
dB
-
(2)
-
100
-
-
-
±6
±12
±25
-
(4)
±4
-
-
Current sense
transconductance (VCOMP to
inductor current gain)
Ipk = 1 A
(2)
-
2.5
-
A/V
Slope compensation
-
(5)
0.45
0.75
1
A
-
1.15
1.2
1.25
-
-
0.5
2
5
%
Error amplifier gain
EA output current capability
A
Inner current loop
gCS
VPP*gCS
Overvoltage protection
VOVP
Overvoltage trip (VOVP/VREF) -
VOVP HYST Overvoltage hysteresis
-
Synchronization (fan out: 6 slave devices typ.)
fSYN MIN
Synchronization frequency
LNM; fSW = VCC
-
266.5
-
-
kHz
VSYN TH
SYNCH input threshold
LNM, SYNCH rising
-
0.70
-
1.2
V
SYNCH pull-down current
LNM, VSYN = 1.2 V
-
0.7
-
mA
High level output
LNM, 5 mA sinking load
-
1.40
-
-
Low level output
LNM, 0.7 mA sourcing load
-
-
-
0.6
Selected RST threshold
MLF pinstrapping before SS
ISYN
VSYN OUT
V
Reset
VTHR
VTHR HYST RST hysteresis
VRST
RST open collector output
-
see Table 7, Table 8, Table 9
(2)
-
2
-
VIN > VINH AND
VFB < VTH
4 mA sinking load
-
-
-
0.4
2 < VIN < VINH
4 mA sinking load
-
-
-
%
V
-
0.8
Delay
VTHD
RST open collector released
as soon as VDELAY > VTHD
VFB > VTHR
-
1.19
ID CH
CDELAY charging current
VFB > VTHR
-
1
2
3
-
(2)
-
165
-
Thermal shutdown hysteresis -
(2)
-
30
-
1.234 1.258
V
A
Thermal shutdown
TSHDWN
THYS
Thermal shutdown
temperature
°C
1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
2. Not tested in production.
3. LCM enables SLEEP mode at light-load.
4. TJ = -40 °C.
5. Measured at fsw = 250 kHz.
10/79
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Electrical characteristics
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 6. fSW selection
Symbol
fSW
RVCC (E24 series)
RGND (E24 series)
0
Tj
fSW min.
fSW typ.
fSW max.
NC
225
250
275
1.8 k
NC
-
285
-
3.3 k
NC
-
330
-
5.6 k
NC
-
380
-
10 k
NC
-
435
-
NC
0
450
500
550
18 k
NC
-
575
-
33 k
NC
-
660
-
56 k
NC
-
755
-
NC
1.8 k
-
870
-
NC
3.3 k
900
1000
1100
NC
5.6 k
-
1150
-
NC
10 k
-
1310
-
-
1500(2)
1925
2200
(1)
(1)
(1)
18 k
NC
NC
33 k
1575
1750(2)
NC
56 k
1800
2000(2)
Unit
kHz
1. Not tested in production.
2. No synchronization as slave in LNM.
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 7. LNM / LCM selection (A6986F3V3)
Symbol
VRST
RVCC
RGND
(E24 1%)
(E24 1%)
VRST
VRST
VRST
min.
typ.
max.
0
NC
93%
3.008
3.069
3.130
8.2 k
NC
80%
2.587
2.640
2.693
18 k
NC
87%
2.814
2.871
2.928
39 k
NC
96%
3.105
3.168
3.231
NC
0
93%
3.008
3.069
3.130
NC
8.2 k
80%
2.587
2.640
2.693
NC
18 k
87%
2.814
2.871
2.928
NC
39 k
96%
3.105
3.168
3.231
Operating VRST/VOUT
mode
(tgt. value)
LCM
LNM
DocID027739 Rev 6
Unit
V
11/79
79
Electrical characteristics
A6986F
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 8. LNM / LCM selection (A6986F5V)
Symbol
VRST
RVCC
RGND
(E24 1%)
(E24 1%)
0
NC
8.2 k
NC
18 k
NC
39 k
Operating VRST/VOUT
mode
(tgt. value)
VRST
VRST
VRST
min.
typ.
max.
93%
4.557
4.650
4.743
80%
3.920
4.000
4.080
87%
4.263
4.350
4.437
NC
96%
4.704
4.800
4.896
NC
0
93%
4.557
4.650
4.743
NC
8.2 k
80%
3.920
4.000
4.080
NC
18 k
87%
4.263
4.350
4.437
NC
39 k
96%
4.704
4.800
4.896
LCM
LNM
Unit
V
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
Table 9. LNM / LCM selection (A6986F)
Symbol
VRST
12/79
RVCC
RGND
VRST/VOUT
VRST
VRST
VRST
(E24 1%)
(E24 1%)
(tgt value)
min.
typ.
max.
0
NC
93%
0.779
0.791
0.802
8.2 k ± 1%
NC
80%
0.670
0.680
0.690
18 k ± 1%
NC
87%
0.728
0.740
0.751
39 k ± 1%
NC
96%
0.804
0.816
0.828
NC
0
93%
0.779
0.791
0.802
NC
8.2 k± 1%
80%
0.670
0.680
0.690
NC
18 k ± 1%
87%
0.728
0.740
0.751
NC
39 k ± 1%
96%
0.804
0.816
0.828
Operating
mode
LCM
LNM
DocID027739 Rev 6
Unit
V
A6986F
4
Datasheet parameters over the temperature range
Datasheet parameters over the temperature range
The 100% of the population in the production flow is tested at three different ambient
temperatures (-40 °C, +25 °C, +135 °C) to guarantee the datasheet parameters inside the
junction temperature range (-40 °C, +135 °C).
The device operation is guaranteed when the junction temperature is inside the (-40 °C,
+150 °C) temperature range. The designer can estimate the silicon temperature increase
respect to the ambient temperature evaluating the internal power losses generated during
the device operation.
However the embedded thermal protection disables the switching activity to protect the
device in case the junction temperature reaches the TSHTDWN (+165 °C typ.) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of
+135 °C to avoid triggering the thermal shutdown protection during the testing phase
because of self-heating.
DocID027739 Rev 6
13/79
79
Functional description
5
A6986F
Functional description
The A6986F device is based on a “peak current mode”, constant frequency control. As
a consequence, the intersection between the error amplifier output and the sensed inductor
current generates the PWM control signal to drive the power switch.
The device features LNM (low noise mode) that is forced PWM control, or LCM (low
consumption mode) to increase the efficiency at light-load.
The main internal blocks shown in the block diagram in Figure 3 are:
14/79
Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the
device features low dropout operation
A fully integrated sawtooth oscillator with adjustable frequency
A transconductance error amplifier
An internal feedback divider GDIV INT
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the
embedded power elements
The soft-start blocks to ramp the error amplifier reference voltage and so decreases the
inrush current at power-up. The SS/INH pin inhibits the device when driven low.
The switchover capability of the internal regulator to supply a portion of the quiescent
current when the VBIAS pin is connected to an external output voltage
The synchronization circuitry to manage master / slave operation and the
synchronization to an external clock
The current limitation circuit to implement the constant current protection, sensing
pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the
current protection is fold back to decrease the stress of the external components
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator
FSW pinstrapping sets the switching frequency
The RST open collector output
DocID027739 Rev 6
A6986F
Functional description
Figure 3. Internal block diagram
5.1
Power supply and voltage reference
The internal regulator block consists of a start-up circuit, the voltage pre-regulator that
provides current to all the blocks and the bandgap voltage reference. The starter supplies
the startup current when the input voltage goes high and the device is enabled (SS/INH pin
over the inhibits threshold).
The pre-regulator block supplies the bandgap cell and the rest of the circuitry with
a regulated voltage that has a very low supply voltage noise sensitivity.
Switchover feature
The switchover scheme of the pre-regulator block features to derive the main contribution of
the supply current for the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is
typically connected to the regulated output voltage). This helps to decrease the equivalent
quiescent current seen at VIN. (Please refer to Section 5.9: Switchover feature on page 35).
DocID027739 Rev 6
15/79
79
Functional description
5.2
A6986F
Voltages monitor
An internal block continuously senses the VCC, VBIAS and VBG. If the monitored voltages are
good, the regulator starts operating. There is also a hysteresis on the VCC (UVLO).
Figure 4. Internal circuit
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5.3
Soft-start and inhibit
The soft-start and inhibit features are multiplexed on the same pin. An internal current
source charges the external soft-start capacitor to implement a voltage ramp on the SS/INH
pin. The device is inhibited as long as the SS/INH pin voltage is lower than the VINH
threshold and the soft-start takes place when SS/INH pin crosses VSS START. (See Figure 5:
Soft-start phase).
The internal current generator sources 1 A typ. current when the voltage of the VCC pin
crosses the UVLO threshold. The current increases to 4 A typ. as soon as the SS/INH
voltage is higher than the VINH threshold. This feature helps to decrease the current
consumption in inhibit mode. An external open collector can be used to set the inhibit
operation clamping the SS/INH voltage below VINH threshold.
The startup feature minimizes the inrush current and decreases the stress of the power
components during the power-up phase. The ramp implemented on the reference of the
error amplifier has a gain three times higher (SSGAIN) than the external ramp present at
SS/INH pin.
16/79
DocID027739 Rev 6
A6986F
Functional description
Figure 5. Soft-start phase
The CSS is dimensioned accordingly with Equation 1:
Equation 1
I SSCH T SS
4A TSS
C SS = SS GAIN -------------------------------- = 3 --------------------------V FB
0.85V
where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the
error amplifier.
The soft-start block supports the precharged output capacitor.
DocID027739 Rev 6
17/79
79
Functional description
A6986F
Figure 6. Soft-start phase with precharged COUT
During normal operation a new soft-start cycle takes place in case of:
Thermal shutdown event
UVLO event
The device is driven in INH mode
The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 msec time
max. For complete and proper capacitor discharge in case of fault condition, a maximum
CSS = 67 nF value is suggested.
The application example in Figure 7 shows how to enable the A6986F and perform the softstart phase driven by an external voltage step, for example the signal from the ignition
switch in automotive applications.
Figure 7. Enable the device with external voltage step
18/79
DocID027739 Rev 6
A6986F
Functional description
The maximum capacitor value has to be limited to guarantee the device can discharge it in
case of thermal shutdown and UVLO events (see Figure 9), so restart the switching activity
ramping the error amplifier reference voltage.
Equation 2
– 1 msec
C SS ------------------------------------------------------------------------------------------V SS_FINAL – 0.9 V
R SS_EQ ln 1 – ----------------------------------------------
600 A – R SS_EQ
where:
Equation 3
R UP R DWN
R SS_EQ = --------------------------------R UP + R DWN
R DWN
V SS_FINAL = V STEP – V DIODE ---------------------------------R UP + R DWN
The optional diode prevents to disable the device if the external source drops to ground.
RUP value is selected in order to make the capacitor charge at first approximation
independent from the internal current generator (4 A typ. current capability, see Table 5 on
page 8), so:
Equation 4
V STEP – V DIODE – V SS END
----------------------------------------------------------------------- » I SS CHARGE 4 A
R UP
where:
Equation 5
V FB
V SS END = V SS START + --------------------SS GAIN
represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier
(see Figure 5); refer to Table 5 for VSS START, VFB and SSGAIN parameters.
As a consequence the voltage across the soft-start capacitor can be written as:
Equation 6
1
v SS t = V SS_FINAL ----------------------------------------t
1–e
– --------------------------------C SS R SS_EQ
RSS_DOWN is selected to guarantee the device stays in inhibit mode when the internal
generator sources 1 A typ. out of the SS/INH pin and VSTEP is not present:
Equation 7
R DWN I SS INHIBIT R DWN 1 A « V INH 200 mV
so:
Equation 8
R DWN 100 k
DocID027739 Rev 6
19/79
79
Functional description
A6986F
RUP and RDWN are selected to guarantee:
Equation 9
V SS_FINAL 2 V V SS_END
The time to ramp the internal voltage reference can be calculated from Equation 10:
Equation 10
V SS_FINAL – V SS START
T SS = C SS R SS_EQ ln -----------------------------------------------------------
V SS_FINAL – V SS END
that is the equivalent soft-start time to ramp the output voltage.
Figure 8 shows the soft-start phase with the following component selection: RUP = 180 k,
RDWN = 33 k, CSS = 200 nF, the 1N4148 is a small signal diode and VSTEP = 13 V.
Figure 8. External soft-start network VSTEP driven
The circuit in Figure 7 introduces a time delay between VSTEP and the switching activity that
can be calculated as:
Equation 11
V SS_FINAL
T SS DELAY = C SS R SS_EQ ln -----------------------------------------------------------
V SS_FINAL – V SS START
Figure 9 shows how the device discharges the soft-start capacitor after an UVLO or thermal
shutdown event in order to restart the switching activity ramping the error amplifier reference
voltage.
20/79
DocID027739 Rev 6
A6986F
Functional description
Figure 9. External soft-start after UVLO or thermal shutdown
DocID027739 Rev 6
21/79
79
Functional description
5.3.1
A6986F
Ratiometric startup
The ratiometric startup is implemented sharing the same soft-start capacitor for a set of the
A6986F devices.
Figure 10. Ratiometric startup
9
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As a consequence all the internal current generators charge in parallel the external
capacitor. The capacitor value is dimensioned accordingly with Equation 12:
Equation 12
I SSCH T SS
4A T SS
C SS = n A6986F SS GAIN -------------------------------- = n A6986F 3 --------------------------V FB
0.85V
where nA6986F represents the number of devices connected in parallel.
For better tracking of the different output voltages the synchronization of the set of
regulators is suggested.
22/79
DocID027739 Rev 6
A6986F
Functional description
Figure 11. Ratiometric startup operation
DocID027739 Rev 6
23/79
79
Functional description
5.3.2
A6986F
Output voltage sequencing
The A6986F device implements sequencing connecting the RST pin of the master device to
the SS/INH of the slave. The slave is inhibited as long as the master output voltage is
outside regulation so implementing the sequencing (see Figure 12).
Figure 12. Output voltage sequencing
9
9287
9287
9287
W
W'(/$ 0.5
The graphical representation of the input RMS current of the input filter in the case of two
devices with 0° phase shift (synchronized to an external signal) or 180° phase shift
(synchronized connecting their SYNCH pins) regulating the same output voltage is provided
in Figure 45. To dimension the proper input capacitor please refer to Section 7.6.1: Input
capacitor selection on page 57.
52/79
DocID027739 Rev 6
A6986F
Application notes
Figure 45. Input RMS current
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DocID027739 Rev 6
53/79
79
Application notes
A6986F
Figure 46 shows two regulators not synchronized.
Figure 46. Two regulators not synchronized
Figure 47 shows the same regulators working synchronized. The MASTER regulator (LX2
trace) delivers the synchronization signal (SYNCH1, SYNCH2 pins are connected together)
to the SLAVE device (LX1). The SLAVE regulator works in phase with the synchronization
signal which is out of phase with the MASTER switching operation.
Figure 47. Two regulators synchronized
54/79
DocID027739 Rev 6
A6986F
Application notes
Multiple A6986F can be synchronized to an external frequency signal fed to the SYNCH pin.
In this case the regulator set is phased to the reference and all the devices will work with 0°
phase shift.
The frequency range of the synchronization signal is 275 kHz - 1.4 MHz and the minimum
pulse width is 100 nsec (see Figure 48).
Figure 48. Synchronization pulse definition
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Since the slope compensation contribution that is required to prevent subharmonic
oscillations in peak current mode architecture depends on the switching frequency, it is
important to select the same oscillator frequency for all regulators (all of them operate as
SLAVE) as close as possible to the frequency of the reference signal (please refer to
Table 6: fSW selection on page 11). As a consequence all the regulators have the same
resistor value connected to the FSW pin, so the slope compensation is optimized
accordingly with the frequency of the synchronization signal. The slope compensation
contribution is latched at power-up and so fixed during the device operation.
The A6986F normally operates in the MASTER mode, driving the SYNCH line at the
selected oscillator frequency as shown in Figure 49 and Figure 46.
In the SLAVE mode the A6986F sets the internal oscillator at 250 kHz typ. (see Table 6 on
page 11 - first row) and drives the line accordingly.
Figure 49. A6986F synchronization driving capability
In order to safely guarantee that each regulator recognizes itself in SLAVE mode during the
normal operation, the external master must drive the SYNCH pin with a clock signal
DocID027739 Rev 6
55/79
79
Application notes
A6986F
frequency higher than the maximum oscillator spread (refer to Table 6 on page 11) for at
least 10 internal clock cycles.
For example: selecting RFSW = 0 to GND
Table 13. Example of oscillator frequency selection from Table 6
Symbol
RVCC (E24 series)
RGND (E24 series)
fSW min.
fSW typ.
fSW max.
fSW
NC
0
450
500
550
the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it
is able to synchronize to a clock signal in the range 275 kHz - 1.4 MHz (see Figure 48).
Anyway it is suggested to limit the frequency range within ± 20% FSW resistor nominal
frequency (see details in text below). If not spread spectrum is required, all the regulators
synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the
example).
The device keeps operating in slave mode as far as the master is able to drive the SYNCH
pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes
back into MASTER mode at the nominal oscillator frequency after successfully driving one
pulse at 250 kHz (see Figure 50) in the SYNCH line.
Figure 50. Slave to master mode transition
switching node
SLAVE mode
250kHz typ. stand alone operation at nominal fsw
SYNCH signal
The external master can force a latched SLAVE mode driving the SYNCH pin low at powerup, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz
typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise
counts to design the slope compensation. The same considerations above are also valid.
56/79
DocID027739 Rev 6
A6986F
Application notes
The master driving capability must be able to provide the proper signal levels at the SYNCH
pin (see Table 5 on page 8 - Synchronization section):
Low level < VSYN THL= 0.7 V sinking 5 mA
High level > VSYN THH = 1.2 V sourcing 0.7 mA
Figure 51. Master driving capability to synchronize the A6986F
As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the
slope compensation is dimensioned accordingly with FSW resistors so, even if the A6986F
supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is important to limit
the switching operation around a working point close to the selected frequency (FSW
resistor).
As a consequence, to guarantee the full output current capability and to prevent the
subharmonic oscillations the master must limit the driving frequency range within ± 20% of
the selected frequency.
A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the
peak current capability (see IPK parameter in Table 5) since the internal slope compensation
signal may be saturated.
In order to guarantee the synchronization as a slave over distribution, temperature and the
output load, the external clock frequency must be lower than 1.4 MHz.
7.6
Design of the power components
7.6.1
Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage
of the application. During the switching activity a pulsed current flows into the input capacitor
and so its RMS current capability must be selected accordingly with the application
conditions. Internal losses of the input filter depends on the ESR value so usually low ESR
capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so
contributes to higher conversion efficiency.
DocID027739 Rev 6
57/79
79
Application notes
A6986F
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 44
D D
I RMS = I OUT 1 – ---- ---
Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This
function has a maximum at D = 0.5 and, considering = 1, it is equal to IOUT/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 45
V OUT + V LOWSIDE
D MAX = -----------------------------------------------------------------------------------------------V INMIN + V LOWSIDE – V HIGHSIDE
Equation 46
V OUT + V LOWSIDE
D MIN = -------------------------------------------------------------------------------------------------V INMAX + V LOWSIDE – V HIGHSIDE
Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches.
The peak-to-peak voltage across the input filter can be calculated as:
Equation 47
I OUT
D D
V PP = ------------------------- 1 – ---- ---- + ESR I OUT + I L
C IN f SW
In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target
VPP can be written as follows:
Equation 48
I OUT
D D
C IN = -------------------------- 1 – ---- ---V PP f SW
Considering this function has its maximum in D = 0.5:
Equation 49
I OUT
C INMIN = ---------------------------------------------4 V PPMAX f SW
Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter
in the order of 5% VIN_MAX.
58/79
DocID027739 Rev 6
A6986F
Application notes
Table 14. Input capacitors
Manufacturer
TDK
Taiyo Yuden
7.6.2
Series
Size
Cap value (F)
Rated voltage (V)
C3225X7S1H106M
1210
10
50
C3216X5R1H106M
1206
-
-
UMK325BJ106MM-T
1210
-
-
Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage
ripple (please refer to Section 7.6.3). Usually the inductor value is selected in order to keep
the current ripple lower than 20% - 40% of the output current over the input voltage range.
The inductance value can be calculated by Equation 50:
Equation 50
V IN – V OUT
V OUT
I L = ------------------------------ T ON = -------------- T OFF
L
L
Where TON and TOFF are the on and off time of the internal power switch. The maximum
current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 7.6.1: Input capacitor selection to calculate minimum duty). So fixing IL = 20%
to 40% of the maximum output current, the minimum inductance value can be calculated:
Equation 51
V OUT 1 – D MIN
L MIN = ------------------- ----------------------I LMAX
F SW
where fSW is the switching frequency 1/(TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IOUT = 2 A and FSW = 500 kHz the minimum
inductance value to have IL = 30% of IOUT is about 8.2 µH.
The peak current through the inductor is given by:
Equation 52
I L
I L PK = I OUT + -------2
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 15 some inductor part numbers are listed.
Table 15. Inductors
Manufacturer
Series
Inductor value (H)
Saturation current (A)
Coilcraft
XAL50xx
2.2 to 22
6.5 to 2.7
-
XAL60xx
2.2 to 22
12.5 to 4
DocID027739 Rev 6
59/79
79
Application notes
7.6.3
A6986F
Output capacitor selection
The triangular shape current ripple (with zero average value) flowing into the output
capacitor gives the output voltage ripple, that depends on the capacitor value and the
equivalent resistive component (ESR). As a consequence the output capacitor has to be
selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be calculated as:
Equation 53
I LMAX
V OUT = ESR I LMAX + --------------------------------------8 C OUT f SW
Usually the resistive component of the ripple can be neglected if the selected output
capacitor is a multi layer ceramic capacitor (MLCC).
The output capacitor is important also for loop stability: it determines the main pole and the
zero due to its ESR. (see Section 6: Closing the loop on page 42 to consider its effect in the
system stability).
For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.6 A, fSW = 500 kHz (resulting by the
inductor value) and COUT = 10 F MLCC:
Equation 54
V OUT
I LMAX
1
1
0 6
15mV
------------------ -------------- ------------------------------ = ------ -------------------------------------------------- = ---------------- = 0.45%
33 8 10F 500kHz
V OUT V OUT C OUT f SW
3.3
The output capacitor value has a key role to sustain the output voltage during a steep load
transient. When the load transient slew rate exceeds the system bandwidth, the output
capacitor provides the current to the load. In case the final application specifies high slew
rate load transient, the system bandwidth must be maximized and the output capacitor has
to sustain the output voltage for time response shorter than the loop response time.
In Table 16 some capacitor series are listed.
Table 16. Output capacitors
Manufacturer
Series
Cap value (F)
Rated voltage (V)
ESR (m)
GRM32
22 to 100
6.3 to 25
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