ALED6000PHTR

ALED6000 Datasheet Automotive 3 A 61 V monolithic current source with dimming capability Features HTSSOP16 • • • • AECQ100 qualification Up to 3 A DC output current 4.5 V to 61 V operating input voltage RDS(on) =250 mΩ typ. • Adjustable fSW (250 kHz - 1.5 MHz) • • Dimming function with dedicated pin Low IQ shutdown (10 µA typ. from VIN) • Low IQ operating (2.4 mA typ.) • • • • • • • • ±3% output current accuracy overtemperature Synchronization Enable with dedicated pin Adjustable soft-start time Adjustable current limitation Low-dropout operation (12 μs max.) VBIAS improves efficiency at light load Auto recovery thermal shutdown Applications Product status link ALED6000 • • • Suitable for automotive systems HB LED driving applications Halogen bulb replacement Description The ALED6000 is a step down monolithic switching regulator designed to source up to 3 A DC current for high power LED driving. The wide input voltage range makes the ALED6000 the ideal choice for automotive systems. The 250 mV typical RSENSE voltage drop enhances the efficiency performance. Digital dimming is implemented by driving the dedicated DIM pin. The adjustable current limitation, designed to select the inductor RMS current accordingly with the nominal output LEDs current, and the switching frequency adjustability make the size of the application compact. Pulse-by-pulse current sensing, improved by digital frequency scaling, implements an effective constant current protection over the different application conditions. The embedded switchover feature on the VBIAS pin maximizes the efficiency. Multiple devices can be synchronized sharing the SYNCH pin to prevent beating noise in low noise applications and the input current RMS value to be reduced. DS13018 - Rev 1 - October 2019 For further information contact your local STMicroelectronics sales office. www.st.com ALED6000 Application schematic 1 Application schematic Figure 1. Application schematic VIN SYNCH VIN VIN VCC EN CIN SS FSW CVCC CSS ILIM DIM DIM VBIAS BOOT CBOOT ALED6000 L LX LX FB CF RF GND TP COMP VLED+ COUT RU VLED- D CP GND DS13018 - Rev 1 RSNS GND page 2/45 ALED6000 Block diagram 2 Block diagram Figure 2. Block diagram VCC VBIAS VIN BOOT EN EN ENABLE VREG BOOT CHARGE UVLO ISNS REF and BIAS VRAMP 0.25V + FB FB CURRENT SENSING - E/A HS DRIVER -PWM COMP + EN Logic and control TEMP MONITOR OUT SOFT START LS DRIVER ISS SS DIMMING VRAMP DIM OSCILLATOR & RAMP COMP DS13018 - Rev 1 FSW MASTER SLAVE SYNCH ILIM FUNCTION GND ILIM page 3/45 ALED6000 Pin settings 3 Pin settings 3.1 Pin connection Figure 3. Pin connection (top view) 3.2 VBIAS 1 16 GND VIN 2 15 BOOT VIN 3 14 LX VCC 4 13 LX EN 5 12 DIM SS 6 11 ILIM SYNCH 7 10 FSW COMP 8 9 EXPOSED PAD TO SGND FB Pin description Table 1. Pin description # DS13018 - Rev 1 Pin Description 1 VBIAS Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency at light load. Connect to GND if not used or bypass with a 1 µF ceramic capacitor if supplied by an auxiliary rail 2 VIN DC input voltage 3 VIN DC input voltage 4 VCC Filtered DC input voltage to the internal circuitry. Bypass to the signal GND by a 1 µF ceramic capacitor 5 EN Active high enable pin. Connect to VCC pin if not used 6 SS An internal current generator (5 µA typ.) charges the external capacitor to implement the soft-start 7 SYNCH Master / slave synchronization 8 COMP Output of the error amplifier. The designed compensation network is connected on this pin 9 FB Inverting input of the error amplifier 10 FSW A pull-down resistor to GND selects the switching frequency 11 ILIM A pull-down resistor to GND selects the peak current limitation page 4/45 ALED6000 Maximum ratings # 3.3 Pin Description A PWM signal in this input pin implements the LED PWM current dimming. It is pulled-down by internal 2 µA current 12 DIM 13 LX Switching node 14 LX Switching node Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge required to drive the internal n-DMOS is recovered by an internal regulator during the off-time 15 BOOT 16 GND Signal GND -- E.P. Exposed pad must be connected to GND plane Maximum ratings Stressing the device above the rating listed in may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute maximum ratings Symbol Min. Max. Unit VIN -0.3 61 V VCC -0.3 61 V VBOOT - GND -0.3 65 V VBOOT – VLX -0.3 4 V VBIAS -0.3 VCC V EN -0.3 VCC V DIM -0.3 VCC V LX -0.3 VIN+0.3 V SYNCH -0.3 5.5 V SS -0.3 3.6 V FSW -0.3 3.6 V COMP -0.3 3.6 V ILIM -0.3 3.6 V FB -0.3 3.6 V BOOT DS13018 - Rev 1 Description TJ Operating temperature range -40 150 °C TSTG Storage temperature range -65 150 °C TLEAD Lead Temperature (soldering 10 s) 260 °C IHS High-side RMS current 3 A page 5/45 ALED6000 Thermal data 3.4 Thermal data Table 3. Thermal data Symbol RthJA 3.5 Parameter Thermal resistance junction-ambient (device soldered on the STMicroelectronics demonstration board) Value Unit 40 °C/W ESD protection Table 4. ESD protection Symbol ESD DS13018 - Rev 1 Test conditions Value Unit HBM 2 kV CDM 500 V page 6/45 ALED6000 Electrical characteristics 4 Electrical characteristics TJ = -40 to +125 °C, VIN = VCC = 24 V and VDIM=VEN =3 V unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter VIN Operating input voltage range RDSON HS High-side RDSON fSW IPK Test conditions Min. Typ. 4.5 Max. Unit 61 V ILX=0.5 A; TJ = 25 °C 0.25 0.32 Ω ILX=0.5 A 0.25 0.46 Ω FSW pin floating; TJ = 25 °C 233 250 267 kHz FSW pin floating 225 250 275 kHz Selected switching frequency RFSW=10 kΩ 1350 1500 1650 kHz Peak current limit ILIM pin floating; VFB = 0 V (1) 3.4 4.1 4.8 A Selected peak current limit RILIM=100 kΩ; VFB = 0 V (1) 0.69 0.84 1.00 A ILIM pin floating (1) 0.40 A RILIM=100 kΩ (1) 0.15 A Switching frequency ISKIP Pulse skipping peak current TONMIN Minimum on-time TONMAX Maximum on-time TOFFMIN Minimum off-time 120 Refer to Functional description section for TONMAX details. (2) 150 ns 12 μs 360 ns VCC / VBIAS VCCH VCC UVLO rising threshold 3.85 4.10 4.30 V VCCHYST VCC UVLO hysteresis 150 250 380 mV 2.84 2.90 3.03 V VBIAS threshold SWO VCC -VBIAS threshold Switch internal supply from VIN to VBIAS Hysteresis Switch internal supply from VCC to VBIAS. VIN=VCC=24 V, VBIAS falling from 24 V to GND 80 3.35 Hysteresis 4.05 mV 4.90 900 V mV Power consumption ISHTDWN Shutdown current from VIN IQUIESC Quiescent current from VIN and VCC IQOPVIN Quiescent current from VIN and VCC IQOPVBIAS Quiescent current from VBIAS VEN = GND; TJ=25 °C 11 16 μA VEN = GND 23 45 μA LX floating, VFB=1 V, VBIAS=GND, FSW floating 2.5 3.0 mA 1.0 1.3 mA 1.6 2.2 mA LX floating, VFB=1 V, VBIAS=3.3 V, FSW floating Enable VENL Device OFF level 0.06 0.30 V VENH Device ON level 0.35 0.90 V Soft-start DS13018 - Rev 1 page 7/45 ALED6000 Electrical characteristics Symbol Parameter Test conditions TSSSETUP Soft-start set-up time Delay from UVLO rising to switching activity ISSCH CSS charging current VSS=GND Min. (2) Typ. Max. Unit 640 4.3 5.0 μs 5.7 μA Error amplifier VFB TJ = 25 °C Voltage feedback VCOMPH VFB = GND; VSS =3.2 V VCOMPL VFB = 3.6 V; VSS = 3.2 V IFB FB biasing current IOSOURCE IOSINK V 0.240 0.250 0.260 V 3.00 3.65 V 0.1 V 50 nA VFB = 3.6 V VFB = GND; SS pin floating; VCOMP = 2 V Output stage sinking capability 0.242 0.250 0.258 Unity gain buffer configuration (FB connected to COMP). COMP voltage variation due to IOSINK injection lower than 3.35 5 (2) 3.1 mA (2) 5.0 mA (2) 100 dB (2) 23 MHz ± 0.1·VFB AV0 Error amplifier gain Unity gain buffer configuration (FB connected to COMP). No load on COMP pin GBWP Synchronization (fan out: 5 slave devices max.) fSYN MIN Synchronization frequency VSYNOUT Master output amplitude VSYNOW Output pulse width VSYNIH VSYNIL Pin FSW pin floating 280 ILOAD = 4 mA 2.45 ILOAD = 0 A; pin SYNCH floating 4.0 ILOAD = 0 A; pin SYNCH floating 150 Slave SYNCH pull-down current VSYNIW Input pulse width 225 275 2.0 SYNCH slave input threshold ISYN kHz 1.0 VSYNCH = 5 V 400 650 900 150 V ns V μA ns Dimming VDIMH DIM rising threshold VDIML DIM falling threshold VDIMPD DIM pull-down current TDIMTO Dimming timeout 1.23 VDIM = 2 V 0.75 1.00 0.5 1.5 1.70 V V 2.5 μA (2) 42 ms Thermal shutdown TSHDWN Thermal shutdown temperature (2) 170 °C THYS Thermal shutdown hysteresis (2) 15 °C 1. Parameters tested in static condition during testing phase. The parameter value may change over dynamic application conditions. 2. Not tested in production. DS13018 - Rev 1 page 8/45 ALED6000 Functional description 5 Functional description The ALED6000 is based on a voltage mode, constant frequency control loop. The LED current, monitored through the voltage drop on the external current sensing resistor, RSNS, is compared to an internal reference (0.25 V) providing an error signal on the COMP pin. The COMP voltage level is then compared to a fixed frequency sawtooth ramp, which finally controls the on- and off-time of the power switch. The main internal blocks are shown in the block diagram in Figure 2. Block diagram and can be summarized as follows: • The fully integrated oscillator that provides the sawtooth ramp to modulate the duty cycle and the synchronization signal. Its switching frequency can be adjusted by an external resistor. The input voltage feed-forward is implemented • The soft-start circuitry to limit inrush current during the start-up phase • The voltage mode error amplifier • The pulse width modulator and the relative logic circuitry necessary to drive the internal power switch • The high-side driver for embedded N-channel power MOSFET switch and bootstrap circuitry. A dedicated high-resistance low-side MOSFET, for anti-boot discharge management purposes, is also present • The peak current limit sensing block, with programmable threshold, to handle overload including a thermal shutdown block, to prevent thermal runaway • The bias circuitry, which includes a voltage regulator and internal reference, to supply the internal circuitry and provide a fixed internal reference and manages the current dimming feature. The switchover function from VCC to VBIAS can be implemented for higher efficiency. This block also implements a voltage monitor circuitry (UVLO) that checks the input and internal voltages 5.1 Oscillator and synchronization Figure 4. Oscillator and synchronization shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock, whose frequency depends on the resistor externally connected between the FSW pin and ground. Figure 4. Oscillator and synchronization clock FSW 180° phase shift Clock Generator Synchronization Ramp Generator SYNCH Sawtooth If the FSW pin is left floating, the programmed frequency is 250 kHz (typ.); if FSW pin is connected to an external resistor the programmed switching frequency can be increased up to 1.5 MHz, as shown in Figure 5. Switching frequency programmability . The required RFSW value (expressed in kΩ) is estimated by the equation below : 12500 FSW = 250kHz + RFSW DS13018 - Rev 1 (1) page 9/45 ALED6000 Oscillator and synchronization Fsw [kHz] Figure 5. Switching frequency programmability 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 10 20 30 40 50 60 70 80 90 100 RFSW [kΩ] To improve the line transient performance, keeping the PWM gain constant versus the input voltage, the input voltage feed-forward is implemented by changing the slope of the saw-tooth ramp, according to the input voltage change (Figure 6. Feed-forward a). The slope of the sawtooth also changes if the oscillator frequency is programmed by the external resistor. In this way a frequency feed-forward is implemented (Figure 6. Feed-forwardb) in order to keep the PWM modulator gain constant versus the switching frequency. On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of 180° with respect to the clock. This delay is useful when two devices are synchronized connecting the SYNCH pins together. When SYNCH pins are connected, the device with a higher oscillator frequency works as master, so the slave device switches at the frequency of the master but with a delay of half a period. This helps reducing the RMS current flowing through the input capacitor. Up to five ALED6000s can be connected to the same SYNCH pin; however, the clock phase-shift from master switching frequency to slave input clock is 180°. The ALED6000 device can be synchronized to work at a higher frequency, in the range 250 kHz-1500 kHz, providing an external clock signal on SYNCH pin. The synchronization changes the saw-tooth amplitude, also affecting the PWM gain (Figure 6. Feed-forwardc). This change must be taken into account when the loop stability is studied. In order to minimize the change of PWM gain, the free-running frequency should be set (with a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-adjusting of the slave IC switching frequency keeps the truncation of the ramp saw-tooth negligible. In case two or more (up to five) ALED6000 SYNCH pins are tied together, the ALED6000 IC with higher programmed switching frequency is typically the master device; however, the SYNCH circuit is also able to synchronize with a slightly lower external frequency, so the frequency pre-adjustment with the same resistor on the FSW pin, as suggested above, is required for a proper operation. The SYNCH signal is provided as soon as EN is asserted high; however, if DIM is kept low for more than TDIMTO timeout, the SYNCH signal is no more available until DIM re-assertion high. DS13018 - Rev 1 page 10/45 ALED6000 Soft-start Figure 6. Feed-forward Ton VIN a*VIN Ton/a a*Vs Vs Vcomp T Ramp slope = Vs/T T Ramp slope = a*Vs/T a) Voltage feed forward Ton Fsw a*Fsw Ton/a Vs Vs Vcomp T Ramp slope = Vs/T T/a Ramp slope = a*Vs/T b) Fsw adjusted by external resistor Ton Fsw a*Fsw Vs Vcomp T Ramp slope = Vs/T Ton/a Vcomp Vs T/a Ramp slope = Vs/T c) Synchronized by external clock signal 5.2 Soft-start The soft-start is essential to assure a correct and safe start-up of the step-down converter. It avoids inrush current surge and makes the output voltage increase monotonically. The soft-start is performed as soon as EN and DIM pin are asserted high; when this occurs, an external capacitor, connected between SS pin and ground, is charged by a constant current (5 µA typ.). The SS voltage is used as reference of the switching regulator and the output voltage of the converter tracks the ramp of the SS voltage. When the SS pin voltage reaches 0.25 V level, the error amplifier switches to the internal 0.25 V reference to regulate the output voltage. DS13018 - Rev 1 page 11/45 ALED6000 Digital dimming Figure 7. Soft-start Vref 250 mV Iss SS Css + + ERROR VLED+ COMP AMPLIFIER - Rf Cp FB Cf Ru RSNS During the soft-start period the current limit is set to the nominal value. The dVSS/dt slope is programmed in agreement with the following equation: CSS = ISS ⋅ TSS 5μA ⋅ TSS = VREF 0.25V (2) Before starting the CSS capacitor charge, the soft-start circuitry turns on the discharge switch shown in Figure 7. Soft-start for TSSDISCH minimum time, in order to completely discharge the CSS capacitor. As a consequence, the maximum value for the soft-start capacitor, which assures an almost complete discharge in case of EN signal toggle, is provided by: TSSDISCH CSS_MAX ≤ ≅ 270nF 5 ⋅ RSSDISCH (3) given TSSDISCH=530 µs and RSSDISCH=380 Ω typical values. The enable feature allows the device to be put in standby mode. With the EN pin lower than VENL the device is disabled and the power consumption is reduced to less than 10 μA (typ.). If the EN pin is higher than VENH, the device is enabled. If the EN pin is left floating, an internal pull-down current ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also VCC compatible. 5.3 Digital dimming The switching activity is inhibited as long as DIM pin is kept below VDIML threshold. When DIM is asserted low, the HS MOS is turned off as soon as the minimum on-time is expired and the COMP pin is parked close to the maximum ramp peak value, in order to limit the input inrush current when the IC restart the switching activity. The internal oscillator and, consequently, the IC quiescent current are reduced only if DIM is kept low for more than TDIMTO timeout. When DIM is forced above the VDIMH threshold after TDIMTO has elapsed, a new soft-start sequence is performed. The inductor current dynamic performance, when dimming input goes high, depends on the designed system response. The best dimming performance is obtained by maximizing the bandwidth and phase margin, when possible. As a general rule, the output capacitor minimization improves dimming performance in terms of shorter LEDs current rising time and reduced inductor peak current . An oversized output capacitor value requires extra current for fast charge so generating an inductor current overshoot and oscillations. DS13018 - Rev 1 page 12/45 ALED6000 Digital dimming Refer also to Section 6.2 Output capacitor and inductor selection for output capacitor design hints. The dimming performance depends on the current pulse shape specification of the final application. Figure 8. Dimming operation I LED t fall t rise DIM TLED TDIM The ideal current pulse has rectangular shape; however, in any case it degenerates into a trapezoid or, at worst, into a triangle, depending on the ratio (tRISE + tFALL)/ TLED. Figure 9. Dimming operation (rising edge) – VIN=44 V, 12 LED DS13018 - Rev 1 page 13/45 ALED6000 Digital dimming Figure 10. Dimming operation (falling edge) – VIN=44 V, 12 LED In Figure 11. Dimming operation – short DIM pulse a very short DIM pulse is shown, measured in the standard demoboard, VIN=44 V, 12 LEDs. The programmed LED current, 1 A, is reached at the end of the DIM pulse (35 µs). Figure 11. Dimming operation – short DIM pulse DS13018 - Rev 1 page 14/45 ALED6000 Error amplifier and light-load management The above consideration is crucial when short DIM pulses are expected in the final application. Once the external power components and the compensation network are selected, a direct measurement to determine tRISE and tFALL is necessary to certify the achieved dimming performance. When DIM is forced above the VDIMH threshold after TDIMTO has elapsed, a new soft-start sequence is performed. 5.4 Error amplifier and light-load management The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the pulse width modulation. Its non inverting input is internally connected to a 0.25V voltage reference and its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier, therefore, with high DC gain and low output impedance. The uncompensated error amplifier characteristics are summarized in Table 6. Error amplifier characteristics . Table 6. Error amplifier characteristics Parameters Value Low frequency gain (A0) 100 dB GBWP 23 MHz Output voltage swing Source/sink current capability 0 to 3.5V 3.1 mA / 5 mA In continuous conduction working mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. If the zero introduced by the output capacitor helps to compensate the double pole of the LC filter, a type II compensation network can be used. Otherwise, a type III compensation network must be used (see Section 6.3 Compensation strategy for details on the compensation network design). In case of light load (i.e. if the output current is lower than the half of the inductor current ripple) the ALED6000 enters pulse-skipping working mode. The HS MOS is kept off if the COMP level is below 200 mV (typ.); when this bottom level is reached the integrated switch is turned on until the inductor current reaches ISKIP value. So, in discontinuous conduction working mode (DCM), the HS MOS on-time is only related to the time necessary to charge the inductor up to ISKIP level. ISKIP threshold is reduced with increasing RILIM resistor value, as shown also in Table 5. Electrical characteristics and plotted in Figure 12. ISKIP typical current and RILIM value , so allowing the ALED6000 to work in continuous conduction mode also in case lower current LEDs is selected. DS13018 - Rev 1 page 15/45 ALED6000 Low VIN operation Figure 12. ISKIP typical current and RILIM value ISKIP current [mA] 550 500 450 400 350 300 250 200 150 100 20 30 40 50 60 70 80 90 100 RILIM [kΩ] However, due to current sensing comparator delay, the actual inductor charge current is slightly impacted by VIN and selected inductor value. In order to let the bootstrap capacitor recharge, in case of extremely light load the ALED6000 is able to pull-down the LX net through an integrated small LS MOS. In this way the bootstrap recharge current can flow from VIN through CBOOT, LX and the LS MOS. This mechanism is activated if the HS MOS has been kept turned-off for more than 3 ms (typ.). 5.5 Low VIN operation In normal operation (i.e. VOUT programmed lower than input voltage) when the HS MOS is turned off, a minimum off-time (TOFFMIN) interval is performed. In case the input voltage falls close or below the programmed output voltage (low-dropout, LDO) the ALED6000 control loop is able to increase the duty cycle up to 100%. However, in order to keep the boot capacitor properly recharged, a maximum HS MOS on-time is limited (TONMAX). When this limit is reached the HS MOS is turned off and an integrated switch working as pull-down resistor between LX and GND is turned on, until one of the following conditions is met: • A negative current limit (300 mA typ.) is reached • timeout (1 μs typ.) is reached So doing the ALED6000 device is able to work in low-dropout operation, due to the advanced boot capacitor management, and the effective maximum duty cycle is about 12 μs / 13 μs = 92%. 5.6 Overcurrent protection The ALED6000 implements overcurrent protection by sensing the current flowing through the power MOSFET. Due to the noise created by the switching activity of the power MOSFET, the current sensing circuitry is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time”. The masking time is about 120 ns. If the overcurrent limit is reached, the power MOSFET is turned off implementing pulse-by-pulse overcurrent protection. In the overcurrent condition, the device can skip turn-on pulses in order to keep the output current constant and equal to the current limit. If, at the end of the “masking time”, the current is higher than the overcurrent threshold, the power MOSFET is turned off and one pulse is skipped. If, at the following switching on, when the “masking time” ends, the current is still higher than the overcurrent threshold, the device skips two pulses. This mechanism is repeated and the device can skip up to seven pulses (refer to Figure 13. OCP and frequency scaling). DS13018 - Rev 1 page 16/45 ALED6000 Overcurrent protection If at the end of the “masking time” the current is lower than the overcurrent threshold, the number of skipped cycles is decreased by one unit. As a consequence, the overcurrent protection acts by turning off the power MOSFET and reducing the switching frequency down to one eighth of the default switching frequency, in order to keep constant the output current close to the current limit. Figure 13. OCP and frequency scaling I_LIM I_IND Ton Tmask Up to seven clock pulses can be skipped This kind of overcurrent protection is effective if the inductor can be completely discharged during HS MOS turnoff time, in order to avoid the inductor current to run away. In case of output short-circuit the maximum switching frequency can be computed by the following equation: 8 ⋅ VF + RDCR ⋅ ILIM 1 FSW, MAX ≤ ⋅ VIN − RON + RDCR ⋅ ILIM TON, MIN (4) Assuming VF = 0.6 V the free-wheeling diode direct voltage, RDCR = 30 mΩ the inductor parasitic resistance, ILIM=IPK = 4 A the peak current limit, RON = 0.25 Ω the HS MOS resistance and TON,MIN = 120 ns the minimum HS MOS on duration, the maximum FSW frequency which avoids the inductor current run away in case of output short-circuit and VIN = 61 V is 801 kHz. If the programmed switching frequency is higher than the above computed limit, an estimation of the inductor current in case of output short-circuit fault is provided by the equation below: FSW ⋅ TON ⋅ VIN − 8 ⋅ VF ILIM = 8 ⋅ RDCR + FSW ⋅ TON, MIN RON + RDCR (5) The peak current limit threshold (ILIM) can be programmed in the range 0.85 A-4.0 A by selecting the proper RILIM resistor, as suggested below: IPK RILIM = 20kΩ ⋅ ILIM (6) IPK is the default ALED6000 current limit in case of RILIM not mounted, as shown in Table 5. Electrical characteristics . DS13018 - Rev 1 page 17/45 ALED6000 Overtemperature protection Figure 14. Current limit and programming resistor 4.500 IPK threshold [A] 4.00 3.500 3.00 2.500 2.00 1.500 1.00 .500 20 30 40 50 60 70 80 90 100 RILIM [kΩ] 5.7 Overtemperature protection It is recommended that the device never exceeds the maximum allowable junction temperature. This temperature increase is mainly caused by the total power dissipated by the integrated power MOSFET. To avoid any damage to the device when reaching high temperature, the ALED6000 implements a thermal shutdown feature: when the junction temperature reaches 170 °C (typ.) the device turns off the power MOSFET and shuts down. When the junction temperature drops to 155 °C (typ.), the device restarts with a new soft-start sequence. DS13018 - Rev 1 page 18/45 ALED6000 Application information 6 Application information 6.1 Input capacitor selection The input capacitor must be rated for the maximum input operating voltage and the maximum RMS input current. Since the step-down converters input current is a sequence of pulses from 0 A to IOUT, the input capacitor must absorb the equivalent RMS current which can be up to the load current divided by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors must be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The RMS input current (flowing through the input capacitor) in step-down conversion is roughly estimated by: ICIN, RMS ≅ IOUT ⋅ D ⋅ 1 − D (7) Actual DC/DC conversion duty cycle, D=VOUT/VIN, is influenced by a few parameters: VOUT + VF DMAX = VIN, MIN − VSW, MAX VOUT + VF DMIN = VIN, MAX − VSW, MIN (8) where VF is the freewheeling diode forward voltage and VSW the voltage drop across the internal high-side MOSFET. Considering the range DMIN to DMAX it is possible to determine the maximum ICIN,RMS flowing through the input capacitor. The input capacitor value must be dimensioned to safely handle the input RMS current and to limit the VIN and VCC ramp-up slew-rate to 0.5 V/µs maximum, in order to avoid the device active ESD protections turn-on. Different capacitors can be considered: • Electrolytic capacitors These are the most commonly used due to their low cost and wide range of operative voltage. The only drawback is that, considering ripple current rating requirements, they are physically larger than other capacitors. • Ceramic capacitors If available for the required value and voltage rating, these capacitors usually have a higher RMS current rating for a given physical dimension (due to the very low ESR). The drawback is their high cost. • Tantalum capacitor Small, good quality tantalum capacitors with very low ESR are becoming more available. However, they can occasionally burn if subjected to very high current, for example when they are connected to the power supply. The amount of the input voltage ripple can be roughly overestimated by the following equation:. VIN, PP = D ⋅ 1 − D ⋅ IOUT + RES, IN ⋅ IOUT CIN ⋅ FSW (9) In case of MLCC ceramic input capacitors, the equivalent series resistance (RES,IN) is negligible. In addition to the above considerations, a ceramic capacitor with an appropriate voltage rating and with a value 1 µF or higher should always be placed across VIN and power ground and across VCC and the IC GND pins, as close as possible to the ALED6000 device. This solution is necessary for spike filtering purposes. 6.2 Output capacitor and inductor selection The output capacitor is very important in order to satisfy the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. DS13018 - Rev 1 page 19/45 ALED6000 Output capacitor and inductor selection The current in the output capacitor has a triangular waveform, which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements. The allowed LED current ripple (∆ILED,PP) is typically 2% to 5% of the LED DC current. Figure 15. LED small signal model LX RDC L V LED+ LX RDC L V LED+ RD RES RES CO CO RSNS RD RSNS Based on the small signal model typically adopted for LEDs (as shown in Figure 15. LED small signal model), the amount of the inductor current ripple which flows through the LEDs can be estimated by the following equation: 1 + sC0RES ΔILED s = ΔIL s ⋅ 1 + sC0 ⋅ (RES + RSNS + N ⋅ Rd) (10) The typical LED dynamic resistance, for high-current LEDs, is about 0.9 Ω to 1 Ω. The output capacitor, CO, is typically an MLCC ceramic capacitor in the range of 1 µF and with equivalent series resistance lower than 10 mΩ, as a consequence the zero due to the time constant CO*RES is in the range of 10 MHz or above. Starting from Eq. (10) it is possible to roughly estimate the required CO value: 8 1 ⋅ ΔIL, PP ⋅ C0 ≥ 2π ⋅ fSW ⋅ RSNS + N ⋅ Rd ⋅ ΔILED, PP π2 (11) In the above equation it has been assumed that the total inductor current ripple is well-approximated by the first Fourier harmonic, 8/π2*∆IL,PP, due to the inductor current triangular shape. The inductance value fixes the current ripple flowing through the output capacitor and LEDs. So the minimum inductance value, in order to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 40%-60% of the programmed LEDs current. In the continuous conduction mode (CCM), the required inductance value can be calculated by the following equation: VOUT VOUT ⋅ 1 − VIN L= ΔIL ⋅ FSW (12) In order to guarantee a maximum current ripple in every condition, Eq. (12) must be evaluated in case of maximum input voltage, assuming VOUT fixed. Increasing the value of the inductance helps to reduce the current ripple but, at the same time, strongly impacts the converter response time in case of high-frequency dimming requirements. On the other hand, with lower inductance value the regulator response time is improved but the power conversion efficiency is impacted and the output capacitor must be increased to limit the current ripple flowing through the LEDs. As usual, the L-CO choice is a trade-off among multiple design parameters. DS13018 - Rev 1 page 20/45 ALED6000 Compensation strategy 6.3 Compensation strategy The compensation network must assure stability and good dynamic performance. The loop of the ALED6000 is based on the voltage mode control. The error amplifier is an operational amplifier with high bandwidth. So, by selecting the compensation network the E/A is considered as ideal, that is, its bandwidth is much larger than the system one. Figure 16. Switching regulator control loop simplified model L V IN RDC LX Internal switch Power section RES RD1 CO RD2 RSNS V REF PWM ZS VS COMP EA FB ZF Compensation network The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the LX pin results in an almost constant gain, due to the voltage feed-forward which generates a sawtooth with amplitude VS directly proportional to the input voltage: 1 1 GPWO = = VS KFF ⋅ VIN (13) The synchronization of the device with an external clock provided through the SYNCH pin can modify the PWM modulator gain (see Section 5.1 Oscillator and synchronization to understand how this gain changes and how to keep it constant in spite of the external synchronization). The transfer function of the power section (i.e. the voltage across RSNS resulting as a variation of the duty cycle) is: GLC s = VSNS s = d s RSNS ⋅ VIN RSNS + s ⋅ L + RDC + N ⋅ Rd / / 1 + s ⋅ C0 ⋅ RES s ⋅ C0 (14) given L, RDC, CO, RES, RSNS and Rd the parameters shown in Figure 16. Switching regulator control loop simplified model . The power section transfer function can be rewritten as follows: DS13018 - Rev 1 page 21/45 ALED6000 Compensation strategy GLC s = GLC0 ⋅ 1+ s 2π ⋅ fz 2 s s 1+ + 2π ⋅ Q ⋅ fLC 2π ⋅ fLC 1 fz = ;f ≅ 2π ⋅ C0 ⋅ RES + N ⋅ Rd LC Q≅ ; GLC0 ≅ 1 RSNS ⋅ VIN RSNS + N ⋅ Rd (15) (16) N ⋅ Rd 2π LC0 N ⋅ Rd + RSNS LC0 ⋅ RSNS + N ⋅ Rd ⋅ N ⋅ Rd L + C0 ⋅ RSNS ⋅ N ⋅ Rd (17) with the assumption that the inductor parasitic resistance, RDC, and the output capacitor parasitic resistance, RES, are negligible compared to LED dynamic resistance, Rd. The closed loop gain is then given by: GLOOP s = GLC s ⋅ GPWO s ⋅ GCOMP s (18) As shown in Eq. (16) , fz depends on the output capacitor parasitic resistance and on the LEDs dynamic resistance. Following the considerations summarized in Section 6.2 Output capacitor and inductor selection , in the typical application the programmed control loop bandwidth (BW) might be higher than fz, so this zero helps stabilize the loop. If this assumption is verified, a type II compensation network is required for loop stabilization. In Figure 17. Type II compensation network the type II compensation network is shown. Figure 17. Type II compensation network V REF COMP EA FB RU CF RF CP V SNS RSNS ZF The type II compensation network transfer function, from VSNS to COMP, is computed in Eq. (19) . ZF s 1 + sCFRF 1 GCOMPII s = − = − = −1 ⋅ RU RU s ⋅ CF + CP ⋅ 1 + sCF / /CPRF ⋅ 1+ (19) s 2π ⋅ fZ1 s s ⋅ 1+ 2π ⋅ fPO 2π ⋅ fP1 1 1 1 fZ1 = ;f = ;f = 2π ⋅ CFRF P0 2π ⋅ CF + CP ⋅ RU P1 2π ⋅ CF / /CPRF (20) The following suggestions can be followed for a quite common compensation strategy, assuming that CP