L6206
DMOS dual full bridge driver
Datasheet - production data
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Applications
Bipolar stepper motor
Dual or quad DC motor
3RZHU62
Description
The L6206 device is a DMOS dual full bridge
designed for motor control applications, realized
in BCD technology, which combines isolated
DMOS power transistors with CMOS and bipolar
circuits on the same chip. Available in the
PowerSO36 and SO24 (20 + 2 + 2) packages, the
L6206 device features thermal shutdown and a
non-dissipative overcurrent detection on the highside power MOSFETs plus a diagnostic output
that can be easily used to implement the
overcurrent protection.
62
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Features
Operating supply voltage from 8 to 52 V
5.6 A output peak current (2.8 A DC)
RDS(ON) 0.3 typ. value at Tj = 25 °C
Operating frequency up to 100 KHz
Programmable high-side overcurrent detection
and protection
Diagnostic output
Paralleled operation
Cross conduction protection
October 2018
This is information on a product in full production.
DocID07617 Rev 4
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www.st.com
Contents
L6206
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
7
8
2/29
5.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 13
5.4
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 21
6.3
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DocID07617 Rev 4
L6206
1
Block diagram
Block diagram
Figure 1. Block diagram
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29
Maximum ratings
2
L6206
Maximum ratings
Table 1. Absolute maximum ratings
Symbol
VS
VOD
Parameter
Supply voltage
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
Test conditions
Value
Unit
VSA = VSB = VS
60
V
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB = GND
60
V
-
-0.3 to +10
V
-
-0.3 to +7
V
VSA = VSB = VS
VS + 10
V
OCDA,OCDB OCD pins voltage range
PROGCLA,
PROGCLB
VBOOT
PROGCL pins voltage range
Bootstrap peak voltage
VIN, VEN
Input and enable voltage range
-
-0.3 to +7
V
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
-
-1 to +4
V
Pulsed supply current (for each VS pin),
internally limited by the overcurrent
protection
VSA = VSB = VS;
tPULSE < 1 ms
7.1
A
RMS supply current (for each VS pin)
VSA = VSB = VS
2.8
A
-
-40 to 150
C
IS(peak)
IS
Tstg, TOP
Storage and operating temperature range
Table 2. Recommended operating conditions
Symbol
VS
Parameter
Supply voltage
Test conditions
Min.
Max.
Unit
VSA = VSB = VS
8
52
V
VOD
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
-
52
V
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
(pulsed tW < trr)
(DC)
-6
-1
6
1
V
V
4/29
IOUT
RMS output current
-
-
2.8
A
fsw
Switching frequency
-
-
100
KHz
DocID07617 Rev 4
L6206
Maximum ratings
Table 3. Thermal data
Symbol
Description
Rth-j-pins
Maximum thermal resistance junction pins
Rth-j-case
Maximum thermal resistance junction case
(1)
SO24
PowerSO36
Unit
14
-
C/W
-
1
C/W
51
-
C/W
Rth-j-amb1
Maximum thermal resistance junction ambient
Rth-j-amb1
Maximum thermal resistance junction ambient(2)
-
35
C/W
Rth-j-amb1
Maximum thermal resistance junction ambient
(3)
-
15
C/W
Maximum thermal resistance junction ambient
(4)
77
62
C/W
Rth-j-amb2
1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2
(with a thickness of 35 µm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2
(with a thickness of 35 µm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2
(with a thickness of 35 µm), 16 via holes and a ground layer.
4. Mounted on a multilayer FR4 PCB without any heatsinking surface on the board.
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Pin connections
3
L6206
Pin connections
Figure 2. Pin connections (top view)
GND
1
36
GND
N.C.
2
35
N.C.
N.C.
3
34
N.C.
VSA
4
33
VSB
OUT2A
5
32
OUT2B
N.C.
6
31
N.C.
VCP
7
30
VBOOT
ENA
8
29
ENB
PROGCLA
IN1A
1
24
PROGCLA
IN2A
2
23
ENA
SENSEA
3
22
VCP
OCDA
4
21
OUT2A
OUT1A
5
20
VSA
9
28
PROGCLB
GND
6
19
GND
IN1A
10
27
IN2B
GND
7
18
GND
IN2A
11
26
IN1B
OUT1B
8
17
VSB
SENSEA
12
25
SENSEB
13
24
OCDB
9
16
OUT2B
OCDA
OCDB
N.C.
14
23
N.C.
SENSEB
10
15
VBOOT
OUT1A
15
22
OUT1B
IN1B
11
14
ENB
N.C.
16
21
N.C.
IN2B
12
13
PROGCLB
N.C.
17
20
N.C.
GND
18
19
GND
D99IN1089A
D99IN1090A
PowerSO36(1)
SO24
1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).
Table 4. Pin description
Package
6/29
SO24
PowerSO36
Name
Type
Function
Pin no.
Pin no.
1
10
IN1A
Logic input
Bridge A logic input 1.
2
11
IN2A
Logic input
Bridge A logic input 2.
3
12
SENSEA
Power supply
Bridge A source pin. This pin must be connected
to power ground directly or through a sensing
power resistor.
Bridge A overcurrent detection and thermal
protection pin. An internal open drain transistor
pulls to GND when overcurrent on bridge A is
detected or in case of thermal protection.
4
13
OCDA
Open drain
output
5
15
OUT1A
Power output
Bridge A output 1.
6, 7, 18, 19
1, 18, 19, 36
GND
GND
Signal ground terminals. In SO packages, these
pins are also used for heat dissipation toward the
PCB.
8
22
OUT1B
Power output
Bridge B output 1.
DocID07617 Rev 4
L6206
Pin connections
Table 4. Pin description (continued)
Package
SO24
PowerSO36
Pin no.
Pin no.
Name
Type
Function
Bridge B overcurrent detection and thermal
protection pin. An internal open drain transistor
pulls to GND when overcurrent on bridge B is
detected or in case of thermal protection.
9
24
OCDB
Open drain
output
10
25
SENSEB
Power supply
Bridge B source pin. This pin must be connected
to power ground directly or through a sensing
power resistor.
11
26
IN1B
Logic input
Bridge B input 1
12
27
IN2B
Logic input
Bridge B input 2
13
28
PROGCLB
R pin
Bridge B overcurrent level programming. A
resistor connected between this pin and ground
sets the programmable current limiting value for
the bridge B. By connecting this pin to ground
the maximum current is set. This pin cannot be
left non-connected.
14
29
ENB
Logic input
Bridge B Enable. LOW logic level switches OFF
all power MOSFETs of Bridge B.
If not used, it has to be connected to +5 V.
15
30
VBOOT
Supply
voltage
Bootstrap voltage needed for driving the upper
power MOSFETs of both bridge A and bridge B.
16
32
OUT2B
Power output
Bridge B output 2.
17
33
VSB
Bridge B power supply voltage. It must be
Power supply connected to the supply voltage together with pin
VSA.
20
4
VSA
Bridge A power supply voltage. It must be
Power supply connected to the supply voltage together with pin
VSB.
21
5
OUT2A
Power output
Bridge A output 2.
22
7
VCP
Output
Charge pump oscillator output.
23
8
ENA
Logic input
Bridge A enable. LOW logic level switches OFF
all power MOSFETs of bridge A.
If not used, it has to be connected to +5 V.
R pin
Bridge A overcurrent level programming. A
resistor connected between this pin and ground
sets the programmable current limiting value for
the bridge A. By connecting this pin to ground
the maximum current is set. This pin cannot be
left non-connected.
24
9
PROGCLA
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Electrical characteristics
4
L6206
Electrical characteristics
Table 5. Electrical characteristics (Tamb = 25 °C, Vs = 48 V, unless otherwise specified)
Symbol
Test conditions
Min.
Typ.
Max.
Unit
Turn-on threshold
-
6.6
7
7.4
V
VSth(OFF) Turn-off threshold
-
5.6
6
6.4
V
All bridges OFF;
Tj = -25 °C to 125 °C(1)
-
5
10
mA
-
-
165
-
C
-
0.34
0.4
-
0.53
0.59
Tj = 25 °C
-
0.28
0.34
Tj = 125 °C(1)
-
0.47
0.53
EN = low; OUT = VS
-
-
2
mA
EN = low; OUT = GND
-0.15
-
-
mA
ISD = 2.8 A, EN = low
-
1.15
1.3
V
VSth(ON)
IS
Tj(OFF)
Parameter
Quiescent supply current
Thermal shutdown temperature
Output DMOS transistors
High-side switch ON resistance
RDS(ON)
Low-side switch ON resistance
IDSS
Leakage current
Tj = 25 °C
Tj = 125
°C(1)
Source drain diodes
VSD
Forward ON voltage
trr
Reverse recovery time
If = 2.8 A
-
300
-
ns
tfr
Forward recovery time
-
-
200
-
ns
Logic input
VIL
Low level logic input voltage
-
-0.3
-
0.8
V
VIH
High level logic input voltage
-
2
-
7
V
IIL
Low level logic input current
GND logic input voltage
-10
-
-
µA
IIH
High level logic input current
7 V logic input voltage
-
-
10
µA
Vth(ON)
Turn-on input threshold
-
-
1.8
2.0
V
Vth(OFF)
Turn-off input threshold
-
0.8
1.3
-
V
Vth(HYS)
Input threshold hysteresis
-
0.25
0.5
-
V
Switching characteristics
tD(on)EN
Enable to out turn ON delay time(2)
ILOAD = 2.8 A, resistive load
100
250
400
ns
tD(on)IN
Input to out turn ON delay time
ILOAD = 2.8 A, resistive load
(deadtime included)
-
1.6
-
µs
Output rise time(2)
ILOAD = 2.8 A, resistive load
40
-
250
ns
tD(off)EN
Enable to out turn OFF delay time(2)
ILOAD = 2.8 A, resistive load
300
550
800
ns
tD(off)IN
Input to out turn OFF delay time
ILOAD = 2.8 A, resistive load
-
600
-
ns
tFALL
(2)
ILOAD = 2.8 A, resistive load
40
-
250
ns
tRISE
8/29
Output fall time
DocID07617 Rev 4
L6206
Electrical characteristics
Table 5. Electrical characteristics (Tamb = 25 °C, Vs = 48 V, unless otherwise specified) (continued)
Symbol
Parameter
tdt
Deadtime protection
fCP
Charge pump frequency
Test conditions
Min.
Typ.
Max.
Unit
-
0.5
1
-
µs
-25 °C < Tj < 125 °C
-
0.6
1
MHz
0.57
4.42
5.6
+10%
+10%
+30%
A
A
A
Overcurrent detection
Is over
Input supply overcurrent detection
threshold
ROPDR
Open drain ON resistance
tOCD(ON)
I = 4 mA
-
40
60
(3)
I = 4 mA; CEN < 100 pF
-
200
-
ns
time(3)
I = 4 mA; CEN < 100 pF
-
100
-
ns
OCD turn-on delay time
tOCD(OFF) OCD turn-off delay
-25 °C < Tj < 125 °C; RCL = 39 k -10%
-25 °C < Tj < 125 °C; RCL = 5 k -10%
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DocID07617 Rev 4
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Circuit description
L6206
Figure 12. tDISABLE versus CEN and REN (VDD = 5 V)
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Figure 13. tDELAY versus CEN (VDD = 5 V)
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5.4
Thermal protection
In addition to the overcurrent detection, the L6206 device integrates a thermal protection for
preventing the device destruction in case of junction overtemperature. It works sensing the
die temperature by means of a sensible element integrated in the die. The device switchesoff when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ.
value).
16/29
DocID07617 Rev 4
L6206
6
Application information
Application information
A typical application using the L6206 device is shown in Figure 14. Typical component
values for the application are shown in Table 8. A high quality ceramic capacitor in the range
of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near
the L6206 device to improve the high frequency filtering on the power supply and reduce
high frequency transients generated by the switching. The capacitors connected from the
ENA/OCDA and ENB/OCDB nodes to ground set the shutdown time for the bridge A and
bridge B respectively when an overcurrent is detected (see Section 5.3: Non-dissipative
overcurrent detection and protection on page 13). The two current sources (SENSEA and
SENSEB) should be connected to power ground with a trace length as short as possible in
the layout. To increase noise immunity, unused logic pins are best connected to 5 V (high
logic level) or GND (low logic level) (see Table 4: Pin description on page 6). It is
recommended to keep power ground and signal ground separated on the PCB.
Table 8. Component values for typical application
Component
Value
Component
Value
C1
100 F
D1
1N4148
C2
100 nF
D2
1N4148
CBOOT
220 nF
RCLA
5 K
CP
10 nF
RCLB
5 K
CENA
5.6 nF
RENA
100 k
CENB
5.6 nF
RENB
100 k
Figure 14. Typical application (with reference to 24-pin packages)
*/7
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Application information
6.1
L6206
Paralleled operation
The outputs of the L6206 device can be paralleled to increase the output current capability
or reduce the power dissipation in the device at a given current level. It must be noted,
however, that the internal wire bond connections from the die to the power or sense pins of
the package must carry current in both of the associated half-bridges. When the two halves
of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak
current rating is not increased since the total current must still flow through one bond wire on
the power supply or sense pin. In addition the overcurrent detection senses the sum of the
current in the upper devices of each bridge (A or B) so connecting the two halves of one
bridge in parallel does not increase the overcurrent detection threshold.
For most applications the recommended configuration is half-bridge 1 of bridge A paralleled
with the half-bridge 1 of the bridge B, and the same for the half-bridges 2 as shown in
Figure 15. The current in the two devices connected in parallel will share very well since the
RDS(ON) of the devices on the same die is well matched.
When connected in this configuration the overcurrent detection circuit, which senses the
current in each bridge (A and B), will sense the current in upper devices connected in
parallel independently and the sense circuit with the lowest threshold will trip first. With the
enables connected in parallel, the first detection of an overcurrent in either upper DMOS
device will turn of both bridges. Assuming that the two DMOS devices share the current
equally, the resulting overcurrent detection threshold will be twice the minimum threshold
set by the resistors RCLA or RCLB in Figure 15. It is recommended to use RCLA = RCLB.
In this configuration the resulting bridge has the following characteristics:
Equivalent device: full bridge
RDS(ON) 0.15 typ. value at TJ = 25 °C
5.6 A max. RMS load current
11.2 A max. OCD threshold
Figure 15. Parallel connection for higher current (with reference to 24-pin packages)
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L6206
Application information
To operate the device in parallel and maintain a lower overcurrent threshold, half-bridge 1
and the half-bridge 2 of the bridge A can be connected in parallel and the same done for the
bridge B as shown in Figure 16. In this configuration, the peak current for each half-bridge is
still limited by the bond wires for the supply and sense pins so the dissipation in the device
will be reduced, but the peak current rating is not increased.
When connected in this configuration the overcurrent detection circuit, senses the sum of
the current in upper devices connected in parallel. With the enables connected in parallel,
an overcurrent will turn of both bridges. Since the circuit senses the total current in the upper
devices, the overcurrent threshold is equal to the threshold set the resistor RCLA or RCLB in
Figure 16. RCLA sets the threshold when outputs OUT1A and OUT2A are high and resistor
RCLB sets the threshold when outputs OUT1B and OUT2B are high.
It is recommended to use RCLA = RCLB.
In this configuration, the resulting bridge has the following characteristics:
Equivalent device: full bridge
RDS(ON) 0.15 typ. value at TJ = 25 °C
2.8 A max. RMS load current
5.6 A max. OCD threshold
Figure 16. Parallel connection with lower overcurrent threshold
(with reference to 24-pin packages)
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Application information
L6206
It is also possible to parallel the four half-bridges to obtain a simple half-bridge as shown in
Figure 17. In this configuration the overcurrent threshold is equal to twice the minimum
threshold set by the resistors RCLA or RCLB in Figure 17. It is recommended to use
RCLA = RCLB.
The resulting half-bridge has the following characteristics:
Equivalent device: half-bridge
RDS(ON) 0.075. typ. value at TJ = 25 °C
5.6 A max. RMS load current
11.2 A max. OCD threshold
Figure 17. Paralleling the four half-bridges (with reference to 24-pin packages)
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6.2
Application information
Output current capability and IC power dissipation
In Figure 18 and Figure 19 are shown the approximate relation between the output current
and the IC power dissipation using PWM current control driving two loads, for two different
driving types:
One full bridge ON at a time (Figure 18) in which only one load at a time is energized.
Two full bridges ON at the same time (Figure 19) in which two loads at the same time
are energized.
For a given output current and driving type the power dissipated by the IC can be easily
evaluated, in order to establish which package should be used and how large must be the
on-board copper dissipating area to guarantee a safe operating junction temperature
(125 °C maximum).
Figure 18. IC power dissipation versus output current with one full bridge ON
at a time
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Figure 19. IC power dissipation versus output current with two full bridges ON
at the same time
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Application information
6.3
L6206
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heatsinking can be achieved
using copper on the PCB with proper area and thickness. Figure 21 and 22 show the
junction to ambient thermal resistance values for the PowerSO36 and SO24 packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper
thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 µm), the
Rth j-amb is about 35 °C/W. Figure 20 shows mounting methods for this package. Using
a multilayer board with vias to a ground plane, thermal impedance can be reduced down
to 15 °C/W.
Figure 20. Mounting the PowerSO package
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
Figure 21. PowerSO36 junction ambient thermal resistance versus on-board copper
area
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Application information
Figure 22. SO24 junction ambient thermal resistance versus on-board copper area
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Application information
L6206
Figure 23. Typical quiescent current vs. supply Figure 24. Typical high-side RDS(ON) vs. supply
voltage
voltage
Iq [m A]
RDS(ON) []
5.6
fsw = 1 kHz
0.380
Tj = 25 °C
0.376
Tj = 85 °C
5.4
0.372
Tj = 25 °C
0.368
0.364
5.2
0.360
Tj = 125 °C
0.356
5.0
0.352
0.348
4.8
0.344
0.340
0.336
4.6
0
10
20
30
V S [V]
40
50
0
60
5
10
15
20
25
30
VS [V]
Figure 25. Normalized typical quiescent current
vs. switching frequency
Figure 26. Normalized RDS(ON) vs.junction
temperature (typical value)
R DS(ON) / (RDS(ON) @ 25 °C)
Iq / (Iq @ 1 kHz)
1.8
1.7
1.6
1.6
1.5
1.4
1.4
1.3
1.2
1.2
1.0
1.1
1.0
0.8
0
0.9
0
20
40
60
80
20
40
60
80
100
120
140
Tj [°C]
100
fSW [kHz]
Figure 27. Typical low-side RDS(ON) vs. supply
voltage
R DS(ON) []
ISD [A]
0.300
3.0
Tj = 25 °C
0.296
2.5
Tj = 25 °C
0.292
2.0
0.288
1.5
0.284
1.0
0.280
0.5
0.276
0
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Figure 28. Typical drain-source diode forward
ON characteristic
5
10
15
V S [V]
20
25
30
0.0
700
800
900
1000
VSD [mV]
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1300
L6206
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1
PowerSO36 package information
Figure 29. PowerSO36 package outline
1
1
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L6206
Table 9. PowerSO36 package mechanical data
Dimensions (mm)
Dimensions (inch)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
-
-
3.60
-
-
0.141
a1
0.10
-
0.30
0.004
-
0.012
a2
-
-
3.30
-
-
0.130
a3
0
-
0.10
0
-
0.004
b
0.22
-
0.38
0.008
-
0.015
c
0.23
-
0.32
0.009
-
0.012
D(1)
15.80
-
16.00
0.622
-
0.630
D1
9.40
-
9.80
0.370
-
0.385
E
13.90
-
14.50
0.547
-
0.570
e
-
0.65
-
-
0.0256
-
e3
-
11.05
-
-
0.435
-
10.90
-
11.10
0.429
-
0.437
E2
-
-
2.90
-
-
0.114
E3
5.80
-
6.20
0.228
-
0.244
E4
2.90
-
3.20
0.114
-
0.126
G
0
-
0.10
0
-
0.004
H
15.50
-
15.90
0.610
-
0.626
h
-
-
1.10
-
-
0.043
L
0.80
-
1.10
0.031
-
0.043
(1)
E1
N
10° (max.)
S
8° (max.)
1. “D” and “E1” do not include mold flash or protrusions.
- Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch).
- Critical dimensions are “a3”, “E” and “G”.
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7.2
Package information
SO24 package information
Figure 30. SO24 package outline
&
Table 10. SO24 package mechanical data
Dimensions (mm)
Dimensions (inch)
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
A
2.35
-
2.65
0.093
-
0.104
A1
0.10
-
0.30
0.004
-
0.012
B
0.33
-
0.51
0.013
-
0.020
C
0.23
-
0.32
0.009
-
0.013
D(1)
15.20
-
15.60
0.598
-
0.614
E
7.40
-
7.60
0.291
-
0.299
e
-
1.27
-
-
0.050
-
H
10.0
-
10.65
0.394
-
0.419
h
0.25
-
0.75
0.010
-
0.030
L
0.40
-
1.27
0.016
-
0.050
-
0.004
k
ddd
0° (min.), 8° (max.)
-
-
0.10
-
1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
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Revision history
8
L6206
Revision history
Table 11. Document revision history
Date
Revision
03-Sep-2003
1
Initial release.
2
Updated Section : Description on page 1 (removed “MultiPower-”
from “MultiPower-BCD technology”).
Added Contents on page 2.
Updated Section 1: Block diagram (added section title, numbered
and moved Figure 1: Block diagram from page 1 to page 3).
Added title to Section 2: Maximum ratings on page 4, added
numbers and titles from Table 1: Absolute maximum ratings to
Table 3: Thermal data.
Added title to Section 3: Pin connections on page 6, added number
and title to Figure 2: Pin connections (top view), renumbered note 1
below Figure 2, added title to Table 4: Pin description.
Added title to Section 4: Electrical characteristics on page 8, added
title and number to Table 5, renumbered notes 1 to 3 below Table 5.
Renumbered Figure 3 and Figure 4.
Added section numbers to Section 5: Circuit description on page 11,
Section 5.1 to Section 5.4. Removed “and uC” from first sentence in
Section 5.2. Renumbered Table 6 and Table 7, added header to
Table 6. Renumbered Figure 5 to Figure 13. .
Added section numbers to Section 6: Application information on
page 17, Section 6.1 to Section 6.3. Renumbered Table 8, added
header to Table 8. Renumbered Figure 14 to Figure 29.
Updated Section 7: Package information on page 26 (added main
title and ECOPACK text. Added titles from Table 9: PowerSO36
package mechanical data to Table 11: SO24 package mechanical
data and from Figure 30: PowerSO36 package outline to Figure 32:
SO24 package outline, reversed order of named tables and figures.
Removed 3D figures of packages, replaced 0.200 by 0.020 inch of
max. B value in Table 11).
Added cross-references throughout document.
Added Section 8: Revision history and Table 12.
Minor modifications throughout document.
13-Mar-2017
3
Updated Table 8 on page 17 (removed CREF row).
Updated Figure 14 on page 17 (replaced by new figure and title).
Updated Figure 15 on page 18, Figure 16 on page 19, and Figure 17
on page 20 [added “(with reference to 24-pin packages)” to titles].
Minor modifications throughout document.
03-Oct-2018
4
Removed PowerDIP24 package from the whole document.
Removed “Tj“ from Table 2 on page 4.
Minor modifications throughout document.
24-Feb-2014
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Changes
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