L6382DTR

L6382D POWER MANAGEMENT UNIT FOR MICROCONTROLLED BALLAST 1 ■ ■ FEATURES INTEGRATED HIGH-VOLTAGE START-UP 4 DRIVERS FOR PFC, HALF-BRIDGE & PREHEATING MOSFETS 3.3V MICROCONTROLLER COMPATIBLE FULLY INTEGRATE POWER MANAGEMENT FOR ALL OPERATING MODES INTERNAL TWO POINT Vcc REGULATOR OVER-CURRENT PROTECTION WITH DIGITAL OUTPUT SIGNAL CROSS-CONDUCTION PROTECTION (INTERLOCKING) UNDER VOLTAGE LOCK OUT INTEGRATED BOOTSTRAP DIODE Figure 1. Package ■ ■ SO20 Table 1. Order Codes Part Number L6382D L6382DTR Package SO20 tube SO20 in Tape & Reel ■ ■ ■ ■ ■ high voltage start-up generator conceived for applications managed by a microcontroller. It allows the designer to use the same ballast circuit for different lamp wattage/type by simply changing the µC software. The digital input pins - able to receive signals up to 400KHz - are connected to level shifters that provide the control signals to their relevant drivers; 2 ■ APPLICATIONS DIMMABLE/NON-DIMMABLE BALLST 3 DESCRIPTION Designed in High-voltage BCD Off-line technology, the L6382D is provided with 4 input pins and a Figure 2. Block Diagram HVSU TPR BOOTSTRAP >600V HIGH “ON” BOOT IC BIAS mP UVLO VOLTAGE START-UP “OFF” GENERATOR R Q LEVEL SHIFT 3.3V 600V HSD HSG OUT LSD S Q RQ LSG ON PSW 3.3V SUPPLY L O G I C TPR S Q CSO OCP CSI HED HEG PFD DIM PFG Vcc HSI LSI HEI PFI REF GND January 2005 Rev. 2 1/14 L6382D in particular the L6382D embeds one driver for the PFC pre-regulator stage, two drivers for the ballast halfbridge stage (High Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated filaments in dimmable applications. A precise reference voltage (+3.3V ±1%) able to provide up to 30mA is available to supply the µC in operating mode. Instead, during start-up and save mode the current available at VREF is up to 10mA and it is provided by the internal high voltage start-up generator. The chip has been conceived with advanced power management logic to minimize power losses and increase the application reliability. In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode. The L6382D integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption. Figure 3. Pin Connection (Top View) PFI LSI HSI HEI PFG N.C. TPR GND LSG VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VREF CSI CSO HEG N.C. HVSU N.C. OUT HSG BOOT Figure 4. Typical System Block Diagram PFC CIRCUIT AC MAINS HV START-UP CHARGE PUMP REGULATOR BOOTSTRAP HB DRIVER TL PFC DRIVER 3.3V SUPPLY PROTECTION µC 2/14 L6382D Table 2. Pin Functions N. 1 2 3 4 5 Pin PFI LSI HSI HEI PFG Function Digital input signal to control the PFC gate driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the half-bridge low side driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the half-bridge high side driver. This pin has to be connected to a TTL compatible signal. Digital input signal to control the HEG output. This pin has to be connected to a TTL compatible signal. PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink. Not connected Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the Vcc. Chip ground. Current return for both the low-side gate-drive currents and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. Low Side Driver Output. This pin must be connected to the gate of the half-bridge low side power MOSFET. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. The totem pole output stage is able to drive power with a peak current of 120mA source and 120mA sink. Supply Voltage for the signal part of the IC and for the drivers. High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. This patented structure normally replaces the external diode. High Side Driver Output. This pin must be connected to the gate of the half bridge high side power MOSFET . A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 20KΩ resistor toward OUT pin avoids spurious and undesired MOSFET turn-on The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 120mA sink. High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground. Not connected High-voltage start-up. The current flowing into this pin charges the capacitor connected between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. When the chip works in operating mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the UVLO threshold. According to the required VREF pin current, this pin can be connected to the rectified mains voltage either directly or through a resistor. High-voltage spacer. The pin is not connected internally to isolate the high-voltage pin and comply with safety regulations (creepage distance) on the PCB. Output for the HEI block; this driver can be used to drive the MOS employed in isolated filaments preheating. An internal 20KΩ resistor toward ground avoids spurious and undesired MOSFET turn-on. 6 7 8 N.C. TPR GND 9 LSG 10 11 Vcc BOOT 12 HSG 13 14 15 OUT N.C. HVSU 16 17 N.C. HEG 3/14 L6382D Table 2. Pin Functions (continued) N. 18 Pin CSO Function Output of current sense comparator, compatible with TTL logic signal; during operating mode, the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.55 typ.) the pin latches high. Input of current sense comparator, it is enabled only during operating mode; when the pin voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously. Voltage reference. During operating mode an internal generator provides an accurate voltage reference that can be used to supply up to 30mA (during operating mode) to an external circuit. A small film capacitor (0.22µF min.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. 19 CSI 20 VREF Table 3. Absolute Maximum Ratings Symbol VCC VHVSU VBOOT VOUT ITPR(RMS) ITPR(PK) VTPR Pin 10 15 11 13 6 6 6 19 1, 2, 3, 4 9, 12, 17 5 Tstg Tj (*) excluding operating mode Parameter IC supply voltage (ICC = 20mA) High voltage start-up generator voltage range Floating supply voltage Floating ground voltage Maximum TPR RMS current Maximum TPR peak current Maximum TPR voltage (*) CSI input voltage Logic input voltage Operating frequency Operating frequency Storage Temperature Ambient Temperature operating range Value Self-limited -0.3 to 600 -1 to VHVSU+VCC -1 to 600 ±200 ±600 14 -0.3 to 7 -0.3 to 7 15 to 400 15 to 600 -40 to +150 -40 to +125 Unit V V V mA mA V V V KHz KHz °C °C Table 4. Thermal Data Symbol Rth j-amb Parameter Max. Thermal Resistance, Junction-to-ambient Value 120 Unit °C/W 4/14 L6382D Table 5. Electrical Characteristcs (Tj = 25°C, VCC=12V unless otherwise specified) Symbol Pin Parameter Test condition min. typ max UNIT SUPPLY VOLTAGE VccON VccOFF VccSM VSMhys VREF(OFF) IvccON IvccSM 10 10 10 10 10 10 10 Turn-on voltage Turn-off voltage Save mode voltage Save mode hysteresys Reference turn-off Start-up current Save Mode consumption current (1) Ivcc Vz 10 10 Quiescent current operating mode Internal Zener in Vcc=13V; LGI=HGI=high; no load on VREF. TBD 150 13 7.5 12.75 0.15 5.7 14 8.25 13.8 0.2 6 15 9.2 14.85 0.25 6.33 150 190 230 2 V V V V V µA µA µA mA V HIGH VOLTAGE START-UP IMSS 15 15 ILSS 15 Maximum current Turn-on Voltage Leakage current off state VHVSU > 50V IHVSU=5mA VHVSU = 600V 20 TBD 40 mA V µA TWO POINT REGULATOR (TPR) PROTECTION TPRst TPR(ON) TPR(OFF) 10 10 10 7 7 7 Vcc Protection level Vcc Turn-on level Vcc Turn-off level Output voltage on state Forward Diode voltage Operating mode Operating mode; after the first falling edge on LSG Operating mode; after the first falling edge on LSG ITPR = 200mA 14.0 12.5 12.45 15.0 13.5 13.48 2 2 5 V V V V V µA drop @ 600mA forward current. VTPR = 13V Leakage current off state LSG, HEG & PFG DRIVERS VOH(LS) VOL(LS) 5, 9, 17 5, 9, 17 HIGH Output Voltage LOW Output Voltage Sink Current Capability ILSG = 10mA ILSG = 10mA LSG and PFG HEG 120 50 VCC 0.5 0.5 V V mA mA 5/14 L6382D Table 5. Electrical Characteristcs (continued) Symbol Pin Parameter Source Current Capability LSG HEG PFG TRISE TFALL TDELAY 5, 9, 17 5, 9, 17 Rise time Fall time Cload = 1nF Cload = 1nF Test condition min. 120 70 250 TBD TBD 300 200 250 200 20 50 10 ns ns ns ns ns ns KΩ KΩ KΩ typ max UNIT mA Propagation delay (input LSG; high to low and low to to output) high HEG; high to low and low to high PFG; high to low PFG; low to high RB Pull down Resistor LSG HEG PFG HSG DRIVER (VOLTAGES REFERRED TO OUT) VOH(HS) VOL(HS) 12 12 12 12 TRISE TFALL TDELAY RB 12 12 12 12 HIGH Output Voltage LOW Output Voltage Sink Current Capability Source Current Capability Rise time Fall time Cload = 1nF Cload = 1nF IHSG = 10 mA IHSG = 10 mA 120 120 TBD TBD 300 20 VOUT 0.5 0.5 V V mA mA ns ns ns KΩ Propagation delay (LGI to high to low and low to high LSG) Pull down Resistor to OUT HIGH-SIDE FLOATING GATE-DRIVER SUPPLY ILKBOOT ILKOUT RDS(on) 11 13 VBOOT current pin leakage VBOOT = 580V VOUT = 562V VLVG = HIGH at 10 mA forward current at 5V forward voltage drop 25 100 1.9 2.4 5 5 µA µA Ω V mA OUT pin leakage current Synchronous bootstrap diode on-resistance Forward Voltage Drop Forward Current 6/14 L6382D Table 5. Electrical Characteristcs (continued) Symbol VREF VREF 20 Reference voltage 15mA load. 15mA load, (1) 20 20 20 20 Load regulation Voltage change VREF latched protection VREF Clamp @3mA VCC from 0 to VCCON during start-up; Vcc from VREF(OFF) to 0 during shut-down. -3 Save mode OVERCURRENT BUFFER STAGE VCSI ICSI 19 19 Comparator Level Input Bias Current Propagation delay 18 18 DIM Normal Mode Time Out Vref enabling drivers TED LOGIC INPUT 1 to 4 1 to 4 LGI Low Level Logic Input Voltage High Level Logic Input Voltage Pull down resistor 2.2 100 0.8 V V KΩ Time enabling drivers 65 100 3.0 10 135 µs V µs High output voltage Low output voltage CSO turn off to LSG low I CSO= 200µA I CSO = -150µA VREF0.5V 0.5 V Bandgap 0.49 0.5 5.01 500 200 V nA ns -3 IRef = -3 to +30 mA 15mA load; Vcc = 9V to 15V 2 1.2 3.267 3.234 -20 3.3 3.3 3.333 3.366 2 15 V V mV mV V V Pin Parameter Test condition min. typ max UNIT IREF 20 Current Drive Capability +30 +10 mA mA Notes: 1. Specification over the -40°C to +125°C junction temperature range are ensured by design, characterization and statistical correlation. 7/14 L6382D 4 APPLICATION INFORMATION 4.1 POWER MANAGEMENT The L6382D has two stable states (save mode and operating mode) and two additional states that manage the Start-up and fault conditions (fig. 5): the Over Current Protection is a parallel asynchronous process enabled when in operating mode. Following paragraphs will describe each mode and the condition necessary to shift between them. Figure 5. START-UP VCCVCC(ON) VCC10ms LGI low for more than 100ms VCC < VCC(OFF) or VREF