L6710

L6710 6 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT 6 BIT PROGRAMMABLE OUTPUT COMPLIANT WITH VRD 10 DYNAMIC VID MANAGEMENT 0.5% OUTPUT VOLTAGE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S RdsON OR A SENSE RESISTOR OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 150kHz POWER GOOD OUTPUT AND ENABLE FUNCTION INTEGRATED REMOTE SENSE BUFFER TQFP44 (10 x 10 x 1mm) Exposed Pad ORDERING NUMBERS:L6710 L6710TR (Tape & Reel) c u d e t le o r P o s b O - ) s ( ct APPLICATIONS ■ POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS ■ POWER SUPPLY FOR SERVER AND WORKSTATION ■ DISTRIBUTED POWER SUPPLY u d o r P e ) s t( DESCRIPTION The device implements a two phase step-down controller with a 180 phase-shift between each phase with integrated high current drivers in a compact 10x10mm body package with exposed pad. A precise 6-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.8375V to 1.6000V with 12.5mV binary steps managing Dynamic VID code changes. The high precision internal reference assures the selected output voltage to be within 0.5% over line and temperature variations. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode until UVP PIN CONNECTION (top view) N.C. HGATE2 PHASE2 N.C. LGATE2 PGND LGATE1 VCCDR PHASE1 HGATE1 N.C. 33 32 31 30 29 28 27 26 25 24 23 22 34 35 21 36 20 37 19 38 18 39 17 40 16 41 15 42 14 13 43 44 1 2 3 4 5 6 7 8 9 12 10 11 OSC / FAULT ISEN2 PGNDS ISEN1 FBG FBR N.C. N.C. OUTEN VSEN REF_OUT N.C. N.C. BOOT1 N.C. VCC SGND SGND COMP FB N.C. N.C. s b O N.C. N.C. BOOT2 PGOOD VID5 VID4 VID3 VID2 VID1 VID0 N.C. t e l o March 2004 1/34 L6710 BLOCK DIAGRAM OSC / FAULT SGND VCCDR 2 PHASE OSCILLATOR PWM1 CURRENT CORRECTION DAC VCC 32k PGND CH2 OCP REMOTE BUFFER Vcc ERROR AMPL IFIER FB COMP ABSOLUTE MAXIMUM RATINGS Symbol Vcc VBOOT-VPHASE Boot Voltage VUGATE1-VPHASE1 VUGATE2-VPHASE2 o r P e c u d (t s) LGATE1, PHASE1, LGATE2, PHASE2 to PGND t e l o VPHASEx s b O e t le o s b O - Parameter To PGND Vcc, VCCDR LGATE1 PGNDS CURRENT READING PWM2 REF_OUT LS CURRENT READING CURRENT CORRECTION I FB 32k PHASE1 ISEN2 32k FBR U GATE1 ISEN1 TO TAL CURRENT VSEN 32k HS VCCDR CH2 OCP CH1 OCP FBG CH1 OCP CURRENT AVG VID5 VID4 VID3 VID2 VID1 VID0 LOGIC AND PROTECTIONS DIGITAL SOFT-START LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION PGOOD LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION BOOT1 OUTEN LS ) s t( LGATE2 c u d PHASE2 o r P HS UGATE2 BOOT2 Value Unit 15 V 15 V 15 V -0.3 to Vcc+0.3 V VID0 to VID5 -0.3 to 5 V All other pins to PGND -0.3 to 7 V 26 V Value Unit Sustainable Peak Voltage. T35µA). ) s ( ct u d o The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON until the current read becomes lower than IOCPx (IINFOx < 35µA) skipping clock cycles. The high side mosfets can be turned ON with a TON imposed by the control loop at the next available clock cycle and the device works in the usual way until another OCP event is detected. r P e This means that the average current delivered can slightly increase also in Over Current condition since the current ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach the IOCPx bottom. The worst-case condition is when the ON time reaches its maximum value. t e l o s b O When this happens, the device works in Constant Current and the output voltage decrease as the load increase. Crossing the UVP threshold causes the device to latch (FAULT pin is driven high). Figure 5 shows this working condition. It can be observed that the peak current (Ipeak) is greater than the IOCPx but it can be determined as follow: V IN – Vout mi n V I N – VoutM IN Ipea k = I OCPx + ------------------------------------- ⋅ TonM AX = IOCPx + -------------------------------------- ⋅ 0.40 ⋅ T L L Where VoutMIN is the minimum output voltage (VID-40% as follow). The device works in Constant-Current, and the output voltage decreases as the load increase, until the 13/34 L6710 output voltage reaches the under-voltage threshold (VoutMIN). When this threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The maximum average current during the Constant-Current behavior results: Ipeak – IOCPx IMA X,TOT = 2 ⋅ I MA X = 2 ⋅  IOCPx + ------------------------------------- 2 In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed (TonMAX) while the OFF time depends on the application: Ipeak – I OCPx T O FF = L ⋅ -------------------------------------V OU t 1 f = ----------------------------------------T ONm ax + T O FF Over current is set anyway when IINFOx reaches 35µA (IFB=70µA). ) s t( The full load value is only a convention to work with convenient values for IFB. Since the OCP intervention threshold is fixed, to modify the percentage with respect to the load value, it can be simply considered that, for example, to have on OCP threshold of 200%, this will correspond to IINFOx = 35µA (IFB = 70µA). The full load current will then correspond to IINFOx = 17.5µA (IFB = 35µA). c u d Figure 5. Constant Current operation Ipeak IMAX ) s ( ct TonMAX e t le o s b O IOCPx Vout o r P UVP TonMAX u d o a) Maximum current for each phase r P e Droop effect Iout IMAX,TOT (IFB=50µA) 2·IOCPx (IFB=70µA) b) Output Characteristic t e l o INTEGRATED DROOP FUNCTION s b O The device uses a droop function to satisfy the requirements of high performance microprocessors, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: the regulated voltage decrease as the load increase with a precise relationship. As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. A static error (VDROOP in figure 6) at zero load is simply introduced by a resistor between FB and GND allowing to exploit the all tolerance interval available. This additional resistor is not required in application such as VRD10 since the nominal value is already set by the VID* and the load regulation fixed by the specs. Since the device has an average current mode regulation, the information about the total current delivered 14/34 L6710 is used to implement the Droop Function. This current IFB (equal to the sum of both IINFOx) is sourced from the FB pin. Connecting a resistor between this pin and Vout, the total current information flows only in this resistor because the compensation network between FB and COMP has always a capacitor in series (See fig. 7). The voltage regulated is then equal to: V OUT = VID* – R FB ⋅ IFB Since IFB depends on the current information about the two phases, the output characteristic vs. load current is given by: R SE NSE V OUT = VID* – R DROOP ⋅ ILOAD = VID* – R F B ⋅ ---------------------- ⋅ I L OAD Rg Where ILOAD is the output current of the system and RDROOP is its equivalent output resistance. The feedback current is equal to 50µA at nominal full load (IFB = IINFO1 + IINFO2) and 70µA at the OC intervention threshold, so the maximum output voltage deviation is equal to: ∆ V FUL L – P OSITIVE – LOAD = – R FB ⋅ 50 µ A ∆ V OC – INTERV ENTION = – R FB ⋅ 70 µ A c u d Figure 6. Output transient response without (a) and with (b) the droop function ESR DROP ESR DROP e t le VMAX VNOM o s b O - ) s t( o r P VDROOP VMIN (s) (a) (b) t c u Figure 7. Active Droop Function Circuit d o r P e t e l o s b O VDROOP To VOUT RFB COMP FB Total Current Info (IINFO1+IINFO2) Ref REMOTE VOLTAGE SENSE A remote sense buffer is integrated into the device to allow output voltage remote sense implementation without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating motherboard trace losses or connector losses if the device 15/34 L6710 is used for a VRM module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and guarded by a power plane results in common mode coupling for any picked-up noise. If remote sense is not required, it is enough connecting RFB directly to the regulated voltage: VSEN becomes not connected and still senses the output voltage through the remote buffer. In this case the FBG and FBR pins must be connected anyway to the regulated voltage (See figure 9). The remote buffer is included in the trimming chain in order to achieve ±0.5% accuracy on the output voltage when the RB Is used: eliminating it from the control loop causes the regulation error to be increased by the RB offset worsening the device performances. Figure 8. Remote Buffer Connections Reference REMOTE BUFFER 32k 32k FBR IFB 32k FB VSEN CF COMP 32k FBR 32k FBG FB VSEN c u d RFB RF Remote Ground e t le RB used (±0.5% Accuracy) CF ) s t( COMP RF o r P VOUT OUTPUT VOLTAGE MONITOR PROTECTION ERROR AMPLIFIER IFB 32k RFB Remote VOUT 32k 32k FBG Reference REMOTE BUFFER ERROR AMPLIFIER RB Not Used o s b O - The device monitors through pin VSEN the regulated voltage in order to build the PGOOD signal and manage the OVP / UVP conditions comparing this voltage level with the programmed reference VID*. ) s ( ct Power good output is forced low if the voltage sensed by VSEN is not within ±12% (Typ.) of the programmed value. It is an open drain output and it is enabled only after the soft start is finished (2048 clock cycles after start-up). During Soft-Start this pin is forced low. u d o Under voltage protection is provided. If the output voltage monitored by VSEN drops below the 60% of the reference voltage for more than one clock period, the device turns off all mosfets and the OSC/FAULT is driven high (5V). The condition is latched, to recover it is required to cycle the power supply. r P e Over Voltage protection is also provided: t e l o Once VCC crosses the turn-ON threshold, when the voltage monitored by VSEN reaches 125% (Typ.) of the programmed voltage the controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets in order to protect the CPU. The OSC/ FAULT pin is driven high (5V) and power supply (Vcc) turn off and on is required to restart operations. s b O Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than the output voltage reaches 0.6V). The reference used in this case to determine the UV thresholds is the increasing voltage driven by the 2048 soft start digital counter while the reference used for the OV threshold is the final reference programmed by the VID pins. 16/34 L6710 Figure 9. OVP (left) and UVP (right) latch. LGATEx LGATEx OSC/FAULT OSC/FAULT OUTEN OUTEN REF_OUT REF_OUT SOFT START, INHIBIT AND POWER DOWN ) s t( At start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in 2048 clock periods as shown in figure 10. c u d Once the soft start begins, the reference is increased: upper and lower MOS begin to switch and the output voltage starts to increase with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the PGOOD signal is then driven high (See fig. 10). The Under Voltage comparator is enabled when the reference voltage reaches 0.6V. The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-on thresholds. e t le o r P During normal operation, if any under-voltage is detected on one of the two supplies the device shuts down. Forcing the OUTEN pin to a voltage lower than 0.4V (Typ.) disables the device: all the power mosfets and protections are turned off until the condition is removed. Figure 10. Soft Start ) s ( ct VCC=VCCDR o s b O - Turn ON threshold u d o VLGATEx VOUT r P e t e l o PGOOD s b O t t t 2048 Clock Cycles Timing Diagram t Acquisition: CH1=PGOOD; CH2=REF_OUT; CH3=VOUT; CH4=LGATEx) 17/34 L6710 Figure 11. Power Down: 0A (left), resistive load (right); CH1= Vout; CH2,CH3 = LS; CH4 =V in ) s t( When shutting the system down, the device continues regulating until Vcc becomes lower than the turnoff threshold. After that point, the device will shut down all power mosfets. c u d INPUT CAPACITOR o r P The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as reported in figure 12. Considering the dual-phase topology, the input RMS current is highly reduced comparing with a single-phase operation. It can be observed that the input RMS value is one half of the single-phase equivalent input current in the worst case condition that happens for D=0.25 and D=0.75. o s b O - The power dissipated by the input capacitance is then equal to: P RMS = ESR ⋅ ( I RMS ) ) s ( ct e t le 2 Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the high RMS value needed by the CPU power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of the single capacitor's RMS current. u d o r P e Figure 12. Input RMS Current vs. Duty Cycle (D) and Driving Relationships. Rms Current Normalized (IRMS/IOUT) t e l o bs O 0.50 Single Phase Irms Dual Phase 0.25 0.25 0.50 0.75 Duty Cycle (VOUT/VIN) 18/34 I OUT ------------ ⋅ 2D ⋅ ( 1 – 2D ) 2 = I OUT ------------ ⋅ ( 2D – 1 ) ⋅ ( 2 – 2D ) 2 if D < 0.5 if D > 0.5 Where D = VOUT/VIN is the operative duty cycle for each phase L6710 Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high frequency noise decoupling, noise generated by parasitic components along power path. OUTPUT CAPACITOR Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the range of tenth A/µs, the output capacitor is a basic component for the fast response of the power supply. Dual phase topology reduces the amount of output capacitance needed because of faster load transient response (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple. When a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. The controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. ) s t( The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): c u d ∆ V OUT = ∆ I OUT ⋅ ESR o r P A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: e t le 2 ∆ I OUT ⋅ L ∆ V OUT = -----------------------------------------------------------------------------4 ⋅ C OUT ⋅ ( V In ⋅ dma x – V OUT ) o s b O - Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. ) s ( ct INDUCTOR DESIGN The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ∆IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: u d o r P e t e l o V IN – V OUT V OUT L = ------------------------------ ⋅ -------------fs ⋅ ∆ IL V IN s b O Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. The response time is the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response: 19/34 L6710 L ⋅ ∆I tapp lic atio n = -----------------------------V IN – V OUT L ⋅ ∆I tre mov al = -------------V OUT The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. MAIN CONTROL LOOP The control loop is composed by the Current Sharing control loop and the Average Current Mode control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Average Current Mode control loop fixes the output voltage equal to the reference programmed by VID. Figure 13 reports the block diagram of the main control loop. Figure 13. Main Control Loop Diagram L1 + c u d PWM1 CURRENT SHARING DUTY CYCLE CORRECTION 1/5 1/5 IINFO2 IINFO1 e t le L2 + PWM2 ERROR AMPLIFIER 4/5 + - COMP o r P RO FB (s) ZF(S) D02IN1392 o s b O REFERENCE PROGRAMMED BY VID CO ) s t( RFB t c u d o r P e Current Sharing (CS) Control Loop Active current sharing is implemented using the information from Tran conductance differential amplifier in an average current mode control scheme. t e l o A current reference equal to the average of the read current (IAVG) is internally built; the error between the read current and this reference is converted to a voltage with a proper gain and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 14). s b O The current sharing control is a high bandwidth control loop allowing current sharing even during load transients. The current sharing error is affected by the choice of external components; choose precise Rg resistor (±1% is necessary) to sense the current. The current sharing error is internally dominated by the voltage offset of Tran conductance differential amplifier; considering a voltage offset equal to 2mV across the sense resistor, the current reading error is given by the following equation ∆ I REA D 2mV -------------------- = -------------------------------------I MAX R SENSE ⋅ I MAX 20/34 L6710 Figure 14. Current Sharing Control Loop. L1 + PWM1 1/5 1/5 + CURRENT SHARING DUTY CYCLE CORRECTION PWM2 IINFO2 IINFO1 L2 COMP VOUT D02IN1393 Where ∆IREAD is the difference between one phase current and the ideal current (IMAX/2). For Rsense=4mΩ and Imax=40A the current sharing error is equal to 2.5%, neglecting errors due to Rg and Rsense mismatches. c u d Average Current Mode (ACM) Control Loop ) s t( o r P The average current mode control loop is reported in figure 15. The current information IFB sourced by the FB pin flows into RFB implementing the dependence of the output voltage from the read current. e t le The ACM control loop gain results (obtained opening the loop after the COMP pin) PWM ⋅ ZF ( s ) ⋅ ( RDROOP + Z P ( s ) ) G LOOP ( s ) ) = – ------------------------------------------------------------------------------------------------------------------ZF ( s )  1 - ⋅ R ( Z P ( s ) + Z L ( s ) ) ⋅ -------------- + 1 + ----------FB A ( s ) A(s )  Where: Rsense ■ R DROOP = ---------------------- ⋅ R FB Rg ■ ■ ■ ■ ) s ( ct o s b O - is the equivalent output resistance determined by the droop function; ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load Ro; ZF(s) is the compensation network impedance; ZL(s) is the parallel of the two inductor impedance; A(s) is the error amplifier gain; u d o r P e V IN 4 ■ PWM = --- ⋅ ------------------5 ∆ V OSC t e l o is the ACM PWM transfer function where Vosc is the oscillator ramp amplitude and has a typical value of 3V s b O Removing the dependence from the Error Amplifier gain, so assuming this gain high enough, the control loop gain results: V IN ZF ( s ) 4 Rs- + Z P ( s ) G LOOP ( s ) = – --- ⋅ ------------------- ⋅ ------------------------------------ ⋅  -------------------5 ∆ V OSC Z P ( s ) + Z L ( s )  Rg RF B  With further simplifications, it results: V IN Z F ( s ) Ro + R DROOP 4 G LOOP ( s ) = – --- ⋅ ------------------- ⋅ --------------- ⋅ ------------------------------------R 5 ∆ V OSC RFB Ro + ------L2 1 + s ⋅ Co ⋅ ( RDROOP //Ro + ESR ) --------------------------------------------------------------------------------------------------------------------------------RL 2 L L -----s ⋅ Co ⋅ --- + s ⋅ --------------- + Co ⋅ ESR + Co ⋅ +1 2 2 2 ⋅ Ro 21/34 L6710 Considering now that in the application of interest it can be assumed that Ro>>RL; ESR