L9374TRLF

L9374LF Four channel valve driver Datasheet - production data  16 bit serial peripheral interface, up to 5 MHz with diagnosis  Battery compatible supply voltage  Detailed load diagnosis – Over load protection – Open load (off-state) – Undercurrent – Undervoltage – Temperature warning and shutdown – Power or signal GND loss – Freewheeling diode loss – Silent valve driver test '!0'03 PowerSO-36 Features  Four protected low-side drivers with diagnostics – Two 140 mΩPWM controlled outputs (Q1 & Q2) – Two 250 mcurrent controlled outputs with 6 % accuracy (Q3 & Q4)  All outputs with 35 V Zener Clamp  Programmable output timer  Clock monitor Description The L9374LF is a SPI (serial peripheral interface) controlled four channel low side driver with integrated recirculation diodes. The output duty cycle (all channels) / current regulation level (Q3 & Q4 only) can be programmed individually. It is possible to program two consecutive output duty cycles or target currents per channel as well as an individual duration time for each channel actuation.  Integrated recirculation diodes . Table 1. Device summary Order code Package Packing L9374LF PowerSO-36 Tube L9374TRLF PowerSO-36 Tape and reel October 2013 This is information on a product in full production. DocID025414 Rev 1 1/80 www.st.com Contents L9374LF Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 ESD susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 4 HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.2 MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.1 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.2 Output power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.3 Freewheeling diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.4 Output timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.5 PWM output behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3.6 Q3 / Q4 (current controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.7 Logic inputs / outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.8 Logic outputs (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.9 Diagnostic functions at output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.10 General diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.11 Filtering times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.12 VD measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.13 Rs measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.14 V_FWD measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.15 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.16 SPI timing characteristics SPICLK, MISO, MOSI, SPICS . . . . . . . . . . . 20 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 2/80 3.2.1 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.1 General protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.2 SPI failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.3 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.4 Address decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.5 Parity generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID025414 Rev 1 L9374LF Contents 4.1.6 Initial MISO information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.7 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Command buffer (data in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Status buffer (data out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 4.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.1 Clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.2 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.3 CLKIN signal monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Synchronization controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.1 Output synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.2 Time shift between output actuation . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 Set-point controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5 Current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.6 4.5.1 Load resistance error integration phase . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5.2 Analog signal measure blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.3 Duty cycle calculation in the ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5.4 Current controller diagnostic performance . . . . . . . . . . . . . . . . . . . . . . . 38 PWM generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.6.1 4.7 4.8 Current not reachable detection(Q3 and Q4 only): . . . . . . . . . . . . . . . . 39 Output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.7.1 Input controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.7.2 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.8.1 Undercurrent / openload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.8.2 Openload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.8.3 Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.8.4 Thermal warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . 43 4.8.5 Power ground loss (PGND-loss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.8.6 Signal ground loss (SGND-loss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.8.7 Freewheeling diode loss detection (Dx-loss) . . . . . . . . . . . . . . . . . . . . . 44 4.8.8 SPI-failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.8.9 CLKIN-failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.8.10 Sync-failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.8.11 Current not reachable failure (Q3 & Q4) . . . . . . . . . . . . . . . . . . . . . . . . 46 4.8.12 ALU- BIST (Build in self test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.8.13 Silent valve driver test (SVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DocID025414 Rev 1 3/80 4 Contents 5 L9374LF Programmers guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1 5.2 6 Command registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1.1 Sync + Sync-trigger register (address 0) . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1.2 Sync tolerance window (STW) register (address 1) . . . . . . . . . . . . . . . 58 5.1.3 Configuration register 1 (address 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.4 Fast switch-on (FSON) register (address 3) . . . . . . . . . . . . . . . . . . . . . 60 5.1.5 Duration registers (address 4 and 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1.6 Duty cycle register (address 6 to 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1.7 Current / duty cycle registers (address 10 to 13) . . . . . . . . . . . . . . . . . . 62 5.1.8 Configuration register 2 - current control / over-voltage threshold (address 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.9 Configuration register 3 (CCV reset and load resistance values) (address 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.1 General status (address 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.2.2 Output status Q1... Q4 (address 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.2.3 VD (address 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2.4 Output duty (address 6 and 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.2.5 ISAT-Qx (address 8 + 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.2.6 Reference diode voltage measurement (V_FWD) (address 10) . . . . . . 71 5.2.7 Sense resistor measurement (Rs) (address 11) . . . . . . . . . . . . . . . . . . 71 5.2.8 Current controller status register (CC-STATUS) (address 12) . . . . . . . . 72 5.2.9 Error average (address 13 + 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2.10 Reserved (address 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Register block functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1 Input command register block overview (MOSI data) . . . . . . . . . . . . . . . 74 6.2 Status register block overview (MISO data) . . . . . . . . . . . . . . . . . . . . . . . 76 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4/80 DocID025414 Rev 1 L9374LF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output power stages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Freewheeling diode electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output timing electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Symmetric switching of DMOS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PWM output behavior characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Q3 / Q4 (current controller) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Logic inputs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Logic outputs (MISO) electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Diagnostic functions at output stage electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 17 General diagnostic functions electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CLKIN-monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Failure filtering times characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SVDT test timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VD measurement electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VD measurement bit values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RS measurement electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Rs SPI bit values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V_FWD measurement electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V_FWD SPI bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Internal oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Command buffer (data_in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Status buffer (data_out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Clock validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Sync. tolerance window interval length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Example of PWM duration timing, t(n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timer t(n) resolution versus RESET_VALUE MSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Qx_ON and Qx_OFF provide gate voltage status history information . . . . . . . . . . . . . . . . 40 Output driver possible input configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Fault diagnostic summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Status monitored during SVDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SVDT command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SVDT status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Sync + Sync-trigger register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STW value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Configuration register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Silent valve driver test (SVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 CLKIN_S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Fast switch off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Edge shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Fast switch-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Register duration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DocID025414 Rev 1 5/80 6 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. 6/80 L9374LF Duration bit resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Duty cycle register (address 6 to 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Current / duty cycle registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Configuration register 2 - current control / over-voltage threshold . . . . . . . . . . . . . . . . . . . 63 Current controller off Q3 / Q4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Overload threshold Q1 / Q2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Configuration register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reset current controller values command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Load resistor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 CLKIN_S command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Output status Q1... Q4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Current / PWM controller select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Overload threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 VD / BIST BUSY general status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 VD value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 BIST BUSY status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ISAT_Qx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reference diode voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 V_FWD value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Sense resistor measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Rs value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Current controller status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Error average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Overview input register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Overview answer register block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DocID025414 Rev 1 L9374LF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PowerSO-36 pins connection (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output power stages Q1/Q2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output power stages Q3/Q4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output timing characteristics diagram with edge shaping. . . . . . . . . . . . . . . . . . . . . . . . . . 14 Symmetric switching of DMOS diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Logic outputs (MISO) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI timing characteristics SPICLK, MISO, MOSI, SPICS. . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General SPI protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Synchronization controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Sync-failure + re-synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Behavior of the output when the synchronization is done. . . . . . . . . . . . . . . . . . . . . . . . . . 31 Channels time shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Set-point controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Set-point control example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Load current response for different target currents diagram. . . . . . . . . . . . . . . . . . . . . . . . 35 Integration of the error average . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PWM control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Gate drive block diagram with power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Diagnosis block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Diagram under current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Diagram openload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Thermal detection / protection behavior.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Functional overview of the ALU BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 BIST sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Timing between each output test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SVDT-Timing with SPI-transfer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Passing test diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Possibilities of a passed test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Test failed: short circuit / overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Test failed: high resistive load / undercurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PowerSO-36 (slug down) mechanical data and package dimensions . . . . . . . . . . . . . . . . 78 DocID025414 Rev 1 7/80 7 8/80 DocID025414 Rev 1 3'.$ #,+). 30)#3 -)3/ -/3) 30)#,+ 6S 6S 0 /2 #LOCK K(Z BITSEACH REGISTERS 30) 6 3UPPLY 6OLTAGE 0'.$ 0'.$ 3'.$0'.$ ,OSS$ETECT $IAGNOSTIC #ONTROLLER #ONTROLLER 3YNCHRONIZATION %NABLE "UFFER 3ET0OINT #ONTROLLER 3ET0OINT #ONTROLLER #HANNEL #HANNEL 07#ONTROL 'ATE $RIVE 'ATE-ONITOR /VER #URRENT 5NDER #URRENT #URRENT3ENSE /PEN,OAD $X,OSS 4HERMAL3ENSE 0'.$ 1 $$ 1 0'.$ 1 'ATE $RIVE 'ATE-ONITOR 07#ONTROL $$ 1 /VER #URRENT 5NDER #URRENT /PEN,OAD $X,OSS 4HERMAL3ENSE #HANNEL #HANNEL 1 #URRENT #ONTROLLER %. Block diagram L9374LF Block diagram Figure 1. Block diagram '!0'03 L9374LF 2 Pins description Pins description Figure 2. PowerSO-36 pins connection (top view) .#   0'.$ 1   .# 1   .# $$   .# $$   .# 1   3'.$ 1   %. 0'.$   30)#3 0'.$   -)3/ 0'.$   -/3) 1   30)#,+ 1   #,+). .#   63 $$   .# $$   .# 1   .# 1   .# .#   0'.$ '!0'03 Table 2. Pins description Pin # Pin name Description 1 PGND 2 Q3 Output. 3 Q3 Output. 4 D1/D3 Free wheeling diode. 5 D1/D3 Free wheeling diode. 6 Q1 Output. 7 Q1 Output. 8 PGND1 Power ground of the output driver 1& 2. 9 PGND12 Power ground of the output driver 1& 2. 10 PGND2 Power ground of the output driver 1& 2. 11 Q2 Output. 12 Q2 Output. 13 N.C. 14 D4/D2 Free wheeling diode. 15 D4/D2 Free wheeling diode. 16 Q4 Not connected/Power ground. Not connected. Output. DocID025414 Rev 1 9/80 79 Pins description L9374LF Table 2. Pins description (continued) 10/80 Pin # Pin name Description 17 Q4 18 PGND Not connected/Power ground. 19 PGND4 Power ground of the output driver 4. 20 N.C. Not connected. 21 N.C. Not connected. 22 N.C. Not connected. 23 N.C. Not connected. 24 VS 25 CLKIN 26 SPICLK 27 MOSI Master Out Slave In for SPI communication. 28 MISO Master In Slave Out for SPI communication. 29 SPICS SPI chip select. 30 EN 31 SGND Signal ground. 32 N.C. Not connected. 33 N.C. Not connected. 34 N.C. Not connected. 35 N.C. Not connected. 36 PGND3 Output. Supply pin. Input for precise clock. SPI communication clock. Enable. Power ground of the output driver 3. DocID025414 Rev 1 L9374LF Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Min. Max. Unit Vs Supply voltage -0.3 38 V VDx Freewheeling diode voltage -0.3 35 V VQx Output voltage -0.3 Internally Clamped V Enable voltage SPI clock voltage SPI chip select voltage SPI MOSI voltage SPI MISO voltage SPI clock input voltage -0.3 6 V - -4 A - -2 A Input clamping currents (static) Input clamping currents (dynamic) -3 -10 +3 +10 mA Ambient operating temperature -40 +125 °C VEN VSPICLK VSPICS VMOSI VMISO VCLKIN IQ1; 2 Output current at reversal voltage IQ3; 4 IEN_CL ISPICLK_CL ISPICS_CL IMOSI_CL ICLKIN_CL Tamb Definition: Current flowing into the L9374LF are considered positive -> “+" Current flowing out of the L9374LF are considered negative -> “-" Warning: Transients beyond this limit will cause currents into ESD structures which must be limited externally to ±10 mA (maximum energy to be dissipated: 2 mJ). DocID025414 Rev 1 11/80 79 Electrical specifications L9374LF 3.2 ESD susceptibility 3.2.1 HBM ESD susceptibility HBM according to EIA/JESD 22-A 114B Table 4. HBM Pin 3.2.2 Condition Min. Max. Unit All pins - ±2 - kV Output pins DX; QX; PGND12, PGND3, PGND4, LGND and GND are connected together. ±4 - kV Min. Max. Unit ± 250 - V MM ESD susceptibility according to EIA/JESD22-A115-A Table 5. MM Parameter Condition Machine model (MM) 3.3 All pins Electrical characteristics VS = 5.2 to 20 V; -40 °C ≤ Tj ≤ 175 °C, unless otherwise specified. Function is guaranteed until thermal shutdown threshold, TSD; 3.3.1 Supply current Table 6. Supply current Symbol Parameter Condition Min Typ Max 2.0 - 7.5 - 9.0 5.2 - 20 Unit Vs = 13.5 V 3.3.2 @+175 °C @+25 °C @-40 °C IVS Supply current Vs Supply voltage operating range - mA V Output power stages The output power stages consist of an MOSFET and a freewheeling diode. Each output contains diagnostic and protection circuitry. Additional current sensing is present in the current regulated outputs (for more details see Section 4.7: Output driver). 12/80 DocID025414 Rev 1 L9374LF Electrical specifications Figure 3. Output power stages Q1/Q2 4O$Y K(Z /FF 3TATE /PEN,OAD $XY TO 20$ -58 &ROM /THER /UTPUTS 1X ),%!+ 6Z )NTERNAL 3IGNAL 3,/0%#/.42/, 0'.$XZ 4O1Z '!0'03 Table 7. Output power stages Symbol Parameter Condition Min. Typ. Max. Unit RON(Q1/Q2) Static drain-source on-resistance Q1 / Q2 IQ = 1 A (TK: 0.58 % / K; Typ @ RT) 60 140 390 mΩ RON(Q3/Q4) Static drain-source on-resistance Q3 / Q4 IQ = 1 A (TK: 0.58 % /K; Typ @ RT) 80 250 520 mΩ VZ Z-diode clamping voltage IQ = current limitation 35 - 40 V RPD Output pull down resistor (multiplexed to the 4 outputs sequentially)(1) EN = 1 20 40 100 kΩ ILEAK Output leakage current VQ = 20 V; EN = 0 V Tj =130 °C Tj = 25 °C - - 5 1 μA μA 1. RPD is sequentially connected to each output for 2 μs (8 μs period) for the purpose of detecting off-state open load. Figure 4. Output power stages Q3/Q4 4O$Y K(Z -ONITOR /PEN,OAD $XY TO 20$ -58 &ROM /THER /UTPUTS 23%.3% 1X ),%!+ 6Z )NTERNAL 3IGNAL 3,/0%#/.42/, 0'.$XZ 4O1Z '!0'03 DocID025414 Rev 1 13/80 79 Electrical specifications 3.3.3 L9374LF Freewheeling diode Table 8. Freewheeling diode electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit IFD = -1.5 A 0.5 0.75 1.75 V D3, D4 @-250 mA 0.5 1.0 1.5 V D3, D4 @-1.8 A 1.6 3.6 V VFD1/2 Forward voltage of free wheeling diodes D1 / D2 VFD3/4 Forward voltage of free wheeling path Rsense Q3/Q4 Sense resistor Calculated: (VFD_1.8A-VFD_250mA)/1.55 A RD1/3 Resistor D13-Pin VQ < VD < 18 V (Typ @ Tj = 25 °C) Ileak_Dx_0 Leakage current into Dx-Pin D13 Ileak_Dx_1/0 Ileak_Dx_1/1.8 3.3.4 - 1 - Ω 100 240 700 kΩ EN = 0 5 - 160 μA Leakage current into Dx-Pin D13 D24 EN = 1 IDAC = 0A 90 70 400 μA Leakage current into Dx-Pin D13 D24 EN = 1 IDAC = 1.8A 90 - 2400 μA Output timing characteristics The DMOS outputs have controlled slopes to minimize EME. The Edge Shaping option is programmed via SPI (See Edge shaping (EDGE_SH); without edge shaping, the slope is fixed to 10V/μs in both directions. Figure 5. Output timing characteristics diagram with edge shaping 616 6$ 3S 6&$ 6EDGE 3F T—S Where:  VD: Valve supply voltage  VFD: Forward voltage drop across the recirculation diode  VEDGE: Voltage Sf to Ss slope transition  Ss: Slow slope  Sf: Fast slope 14/80 DocID025414 Rev 1 '!0'03 L9374LF Electrical specifications Table 9. Output timing electrical characteristics(1) Symbol Vedge Sf_Q1/Q2 Parameter Condition Edge shaping threshold measured from VD Sf output on/off slope fast Q1/Q2 Ss_Q1/Q2 Ss output on/off slope slow Q1/Q2 Sf_Q3/Q4 Sf output on/off slope fast Q3/Q4 Ss_Q3/Q4 Ss output on/off slope slow Q3/Q4 VD = 20 V Iload=1.5 A resistive load Min. Typ. Max. Unit -2.2 - -1 V 3 10 17 V/μs 2 4 6 V/μs 6 13 20 V/μs 2.5 5 7.5 V/μs 1. See Figure 5 for waveform. The slope is defined between 20 % and 80 % of the edge. Symmetric switching of DMOS Figure 6. Symmetric switching of DMOS diagram 51X  TX T 4 '!0'03 A Symmetric switching is present to ensure a reliable PWM at the output. Table 10. Symmetric switching of DMOS electrical characteristics Symbol Parameter tsym1 Symmetry II with edge shaping tsym2 Symmetry II without edge shaping 3.3.5 Condition tx-dc · T< 1.5 μs dc = 50 % VQ = 10 V Min. Typ. Max. Unit -1.0 - 2.0 μs 0 - 3.0 μs Min. Typ. Max. Unit PWM output behavior (refer to Section 4.4: Set-point controller for details) Table 11. PWM output behavior characteristics Symbol Parameter Condition f_Qx Output frequency - -2 % 4 +2 % kHz DC Duty range - 0 - 100 % Duty resolution of f_A - - 0.2 - % Number of bits for duty resolution/ target current value - 9 - - DCRES NRES DocID025414 Rev 1 15/80 79 Electrical specifications L9374LF Table 11. PWM output behavior characteristics (continued) Symbol Parameter Condition Min. Typ. Max. Unit Resolution of duration t(n)RES Add. 0 bit D9 = 0 Add. 0 bit D9 = 1 NBit Number of bits for duration 1/f_A - - - 5 - - - 250 500 μs μs - - 7.75 15.5 ms ms Max. Unit 1.8 A Max. Duration t(n)MAX (25-1) x 250 μs (25-1) x 500 μs Add. 0 bit D9 = 0 Add. 0 bit D9= 1 3.3.6 Q3 / Q4 (current controller) (refer to Section 4.5: Current controller for details) Table 12. Q3 / Q4 (current controller) electrical characteristics Symbol Parameter Condition Min. Typ. IQ3/Q4 Current range - 0 IQ3/Q4_res Current resolution - - 3.5 - mA IQ3/Q4_acc Current accuracy Iload = 0 mA to 400 mA Iload > 400 mA - - ±24 ±6 mA % 3.3.7 Logic inputs / outputs Figure 7. Logic inputs 6 ) 0 5 30)#3 30)#,+ -/3) 3IGNAL %. #,+). 3IGNAL ) 0 $ '!0'03 Table 13. Logic inputs electrical characteristics Symbol VIn_low Parameter Condition Min. Typ. Max. Unit Input threshold - -0.3 - 1.0 V VIn_high Input threshold - 2.0 - 3.5 V Input threshold hysteresis - 50 100 350 mV IP-U Internal pull-up current source for SPICS, SPICLK, MOSI 0 V ≤ VIn-xy ≤ 2 V -12 -30 -60 μA IP-D Internal pull-down current source for EN, CLKIN 1 V ≤ VIn-xy ≤ 3.45 V +12 +30 +60 μA Cin Input capacitance Designed but not tested 3.5 - 7.5 pF VIn-hys 16/80 DocID025414 Rev 1 L9374LF 3.3.8 Electrical specifications Logic outputs (MISO) Figure 8. Logic outputs (MISO) circuit 6 2 0 5 4RISTATE -)3/ 2 -)3/ 3IGNAL '!0'03 Table 14. Logic outputs (MISO) electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit 0 - 0.4 V VMISO_L MISO low voltage IOut-xy ≤ 25 μA; CL ≤ 30 pF VMISO_H MISO high voltage IOut-xy ≤ -25 μA; 2.5 3.3 3.45 V RON+RMISO 40 100 400 Ω MISO pull up resistor SPICS = high → MISO in tristate mode 50 120 300 kΩ Input capacitance designed but not tested 3.5 - 7.5 pF RMISO-ON MISO ON resistance RP-U Cin 3.3.9 Diagnostic functions at output stage (refer to Section 4.8: Diagnostics for details) Table 15. Diagnostic functions at output stage electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit VOL Open load threshold output off 0.3 0.33 0.39 x VS IUC Undercurrent threshold output on 50 100 140 mA TSD Temperature shut down threshold(1) - 180 200 220 °C TW Temperature warning - 160 180 200 °C ΔTWSD Difference between TW and TSD TSD-TW 10 - 40 °C Dx loss Supply loss threshold - 32 - 39 V OC_TH_Qx = ‘01’ 5 7.5 9 A OC_TH_Qx = ‘10’ 7 8.5 10 A - 3 5 8 A 2.5 - - V - - 1 V IOC1(1/2) Overcurrent threshold 1 Q1/Q2 IOC2(1/2) Overcurrent threshold 2 Q1/Q2 IOC(3/4) Overcurrent threshold Q3/Q4 VG_ON Gate monitoring threshold Internal node VG_OFF Gate monitoring threshold IQ > 15 mA, Internal node 1. Monitoring is only active if the output is on. DocID025414 Rev 1 17/80 79 Electrical specifications 3.3.10 L9374LF General diagnostic functions (refer to Section 4.8: Diagnostics for details) Table 16. General diagnostic functions electrical characteristics Symbol VUV Parameter Condition Min. Typ. Max. Unit Under voltage threshold (VS-pin) 3.0 - 5.2 V VSG_L Signal GND loss threshold - 0.2 0.4 0.6 V VPG_L Power GND loss threshold - 0.5 - 2.5 V VPG_Lh Power GND loss hysteresis - - 1.0 - V 111 Table 17. CLKIN-monitoring characteristics Symbol Parameter Conditions Min. Typ. Max. Unit fCLKIN_H250 CLKIN monitoring @ 250 kHz-mode frequency too high set SPI bit 300 - 760 kHz fCLKIN_L250 CLKIN monitoring @ 250 kHz-mode frequency too low set SPI bit 90 - 190 kHz fCLKIN_H1M CLKIN monitoring @ 1 MHz-mode set SPI bit frequency too high 1.20 - 3.04 MHz fCLKIN_L1M CLKIN monitoring @ 1 MHz-mode set SPI bit frequency too low 0.36 - 0.76 MHz fCLKIN_OK CLKIN monitoring clear SPI bit - 250 1 - kHz MHz Min. Typ. Max. Unit 3.3.11 CLKIN frequency ok Filtering times Table 18. Failure filtering times characteristics Symbol Parameter(1) Condition tOL Openload filtering time outputs off 20 44 70 μs tUC Under current filtering time - 10 20 40 μs tOVL Overload switch-off delay time - 10 20 40 μs tSD Thermal shutdown delay time - 10 40 80 μs tTW Thermal warning filtering time - 10 20 40 μs Dx loss filtering time - 1 2 5 μs tPGND_L Power GND loss filtering time - 10 20 40 μs tSGND_L Signal GND loss filtering time - 10 20 40 μs t_EN_F EN filtering time(2) - 1.5 2 2.5 μs tCLK_F CLKIN-failure detection time - 140 200 310 μs tCURR_F Current not reachable failure filtering time - 7.75 8 8.25 ms tDX_L 1. All parameters based on valid CLKIN (250 kHz / 1 MHz) signal. 2. Digital filter only for falling edges and analog filter for both edges. 18/80 DocID025414 Rev 1 L9374LF Electrical specifications Table 19. SVDT test timing Symbol Parameter Condition Min. Typ. Max. Unit tx Minimum passing test time SVDT Enabled I_Qx < IUC 90 100 110 μs ty Maximum failing test time SVDT Enabled I_Qx < IUC 450 500 550 μs Refer to Section 4.8.13: Silent valve driver test (SVDT). 3.3.12 VD measurement (refer to Section 4.5.2 VD for details) Table 20. VD measurement electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit VDtol VD measurement accuracy VD = 10 V - - 10 % Vres Voltage resolution - - 0.1 - V Integration Time VD = 13.5 V 0.71 - ms tint VD-Integration time increases linearly with VD. Table 21. VD measurement bit values 3.3.13 SPI - bit D8 D7 D6 D5 D4 D3 D2 D1 D0 VD-value 16 V 8V 4V 2V 1V 1/2 V 1/4 V 1/8 V 1/16 V Rs measurement (refer to Section 4.5.2 : RS for details) Table 22. RS measurement electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit RS_M_ACC RS-measurement accuracy - - - 10 % RS_M_RES RS-measurement resolution - - 8.6 - mΩ Table 23. Rs SPI bit values Note: SPI - Bit D8 D7 D6 D5 D4 D3 D2 D1 D0 RS-value 4Ω 2Ω 1Ω 1/2 Ω 1/4 Ω 1/8 Ω 1/16 Ω 1/32 Ω 1/64 Ω RS-measurement time increases linearly with RS. DocID025414 Rev 1 19/80 79 Electrical specifications 3.3.14 L9374LF V_FWD measurement (refer to Section 4.5.2 : V_FWD for details) Table 24. V_FWD measurement electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit VFWD_ACC V_FWD measurement accuracy - - - 10 % VFWD_RES V_FWD measurement resolution - - 7.8 - mV - 0.5 0.7 1.3 V VFWD_MEAS Expected measured voltage range V_FWD-measurement time increases linearly with V_FWD. Table 25. V_FWD SPI bit Values 3.3.15 SPI - Bit D8 D7 D6 D5 D4 D3 D2 D1 D0 V_FWD 2V 1V 1/2 V 1/4 V 1/8 V 1/16 V 1/32 V 1/64 V 1/128 V Internal oscillator Table 26. Internal oscillator electrical characteristics Symbol fosc 3.3.16 Parameter Oscillator frequency Condition - Min. Typ. Max. Unit 1.4 2.0 2.6 MHz SPI timing characteristics SPICLK, MISO, MOSI, SPICS Figure 9. SPI timing characteristics SPICLK, MISO, MOSI, SPICS T30)#3 HIGH T30)#3 LOW 30)#3 TLEAD TRISE TFALL TLAG T30)#LK HIGH T30)#LK LOW  6HIGH 30)#LK  6HIGH -/3) T-/3) STABLE T-)3/ DELAY T-)3/ TRISTATE -)3/ '!0'03 20/80 DocID025414 Rev 1 L9374LF Electrical specifications Table 27. SPI timing characteristics Symbol fSPICLK Parameter SPICLK frequency tSPICLK-high, SPICLK high time / low time tSPICLK-low Conditions Min. Typ. Max. Unit Cload ≤ 30 pF 0 - 5 MHz - 68 - - ns tlead SPICS -> SPICLK delay - 80 - - ns tlag SPICLK -> SPICS delay - 60 - - ns - 68 - - ns SPICLK, MOSI rise time / fall time Cload ≤ 150 pF 0 - 100 ns tMISO-delay SPICLK -> MISO delay Cload ≤ 150 pF - - 80 ns tMISO-rise, tMISO-fall MISO rise time / fall time(1) Cload ≤ 15 pF Cload ≤ 50 pF Cload ≤ 65 pF 0.8 2.5 3.5 2 7 9 7 21 28 ns ns ns tSPICS-high SPICS high time / low time Cload ≤ 150 pF 150 - - ns MISO tri-state Cload ≤ 150 pF - - 100 ns tMOSI-stable MOSI stable trise/tfall tMISO_tri 1. guaranteed by design Note: The MISO pin is tri-stated with a weak pull-up when SPICS is high. DocID025414 Rev 1 21/80 79 Circuit description 4 L9374LF Circuit description The L9374LF is a four channel low side driver with integrated recirculation diodes intended for ABS applications. The device communicates entirely by 16 individual SPI commands. All outputs can be switched or PWMed. Two outputs have the additional capability of providing current regulation It is possible to program two consecutive PWM duty cycles / Current levels at one time. Individual switched on-times can also be generated. All outputs have high level diagnostic capabilities. These include off state open load, under current, shorted load, gate voltage monitoring, thermal warning and shutdown flags. Higher level diagnostics include a Silent-Valve-Detection-test (SVDT) to verify load and driver integrity as well as a Built-in-Self-test (BIST) to verify the internal logic integrity. The L9374LF can detect and report a missing recirculation diode, Ground loss, Clock failure, and synchronization failure. 4.1 SPI serial peripheral interface The L9374LF SPI is a fully bidirectional serial interface configured as a SLAVE for communication between a μC (the MASTER) and the L9374LF. All data management is handled in 16 sets of SPI registers of 16 bits each. There are 16 input or command registers and 16 status registers. All output control including current control and PWM / switching timing is realized internally. The control parameters (Duty Cycle, Duration, and Current regulation) are programmed via serial communication. The 16 status registers provide a high level of diagnostic capability from output status to internal control parameter confirmation. Figure 10. SPI block diagram 0 BUFFERSTORE 30)#,+ ADDRESSDECODER PARITY GENERATOR $ATA 30) -/3) -)3/ DATA?INDATA?OUT DATA?IN X"IT DATA?OUT X"IT 30)?3YNC?!DD?FLAG !DD 30)#3 FAILURE DETECTION RELEASEBLOCK FAILUREDETECTION '!0'03 22/80 DocID025414 Rev 1 L9374LF Circuit description Messages from the master (μC) to the L9374LF is sent over the MOSI (Master out Slave In) pin. Messages from the L9374LF to the master will be sent over the MISO (Master in Slave Out) pin. The master starts the communication with a '1'  '0' transition on the SPICS pin. After tLEAD,(Table 27.) the master sends a clock signal to the SPICLK and data to the MOSI pin. The SPICLK pin must be low at the falling edge of SPICS and remain low for tLEAD for correct communication to occur. The SPICS pin must rise after every 16 bits sent. The MISO pin is tri-stated with an high ohmic pull-up resistor when the SPI chip select (SPICS) pin is held high. The SPI has the following features:  4 wire SPI (SPICS, SPICLK, MOSI, MISO)  Word length of 16-Bits (0..15)  4 address and 11 data bits and one parity bit  16 receive-buffers (11 bit wide)  16 send-buffers (11 bit wide) 4.1.1 General protocol The protocol has the following structure:  A parity-bit at the LSB and eleven data bits (bits 1 to 11).  The four address bits are at the highest position at the transfer (bits 12 - 15).  SPI communication begins with the MSB.  High level = '1'  Low level = '0' Figure 11. General SPI protocol -3" ! ,3" ! ! ! $ $ $ $ $ $ $ $ $ $ $ 0 '!0'03    Ax: address bits Dx: data bits P: parity bit A message from the L9374LF to the master μC (MISO) contains 4 address bits. These bits are not a copy of the received address from the previous transmission, but are addresses that were decoded from the address decoder. This is done so that the master (μC) has the ability to discern the integrity of the L9374LF address decoder. Every time an error bit in one of the SPI registers is set by the L9374LF it will remain set until the corresponding register has been read out via SPI. Once a status register has been read the corresponding register will be reset upon the rising edge of SPICS. Every SPI communication writes data into a register (read only not possible). Every SPI response is associated with the address of the message sent one communication before. DocID025414 Rev 1 23/80 79 Circuit description 4.1.2 L9374LF SPI failure detection SPI communications sent to the L9374LF that contain errors are ignored. This inaction includes both the commands given and the data retrieved. That is, commands are ignored and the initial state of the output is not changed. Also data registers referenced by the erroneous SPI communication will not be reset. Figure 12. SPI error handling FAILURE AFTERFILTERTIME TY FAILUREISDETECTED 30)BITISSET 30)BIT ADDRX"ITY TY AFTERSENDING ADDRXBITY VIA30)BITIS CLEARED VALUEISSEND VIA30) ADDRXBITY 30)#3 NO30) FAILURE DETECTED NO30) FAILURE DETECTED NO30) FAILURE DETECTED —#TO!3)# ACCESSTO ADDRX BY —# ACCESSTO ADDRXBY —# ACCESSTO ADDRXBY —# !3)#TO—# !3)#ANSWER !3)#ANSWER ADDRX  !3)#ANSWER ADDRX BITY '!0'03 Three functions are monitored to discern a correct SPI communication from the master: 1. Correct number of Clock pulses in SPICLK per transfer. During each SPICS-low-phase the L9374LF counts the number of positive edges of SPICLK. If this number is unequal to 16 a SPICLK-error is detected. 2. Parity check (odd) The L9374LF detects a parity error if the number of ‘1’s within a transfer is even. 3. Data-failure monitoring: This bit is set if the master writes inappropriate data to any of the configuration registers (2/14/15). 4.1.3 Data transfer Upon the completion of each 16 bit SPI command (rising edge of SPICS), data is transferred from the SPI block to the appropriate internal registers. Some internal SPI registers are reset (such as fault bits) once they are accessed. 24/80 DocID025414 Rev 1 L9374LF 4.1.4 Circuit description Address decoder The address decoder routes incoming data into the appropriate receive buffer and sets up the appropriate send buffer register to transmit information back to the master (MISO) for the subsequent SPI communication. 4.1.5 Parity generator The parity generator completes the output messages with a parity bit. The number of ‘1’s within an output-transfer has to be odd. Parity is verified prior to the SPICS going high. 4.1.6 Initial MISO information After initial power on, the first SPI-answer from the L9374LF reflects the Chip-ID information. Typically, the information will appear as follows: A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 0 This information is unique to this device and reflects specific device information relevant only to ST. 4.1.7 Register map This is a brief reference to the register locations within the L9374LF. Refer to Section 5: Programmers guide for a more detailed description of each register. Command buffer (data in) Table 28. Command buffer (data_in) Address(HEX) Content Buffer name 0 Sync-trigger, Reset, and Sync values SYNC_REG 1 STW min and max values STW_V 2 Configuration register CONFIG 1 3 Fast Switch ON gate commands FSON 4 Duration Registers doe Q1 /Q2 Duration Q1/Q2 5 Duration of current 1 Q3 + duration of current 1 Q4 Duration Q3/Q4 6 Duty cycle 1 Q1 DUTY1_Q1 7 Duty cycle 2 Q1 DUTY2_Q1 8 Duty cycle 1 Q2 DUTY1_Q2 9 Duty cycle 2 Q2 DUTY2_Q2 10 Current/duty cycle1 Q3 CUR/DTY1_Q3 11 Current/duty cycle 2 Q3 CUR/DTY2_Q3 12 Current/duty cycle 1 Q4 CUR/DTY1_Q4 13 Current/duty cycle 2 Q4 CUR/DTY2_Q4 14 Current / PWM controller configuration register 2 CONFIG 2 15 Current / PWM controller configuration register 3 CONFIG 3 DocID025414 Rev 1 25/80 79 Circuit description L9374LF Status buffer (data out) Table 29. Status buffer (data_out) Address(HEX) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Content Buffer name General status Q1 output status register Q2 output status register Q3 output status register Q4 output status register Voltage of Dx Output-duty Q3 Output-duty Q4 ISAT value for Q3 ISAT value for Q4 Internal diode Voltage measurement Measurement resistor Current controller status Error average Q3 Error average Q4 Reserved → data ‚000 0000 0000‘ G_STATUS STATUS_Q1 STATUS_Q2 STATUS_Q3 STATUS_Q4 VD OUT_DUTY_Q3 OUT_DUTY_Q4 ISAT_Q3 ISAT_Q4 V_FWD RS CC-STATUS ERRORAVG_Q3 ERRORAVG_Q4 RESERVED A more detailed explanation about the register settings can be found in section Section 5: Programmers guide. 4.2 Clock The clock controller contains a CLKIN-monitoring function to validate the CLKIN frequency, a clock multiplier to produce an internal 2 MHz clock, and an internal oscillator for monitoring purposes and backup. Figure 13. Clock block diagram )NTERNAL #,+).-ONITOR -(Z /SCILLATOR #,+). #,+).?3 K(Z -(Z   OR  3WITCH #,+).?& F#,+ K(Z X -ULTIPLIER -(Z '!0'03 4.2.1 Clock multiplier The Clock Multiplier provides a steady 2MHz signal (fCLK) for the internal logic based on the CLKIN signal. The multiplier factor is determined by setting the CLKIN_S bits in the SPI Command register Configuration register 1 (address 2). It is possible to have the wrong CLKIN_S bits set for a specific CLKIN frequency. When this occurs a CLKIN failure (CLKIN_F) is registered. 26/80 DocID025414 Rev 1 L9374LF 4.2.2 Circuit description Internal oscillator The 2MHz internal oscillator (fosc, Table 26.) provides a comparison signal used to validate the incoming CLKIN signal. If the CLKIN signal is determined to be out of range then the internal oscillator is used to provide clock signals internal to the L9374LF. The internal oscillator does not have the accuracy of a proper CLKIN signal. Therefore the diagnostic filter times will reflect the accuracy of this clock for that case. 4.2.3 CLKIN signal monitoring The CLKIN signal is an external 250 kHz or 1MHz signal from the μC to the L9374LF. This signal is monitored to be within a specified range (fCLKIN_L