L99DZ100G, L99DZ100GP
Automotive door module with LIN and HS-CAN (L99DZ100G) or
HS-CAN supporting selective wake up (L99DZ100GP)
Datasheet - production data
All the embedded outputs come with protection
and supervision features:
– Current Monitor (high-side only)
– Open-load
– Overcurrent
– Thermal warning
– Thermal shutdown
Fully protected driver for external MOSFETs in
H-bridge configuration or dual Half bridge
configuration
Features
AEC Q100 compliant qualified
1 half bridge for 7.5 A load (RON = 100 mΩ)
1 half bridge for 7.5 A load (RON = 150 mΩ)
2 half bridges for 0.5 A load (RON = 2000 mΩ)
2 half bridges for 3 A load (RON = 300 mΩ)
1 configurable high-side driver for up to 1.5 A
(RON = 500 mΩ) or 0.35 A (RON = 1600 mΩ)
load
1 configurable high-side driver for 0.8 A
(RON = 800 mΩ) or 0.35 A (RON = 1600 mΩ)
load
3 configurable high-side drivers for
0.15 A/0.35 A (RON =2 Ω)
1 configurable high-side driver for 0.25 A/0.5 A
(RON = 2 Ω) to supply EC Glass MOSFET
Fully protected driver for external high-side
MOSFET
Control block for electro-chromic element
Two 5 V voltage regulators for microcontroller
and peripheral supply
Programmable reset generator for power-on
and undervoltage
Configurable window watchdog
LIN 2.2a compliant (SAEJ2602 compatible)
transceiver
Advanced high speed CAN transceiver (ISO
11898-2:2003 /-5:2007 and SAE J2284
compliant) with local failure and bus failure
diagnosis and selective wake-up functionality
according to ISO 11898-6:2013
4 configurable high-side drivers for
0.15 A/0.25 A (RON = 5 Ω)
Separated (Isolated) fail-safe block with 2 LS
(RON = 1 Ω) to pull down the gates of the
external HS MOSFETs
Internal 10bit PWM timer for each stand-alone
high-side driver
Thermal clusters
Buffered supply for voltage regulators and 2
high-side drivers (OUT15 & OUT_HS / both
P-channel) to supply e.g. external contacts
Programmable soft-start function to drive loads
with higher inrush currents as current limitation
value (for OUT1-6, OUT7, OUT8 and
OUT_HS) with thermal expiration feature
March 2019
This is information on a product in full production.
A/D conversion of supply voltages and internal
temperature sensors
Embedded and programmable VS duty cycle
adjustment for LED driver outputs
Applications
Door zone applications.
DS11546 Rev 5
1/197
www.st.com
L99DZ100G, L99DZ100GP
Table 1. Device summary
Order codes
Package
Variant
LQFP-64 epad
High Speed CAN Transceiver with partial networking
(ISO 11898-6:2013)
LQFP-64 epad
High Speed CAN Transceiver (ISO 11898-2:2003
and 11898-5:2007)
Product label
2/197
DS11546 Rev 5
Tray
Tape and reel
L99DZ100GP
L99DZ100GPTR
L99DZ100G
L99DZ100GTR
L99DZ100G, L99DZ100GP
Contents
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2
Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.1
3.4
LQFP64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.3
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.5
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.6
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.7
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.8
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.9
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.10
Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . 38
3.4.11
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4.12
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.13
Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.4.14
H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4.15
Gate drivers for the external Power-MOS switching times . . . . . . . . . . 45
3.4.16
Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . 48
3.4.17
Drain source monitoring external heater MOSFET . . . . . . . . . . . . . . . . 49
3.4.18
Open-load monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4.19
Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . 50
3.4.20
Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.21
Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.22
Wake up input WU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.23
High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.24
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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L99DZ100G, L99DZ100GP
3.4.25
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.4.26
Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . 63
3.4.27
Inputs DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.28
Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.29
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.4.30
Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.31
Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.4.32
Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.4.33
SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1
Supply VS, VSREG
4.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3
4.4
4.2.1
Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2.2
Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.3
Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.4
Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2.5
Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3.1
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3.2
Flash modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.3
SW-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.4
V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.5
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.6
CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.3.7
VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Wake-up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4.1
Wake up input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.6
Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.6.1
4.7
4/197
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.7.1
Temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.7.2
Non-recoverable failures – forced Vbat_standby mode . . . . . . . . . . . . . 83
4.8
Reset output (NReset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.9
LIN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.10
Contents
4.9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.9.2
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.9.3
Wake up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.9.4
Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
High-speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.10.1
Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.10.2
CAN transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.10.3
Automatic voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.10.4
Wake-up by CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.10.5
CAN looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.10.6
Pretended networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.10.7
CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.11
Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 93
4.12
Power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.12.1
VS supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.12.2
VSREG supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.13
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 97
4.14
Power outputs OUT1..15 and OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.15
Auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 99
4.16
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.17
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.18
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.19
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.20
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.21
PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.22
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.23
Programmable soft-start function to drive loads with higher inrush current .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.24
H-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.25
H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.26
Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.27
Short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . 108
4.28
H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.29
Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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L99DZ100G, L99DZ100GP
4.30
Power window H-bridge safety switch off block . . . . . . . . . . . . . . . . . . . . 111
4.31
Heater MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
4.32
Controller of electro-chromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
4.33
Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
4.34
Thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
4.35
VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . .117
4.36
Analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1
ST SPI 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1.1
5.2
Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.2.1
Clock and Data Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.2
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.2.3
Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.4
Protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6/197
7.1
Global Status Byte GSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.2
Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.3
Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
7.4
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.4.1
Control Register CR1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.4.2
Control Register CR2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.4.3
Control Register CR3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.4.4
Control Register CR4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.4.5
Control Register CR5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.4.6
Control Register CR6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.4.7
Control Register CR7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.4.8
Control Register CR8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
7.4.9
Control Register CR9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.4.10
Control Register CR10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
7.4.11
Control Register CR11 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
7.4.12
Control Register CR12 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Contents
7.4.13
Control Register CR13 (0x0D) to CR17 (0x11) . . . . . . . . . . . . . . . . . . 167
7.4.14
Control Register CR18 (0x12) to CR22 (0x16) . . . . . . . . . . . . . . . . . . 168
7.4.15
Control Register CR23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.4.16
Control Register CR24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7.4.17
Control Register CR25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.4.18
Control Register CR26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.4.19
Control Register CR27 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.4.20
Control Register CR28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7.4.21
Control Register CR29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.4.22
Control Register CR34 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
7.4.23
Configuration Register (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.5
8
9
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.5.1
Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.5.2
Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.5.3
Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.5.4
Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.5.5
Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.5.6
Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.5.7
Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . 188
7.5.8
Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.5.9
Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.5.10
Status Register SR12 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
8.1
LQFP-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
8.2
LQFP-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
DS11546 Rev 5
7/197
7
List of tables
L99DZ100G, L99DZ100GP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
8/197
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Charge pump electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . . 45
Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Drain source monitoring external heater MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Open-load monitoring external H-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CAN transmit data input: pin TxDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CAN receive data output: Pin RxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CAN transmitter dominant output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CAN transmitter recessive output characteristics, CAN normal mode . . . . . . . . . . . . . . . . 54
CAN transmitter recessive output characteristics, CAN low-power mode, biasing active . 54
CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive 55
CAN receiver input characteristics during CAN normal mode . . . . . . . . . . . . . . . . . . . . . . 55
CAN receiver input characteristics during CAN low power mode, biasing active . . . . . . . . 55
CAN Receiver input characteristics during CAN Low power mode, biasing inactive . . . . . 56
CAN receiver input resistance biasing active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CAN transceiver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Maximum leakage currents on CAN_H and CAN_L, unpowered . . . . . . . . . . . . . . . . . . . . 57
Biasing control timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LIN transmit data input: pin TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN receive data output: pin RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
List of tables
DI, CLK and CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Inputs: TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Inputs DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Wake-up events description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Status of different functions/features vs operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 77
Temporary failures description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Non-recoverable failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Power output settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
H-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Heater MOSFET control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Global Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RAM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ROM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Information Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Burst Read Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SPI Data Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Data Consistency Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
WD Type/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
WD bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Global Status Byte (GSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
GSB signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Control Register CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
CR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Wake-up input1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CAN transceiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Voltage regulator V2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Standby transition configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Control Register CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Configuration of Timer x on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Control Register CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
CR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Control Register CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
CR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
DS11546 Rev 5
9/197
11
List of tables
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
10/197
L99DZ100G, L99DZ100GP
Control Register CR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
CR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
OUTx Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Control Register CR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
CR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Control Register CR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
CR7 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Half-bridge minimum ON time and related overcurrent recovery frequency. . . . . . . . . . . 160
High-side minimum ON time and related overcurrent recovery frequency . . . . . . . . . . . . 160
Control Register CR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
CR8 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Control Register CR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
CR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Control Register CR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
CR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Control Register CR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
CR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Control Register CR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
CR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Control Register CR13 to CR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
CR13 to CR17 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Control Register CR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
CR18 to CR22 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Control Register CR23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
CR23 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Control Register CR24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
CR24 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Control Register CR25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
CR25 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Control Register CR26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
CR26 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Control Register CR27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
CR27 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Control Register CR28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
CR28 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Control Register CR29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
CR29 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Control Register CR34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
CR34 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
CR signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
SR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
SR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
SR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
List of tables
SR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
SR7 to SR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
SR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
SR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Status Register SR12 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
SR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
LQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
DS11546 Rev 5
11/197
11
List of figures
L99DZ100G, L99DZ100GP
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
12/197
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Activation profile 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Activation profile 1 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Activation profile 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Activation profile 2 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LQFP64 package and PCB thermal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator V1 characteristics (quiescent current and accuracy) . . . . . . . . . . . . . . . 31
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SPI input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPI CSN - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SPI – CSN high to low transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 69
Voltage regulator behaviour and diagnosis during supply voltage . . . . . . . . . . . . . . . . . . . 72
Sequence to disable/enable the watchdog in CAN Flash mode . . . . . . . . . . . . . . . . . . . . . 73
NINT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
NReset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
RxDL pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Wake-up behavior according to LIN 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RxDC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
CAN transceiver state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR, thermal
expiration occurs after a ∆T = 30° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Block diagram of physical realization of AR alert and thermal expiration . . . . . . . . . . . . . 101
Charge pump low filtering and start up implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Software strategy for half bridges before applying auto-recovery mode. . . . . . . . . . . . . . 104
Overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
H-bridge open-load-detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 109
H-bridge open-load-detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
H-bridge open-load-detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . 110
H-bridge open-load detection (short to VS detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PWMH cross current protection time implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LSx_FSO: low-side driver “passively” turned on, taking supply from output pin (if main supply
fails), can guarantee VLSx_FSO < VOUT_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
List of figures
Safety concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Heater MOSFET open-load and short-circuit to GND detection . . . . . . . . . . . . . . . . . . . . 113
Electro-chrome control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Thermal clusters identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Block diagram VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 118
Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6 . . . . . . . . . . . . . . . . 119
SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SDI Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Timer_x controlled by DIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Extended ID and extended ID mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
LQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
LQFP-64 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
LQFP-64 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
DS11546 Rev 5
13/197
13
Description
1
L99DZ100G, L99DZ100GP
Description
The L99DZ100G and L99DZ100GP are door zone systems IC providing electronic control
modules with enhanced power management power supply functionality, including various
standby modes, as well as LIN and HS CAN physical communication layers.
The two low-drop voltage regulators of the devices supply the system microcontroller and
external peripheral loads such as sensors and provide enhanced system standby
functionality with programmable local and remote wake-up capability. In addition 8 high-side
drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration
level.
Up to 5 DC motors and 4 external MOS transistors in H-bridge configuration can be driven.
An additional gate drive can control an external MOSFET in high-side configuration to
supply a resistive load connected to GND (e.g. mirror heater). An electro-chromic mirror
glass can be controlled using the integrated SPI-driven module in conjunction with an
external MOS transistor. All outputs are SC protected and implement an open-load
diagnosis.
The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables
generic software development.
14/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Block diagram and pin descriptions
Figure 1. Block diagram
&33 &3 96
287 P
$
&30
&KDUJH
3XPS
&33
&30
$
287 P
287 P
$
*+
$
287 P
6+
*/
$
287 P
[
'ULYHU,QWHUIDFH/RJLF 'LDJQRVWLF
$
287 P
',5+
3:0+
/6B)62
/6B)62
)DLO6DIH
[
965(*
9B
15(6(7
95(*
9B
95(*
&$16XSSO\
5['B&1,17
7['B&
&$1B+
&$1B/
5['B/1,17
7['B/
/,1
'HEXJ
/,1
287 P
$UHVS
$ :DWW%XOE
+6
287 P
$UHVS
$ :DWW%XOE
+6
287
$$
+6
287
$ !7RGULYH(&026)(7DVZHOO
+6
287
P$
+6
287
P$
+6
287
P$
+6
P$
287
*+KHDWHU
6+KHDWHU
+6
3&KDQQHO
1,17
:8
+6
965(*
[7M
&O
3&KDQQHO
96
[7M
&O
&61
&/.
',
'2
&0
+6
%XI IHUHG 96
+6&$1
ZLWK31
P$
287
287B+6
P$
',5
',5
%LW
$'&6$5
63,,QW HUI DF H
:LQG RZ
:DW FKG RJ
2
Block diagram and pin descriptions
(&*ODVV
&RQWURO%ORFN
%,763,FRQWUROOHG
*1'
6*1'
(&'5
(&9
3*1'
*$3*&)7
Table 2. Pin definitions and functions
Pin
Symbol
Function
1
WU
Wake-up Input: Input pin for static or cyclic monitoring of external contacts
2
CP2M
Charge pump pin for capacitor 2, negative side
3
CP2P
Charge pump pin for capacitor 2, positive side
4
CP
5
CP1P
Charge pump pin for capacitor 1, positive side
6
CP1M
Charge pump pin for capacitor 1, negative side
Charge pump output
DS11546 Rev 5
15/197
196
Block diagram and pin descriptions
L99DZ100G, L99DZ100GP
Table 2. Pin definitions and functions (continued)
Pin
Symbol
7
GHheater
Gate driver for external power N-Channel MOSFET in high-side
configuration to control the heater
8
SHheater
Source of high-side MOSFET to control the heater
9
OUT14
High-side-driver output to drive LEDs
10
OUT13
High-side-driver output to drive LEDs
11
OUT12
High-side-driver output to drive LEDs
12
OUT9
High-side-driver output to drive LEDs
13
OUT10
High-side-driver-output; Important: Beside the bits OUT10_x (CR 5) this
output can be switched on setting the ECON bit for electro-chrome control
mode with higher priority.
14
OUT11
High-side-driver output to drive LEDs
15
LS1_FSO
Fail Safe low-side switch (Active low)
16
LS2_FSO
Fail Safe low-side switch (Active low)
Power supply voltage for power stage outputs (external reverse battery
protection required), for this input a ceramic capacitor as close as
possible to GND is recommended. Important: For the capability of driving,
the full current at the outputs all pins of VS must be connected externally!
17
VS
18
VS; 2nd pin
19
OUT7
High-side-driver output to drive LEDs or a 10 Watt bulb (programmable
Rdson)
OUT6
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
OUT1
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
OUT2
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
23
OUT5
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
24
OUT5; 2nd pin
20
21
22
16/197
Function
Current capability (pin description see above)
Current capability (pin description see above)
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Block diagram and pin descriptions
Table 2. Pin definitions and functions (continued)
Pin
Symbol
Function
25
VSREG
Power supply voltage to supply the internal voltage regulators, OUT15
and the OUT_HS (external reverse battery protection required / Diode) for
this input a ceramic capacitor as close as possible to GND and an
electrolytic back up capacitor is recommended.
26
OUT_HS
27
OUT4
28
OUT4; 2nd pin
High-side-driver output to drive LEDs or to supply contacts
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
Current capability (pin description see above)
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
29
OUT3
30
VS; 3rd pin
31
OUT15
High-side-driver output to drive LEDs
32
PGND
Power GND
33
OUT8
High-side-driver output to drive LEDs or a 5 Watt bulb (programmable
Rdson)
34
ECDR
ECDR: using the device in EC control mode this pin is used to control the
gate of an external N-Channel MOSFET
35
SGND
Signal Ground
Current capability (for the pin description see above)
36
CM
Current monitor output: depending on the selected multiplexer bits
CM_SEL_x (CR 7) of the; Control Register this output sources an image
of the instant current; through the corresponding high-side driver with a
fixed ratio
37
ECV
ECV: using the device in EC control mode this pin is used as voltage
monitor input. For fast discharge an additional low-side-switch is
implemented
38
CLK
SPI: serial clock input
39
DO
SPI: serial data output (push pull output stage)
40
DI
SPI: serial data input
41
CSN
42
TxD_L
43
RxD_L/NINT
44
TxD_C
45
RxD_C/NINT
46
DIR1
SPI: chip select not input
LIN Transmit data input
RxDL -> LIN receive data output; NINT -> indicates local/remote wake-up
events (push pull output stage)
CAN transmit data input
CAN receive data output NINT -> indicates local/remote wake-up events
(push pull output stage)
Direct Drive Input 1
DS11546 Rev 5
17/197
196
Block diagram and pin descriptions
L99DZ100G, L99DZ100GP
Table 2. Pin definitions and functions (continued)
18/197
Pin
Symbol
Function
47
PWMH
PWMH input: this input signal can be used to control the H-bridge Gate
Drivers.
48
DIRH
Direction Input: this input controls the H-bridge Drivers for the external
MOSFETs
49
DIR2
Direct Drive Input 2
50
NRESET
51
5V_1
52
CAN Supply
53
NINT
54
CAN_L
CAN low level voltage I/O
55
CAN_H
CAN high level voltage I/O
56
Debug
Debug input to deactivate the window watchdog (high active)
57
LIN
58
5V_2
Voltage regulator 2 output: 5 V supply for external loads (potentiometer,
sensors) or CAN Transceiver. V2 is protected against reverse supply
59
GL1
Gate driver for PowerMOS low-side switch in half-bridge 1
60
SH1
Source of high-side switch in half-bridge 1
61
GH1
Gate driver for PowerMOS high-side switch in half-bridge 1
62
GH2
Gate driver for PowerMOS high-side switch in half-bridge 2
63
SH2
Source of high-side switch in half-bridge 2
64
GL2
Gate driver for PowerMOS low-side switch in half-bridge 2
NReset output to micro controller; (reset state = LOW) (Low-side switch
with drain connected to the output pin and internal pull up resistance to
5V_1)
Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN
transceiver
CAN supply input; to allow external CAN supply from V1 or V2 regulator
Interrupt output (low active; push-pull output stage) to indicate VSREG
early warning (Active mode); indicates wake-up events from V1_standby
mode
LIN bus line
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Block diagram and pin descriptions
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Figure 2. Pin connection (top view)
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287
287
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287
287
287
287
287
287
287
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DS11546 Rev 5
19/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
3
Electrical specifications
3.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability
Table 3. Absolute maximum ratings
Symbol
Value [DC voltage]
Unit
DC supply voltage / “jump start”
-0.3 to +28
V
Load dump
-0.3 to +40
V
Stabilized supply voltage, logic supply
-0.3 to 6.5
V1 < VSREG
V
Stabilized supply voltage
-0.3 to +28(2)
V
-0.3 to V1+0.3
V
Multi Level Inputs
-0.3 to 40
V
Debug input pin voltage range
-0.3 to 40
V
Output voltage range of Fail-Safe Low-side
Switches
-0.3 to 35
V
DC Wake up input voltage / “jump start”
-0.3 to +28
V
Load dump
-0.3 to +40
V
LIN bus I/O voltage range
-20 to +40
V
Current injection into VS related input pins
20
mA
IOUT_INJ(3)
Current injection into VS related outputs
20
mA
VCANSUP
CAN supply
-0.3 to +5.25
V
VS, VSREG
5V_1
5V_2(1)
Parameter / test condition
VDI, VCLK VCSN VDO,
VRXDL/NINT, VRXDC,
VNRESET, VCM, VDIR, Logic input / output voltage range
VDIR2, VPWMH,
VDIRH, VINT
VTXDC, VTXDL
VDebug
VLS1_FSO, VLS2_FSO
VWU
VLIN
IInput(3)
VCANH, VCANL
CAN bus I/O voltage range
-27 to +40
V
VCANH - VCANL
Differential CAN-Bus Voltage
-5 to +10
V
-0.3 to VS+0.3
V
VOUTn, VECDR, VECV,
Output voltage (n = 1 to 15)
Vout_HS
20/197
VGH1, VGH2 (VGxy)
High Voltage Signal Pins
VSxy-0.3 to
VSxy+13; VCP+0.3
V
VGL1, VGL2, (VGxy)
High Voltage Signal Pins
VSxy-0.3 to
VSxy+13; VCP-0.3V
to +12V; Vcp+0.3V
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Table 3. Absolute maximum ratings (continued)
Symbol
VSH1, VSH2 (VSxy)
Parameter / test condition
Value [DC voltage]
Unit
High Voltage Signal Pins
-1 to 40
V
High Voltage Signal Pins; single pulse with
tmax = 200ns
-5 to 40
V
VCP1P
High Voltage Signal Pins
VS-0.3 to VS+14
V
VCP2P
High Voltage Signal Pins
VS-0.6 to VS+14
V
VCP1M, VCP2M
High Voltage Signal Pins
-0.3 to VS+0.3
V
High Voltage Signal Pin VS ≤ 26 V
VS-0.3 to VS+14
V
High Voltage Signal Pin VS > 26 V
VS-0.3 to +40
V
VGH_heater
VSheater -0.3 to
VSheater+13;
VCP+0.3
V
VSH_heater
-0.3 to 40V
Or -0.3 to Vs+0.3
V
ISH_Heater
+/-10
mA
IECV, IOUT2, IOUT3,
IOUT9, IOUT10, IOUT11,
IOUT12, IOUT13,
IOUT14, IOUT15,
IOUT_HS
±1.25
A
±2.5
A
IOUT7
±5
A
IOUT1,6
±5
A
IOUT4,5
±10
A
VCP
IOUT8
Output current(2)
IVScum
Maximum cumulated current at VS drawn by
OUT1 & OUT2(2)
±7.5
A
IVScum
Maximum cumulated current at VS drawn by
OUT3, OUT8 & OUT10(2)
±2.5
A
IVScum
Maximum cumulated current at VS drawn by
OUT4(2)
±10
A
IVScum
Maximum cumulated current at VS drawn by
OUT5(2)
±10
A
IVScum
Maximum cumulated current at VS drawn by
OUT6 & OUT7(2)
±7.5
A
IVScum
Maximum cumulated current at VS drawn by
OUT9, OUT11, OUT12, OUT13, OUT14,
OUT15 and CP
±2.5
A
IVSREG
Maximum current at VSREG pin (2) (5V_1. 5V_2
and OUT_HS)
±2.5
A
Maximum cumulated current at PGND drawn
by OUT1 & OUT6(2)
±7.5
A
IPGNDcum
DS11546 Rev 5
21/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 3. Absolute maximum ratings (continued)
Symbol
Parameter / test condition
Value [DC voltage]
Unit
IPGNDcum
Maximum cumulated current at PGND drawn
by OUT2 & OUT5(2)
±12.5
A
IPGNDcum
Maximum cumulated current at PGND drawn
by OUT3, OUT4 & ECV(2)
±12.5
A
Maximum current at SGND(2)
±1.25
A
-0.3 to 0.3
V
ISGND
GND pins
PGND versus SGND
1. 5V_2 is robust against SC to 28 V only in case VSREG is supplied.
2. Values for the absolute maximum DC current through the bond wires. This value does not consider
maximum power dissipation or other limits.
3. Guaranteed by design.
Note:
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
Note:
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds,
the current load must be limited to this nominal current.
3.2
ESD protection
Table 4. ESD protection
Parameter
All pins(1)
All power output pins
(2):
OUT1 – OUT15, OUT_HS, ECV
Value
Unit
+/-2
kV
+/-4
kV
+/-8(2)
+/-9(3) (4)
+/-6(5)
LIN
kV
+/-8(2)
+/-6(5) (4)
kV
All pins(6)
+/-500
V
Corner pins(6)
+/-750
V
pins(7)
+/- 200
V
CAN_H, CAN_L
All
1. HBM (human body model, 100 pF, 1.5 kΩ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.
2. HBM with all none zapped pins grounded.
3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω) and ‘Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
4. Value has been verified by an external test house; the result was equal or better than minimum
requirement.
5. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω) and ‘Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
6. Charged device model.
7. Machine model; C = 220 pF, R = 0 Ω.
22/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
3.3
Electrical specifications
Thermal data
Table 5. Operating junction temperature
Symbol
Tj
Parameter
Operating junction temperature
Value
Unit
-40 to 175
°C
All parameters are guaranteed in the junction temperature range -40 to 150°C (unless
otherwise specified); the device is still operative and functional at higher temperatures (up to
175°C).
Note:
Parameters limits at higher junction temperatures than 150°C may change respect to what
is specified as per the standard temperature range.
Note:
Device functionality at high junction temperature is guaranteed by characterization.
Table 6. Temperature warning and thermal shutdown
Symbol
TW
Parameter
Thermal overtemperature warning threshold
Min.
Typ.
Max.
Unit
140
150
160
°C
Cluster 1-4
Cluster 5-6
165
165
175
175
185
190
°C
Tj(1)
175
185
195
°C
Tj(1)
Tj(1)
TSD1
TSD2
TSD12hys
Tjtft
Thermal shutdown junction temperature 1
Thermal shutdown junction temperature 2
Thermal warning / shutdown filter time
Hysteresis
5
°C
32
µs
1. Non-overlapping.
3.3.1
LQFP64 thermal data
Devices belonging to L99DZxxx family embed a multitude of junctions (i.e. Outputs based
on a PowerMOSFET stage) housed in a relatively small piece of silicon. The devices
contain, among all the described features, 6 Half-bridges (12 N-Channel PowerMOS), 10
high-sides and two voltage regulators; all the other derivatives, even if smaller than the
family super set device, still contain a significant number of junctions.
For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or
major power dissipation contributor) does not allow to predict thermal behavior of the whole
device and therefore it is not possible to assess if a device is thermally suitable for a given
activation profile and loads characteristics.
Thermal information is provided as temperature reading by different clusters placed close to
the most dissipative junctions.
Some representative and realistic worst-case thermal profiles are described in the below
paragraph.
Following measurement methods can be easily implemented, by final user, for a specific
activation profile.
DS11546 Rev 5
23/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
L99DZ100G and L99DZ100GP thermal profiles
Profile 1
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 Ω resistor (DC activation)
OUT12: 300 Ω resistor (DC activation)
OUT13: 300 Ω resistor (DC activation)
OUT14: 300 Ω resistor (DC activation)
Cyclic activation
OUT4 – OUT5: 3,3 Ω resistor placed across those outputs
–
10 activations of Lock/Un-lock (250 ms ON Lock; 500 ms wait; 250 ms ON Unlock unlock; 500 ms wait)
OUT5 – OUT6: 10 Ω resistor placed across those outputs
–
(250 ms ON Safe Lock; 500 ms wait; 250 ms ON Safe unlock; 500 ms wait)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation”
sequence is applied.
Temperature reading is logged just at the end of the whole sequence.
Figure 3. Activation profile 1
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24/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 4. Activation profile 1 (first cycle)
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All curves are plotted interpolating measured samples with 15 ms of period.
Profile 2
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 Ω resistor (DC activation)
OUT12: 300 Ω resistor (DC activation)
OUT13: 300 Ω resistor (DC activation
OUT14: 300 Ω resistor (DC activation)
Cyclic activation
OUT1 – OUT6: 6,8 Ω resistor placed across those outputs
–
2 activations of Fold/Unfold. (3s ON; 1s OFF; 2x)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation”
sequence is applied.
DS11546 Rev 5
25/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Figure 5. Activation profile 2
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Figure 6. Activation profile 2 (first cycle)
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26/197
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DS11546 Rev 5
ͲϮ͘ϱ
("1($'5
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 7. LQFP64 package and PCB thermal configuration
Note:
Layout condition for Thermal Characterization (board finishing thickness 1.5 mm +/- 10%,
board four layers, board dimension 77 mm x 114 mm, board material FR4, Cu thickness
0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm.
3.4
Electrical characteristics
3.4.1
Supply and supply monitoring
All SPI communication, logic and oscillator parameter are working down to VSREG = 3.5 V
and parameter are as specified in the according chapters (guaranteed by design).
SPI thresholds
Oscillator frequency (delay times correctly elapsed)
Internal register status correctly kept (reset at default values for VSREG< VPOR)
Reset threshold correctly detected
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
DS11546 Rev 5
27/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 7. Supply and supply monitoring
Symbol
Parameter
VSUV
VS undervoltage threshold
Vhyst_UV
VS undervoltage hysteresis
VSOV
VS overvoltage threshold
Vhyst_OV
VS overvoltage hysteresis
VSREG_UV
VSREG undervoltage threshold
Vhyst_UV
VSREG undervoltage hysteresis
VSREG_OV
VSREG overvoltage threshold
Vhyst_OV
VSREG overvoltage hysteresis
tovuv_filt
VS/VSREG over/undervoltage filter
time
Test condition
VS increasing / decreasing
V
0.2
V
VS decreasing
18.5
22.5
0.5
VSREG increasing / decreasing
1
4.2
0.04
0.1
V
4.9
V
0.2
V
20
22.5
VSREG decreasing
18.5
22.5
0.5
1
1.5
64
Current consumption in
Vbat_standby mode with cyclic
sense enabled (1)
IV(BAT)CW
V
1.5
VSREG increasing
IV(BAT)CS
28/197
5.4
22.5
Current consumption in
Vbat_standby mode (1)
IV(SW)
Unit
20
VS = 12 V; Both voltage
regulators deactivated; HS/LS
Driver OFF; No CAN
communication; CAN automatic
voltage biasing enabled
IV(V1stby)
0.1
Max.
VS increasing
Current consumption in Active
mode
IV(BAT)
Typ.
4.7
0.04
VS = VSREG = 12 V;
TxD CAN = high;
TxD LIN = high; V1 = ON;
V2 = ON; HS/LS Driver OFF;
CP = ON
IV(act)
Min.
V
V
µs
11
15
mA
8
21
35
µA
VS = 12 V; Both voltage
regulators deactivated;
T = 50 ms, tON = 100 µs
40
100
143
µA
Current consumption in
Vbat_standby mode with cyclic
wake enabled (1)
VS = 12 V; Both voltage
regulators deactivated during
standby phase
40
100
143
µA
Current consumption in
V1_standby mode (1)
VS = 12 V; Voltage regulator V1
active; (IV1 = 0); HS/LS Driver
OFF
16
56
76
µA
Current consumption in
V1_standby mode (1) (2)
VS = 12 V; Voltage regulator V1
active; (IV1 = ICMP); HS/LS
Driver OFF
196
µA
Current consumption in
V1_standby mode (1)
VS = 12V; Voltage regulator V1
active; (IV1 = IPEAK); HS/LS
Driver OFF
436
µA
Current consumption adder in
standby mode if Selective
Wakeup enabled and CAN
communication on the bus
TRX_BIAS mode (1)
VS = 12 V
2000
µA
DS11546 Rev 5
1570
L99DZ100G, L99DZ100GP
Electrical specifications
Table 7. Supply and supply monitoring (continued)
Symbol
Parameter
IqCAN
Quiescent current adder for CAN
wake up activated
Guaranteed by design
0
µA
IqLIN
Quiescent current adder for LIN
wake up activated
Guaranteed by design
0
µA
IOUT_HS
Test condition
Min.
Additional bias quiescent current
for switched on OUT_HS or
Guaranteed by design
OUT15 by DIR or Timer; value for
1 output
Typ.
Max.
Unit
620
1100
µA
IOUTHS_DIR
Quiescent current adder if
OUT_HS and/or OUT15 are
configured for Direct Drive; value
during output off
Guaranteed by design
0
5
µA
Itimer
Quiescent current adder if timer1
and/or timer 2 are active to
provide interrupt on NINT upon
timer expiration
Guaranteed by design
65
110
µA
1. Conditions for specified current consumption:
— VLIN > (VS-1.5 V)
— (VCAN_H – VCAN_L) < 0.4 V or (VCAN_H – VCAN_L) > 1.2 V
— VWU < 1 V or VWU > (VS – 1.5 V)
2. Iq = Iq0 + 2% * ILOAD (see also Figure 8: Voltage regulator V1 characteristics (quiescent current and accuracy)
3.4.2
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 8. Oscillator
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
fCLK1(1)
Oscillation frequency OSC1
1.66
2.0
2.34
MHz
(1)
Oscillation frequency OSC2
30.4
32.0
33.6
MHz
Typ.
Max.
Unit
3.45
4.5
V
3.5
V
fCLK2
1. OSC1: charge pump, SPI, output drivers, watchdog
OSC2: ADC, CAN-PN
3.4.3
Power-on reset (VSREG)
All outputs open; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 9. Power-on reset (VSREG)
Symbol
VPOR_R
VPOR_F
Parameter
VPOR threshold
VPOR threshold
Test condition
Min.
VSREG rising
VSREG
falling(1)
2.45
1. This threshold is valid if VSREG had already reached VPOR_R(max) previously.
DS11546 Rev 5
29/197
196
Electrical specifications
3.4.4
L99DZ100G, L99DZ100GP
Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V ≤ VS ≤ 28 V; 4.5 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 10. Voltage regulator V1
Symbol
V1
VSREG_absmin
Parameter
Test condition
Output voltage
VSREG = 13.5V
VSREG absolute
minimum value for
controlling NRESET
output
VSREG rising/falling
Min.
Typ.
Max.
5.0
Unit
V
2
V
V1_low_acc
Output voltage
ILOAD = 0 mA to ICMP; (Active
tolerance Low accuracy mode) or ILOAD = 0 mA to IPEAK
(V1stdby); VSREG = 13.5 V
mode
-3
3
%
V1_hi_acc
ILOAD = ICMP to 100 mA; (Active
Output voltage
mode) or ILOAD = IPEAK to
tolerance High accuracy
100 mA (V1stdby);
mode
VSREG = 13.5 V
-2
2
%
V1_250mA
Output voltage
tolerance (100 to
250mA)
-3
3
%
VDP1
ICC1
ICCmax1
Cload1
tTSD
Drop-out Voltage
ILOAD = 250 mA;
VSREG = 13.5 V
ILOAD = 50 mA; VSREG = 5 V
0.2
0.4
V
ILOAD = 100 mA; VSREG = 5 V
0.3
0.5
V
ILOAD = 150 mA; VSREG = 5 V
0.45
0.6
V
250
mA
900
mA
Output current in Active
Max. continuous load current
mode
Short circuit output
current
Current limitation
Load capacitor1
Ceramic (+/- 20%)
340
600
0.22(1)
V1 deactivation time
after thermal shut-down
µF
1
sec
ICMP_ris
Current comp. rising
thresh
Rising current
2
4
6
mA
ICMP_fal
Current comp. falling
threshold
Falling current
1.4
2.8
4.2
mA
ICMP_hys
Current comp.
Hysteresis
1.2
mA
IPeak_ris(2)
Current comp. rising
thresh.
Rising current
6
12
18
mA
IPeak_fal(2)
Current comp. falling
threshold
Falling current
5
10
15
mA
IPeak_hys(2)
Current comp.
Hysteresis
30/197
2
DS11546 Rev 5
mA
L99DZ100G, L99DZ100GP
Electrical specifications
Table 10. Voltage regulator V1 (continued)
Symbol
Parameter
V1fail
V1 fail threshold
tV1fail
Test condition
Min.
Max.
Unit
2
V
V1 fail filter time
2
µs
V1 short filter time
4
ms
tV1FS
V1 Fail-Safe Filter Time
2
ms
tV1off
V1 deactivation time
after 8 consecutive WD
failures
tV1short
V1 forced
Typ.
Tested by scan
150
200
250
ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be
located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.
2. In Active mode, V1 regulator is switched to high accuracy mode, dropping below the ICMP threshold regulator switches to
low accuracy mode.
Figure 8. Voltage regulator V1 characteristics (quiescent current and accuracy)
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Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V ≤ VS ≤ 28 V; 4.5 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 11. Voltage regulator V2
Symbol
V2
V2_1mA
Parameter
Test condition
Output voltage
VSREG = 13.5 V
Output voltage tolerance
(0 to 1 mA)
ILOAD = 1 mA; VSREG = 13.5 V
DS11546 Rev 5
Min.
Typ.
Max.
5.0
-6.5
Unit
V
6.5
%
31/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 11. Voltage regulator V2 (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
V2_25mA
Output voltage tolerance
(1 to 25 mA)
ILOAD = 25 mA; VSREG = 13.5 V
-3
3
%
V2_50mA
Output voltage tolerance
(25 to 50 mA)
ILOAD = 50 mA; VSREG = 13.5 V
-4
4
%
V2_100mA
Output voltage tolerance
(50 to 100 mA)
ILOAD = 100 mA; VSREG = 13.5 V
-4
4
%
VDP2
Drop-out voltage
ILOAD = 25 mA; VSREG = 5.25 V
0.3
0.4
V
ILOAD = 50 mA; VSREG = 5.25 V
0.4
0.8
V
ILOAD = 100 mA; VSREG = 13.5 V
1
1.6
V
50
mA
250
mA
Output current in Active
mode
Max. continuous load current
Short circuit output
current
Current limitation
Cload
Load capacitor
Ceramic (+/- 20%)
V2fail
V2 fail threshold
V2 forced
tV2fail
ICC2
ICCmax2
tV2short
100
150
0.22 (1)
μF
2
V
V2 fail filter time
2
µs
V2 short filter time
4
ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be
located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.
3.4.6
Reset output
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4V ≤ VSREG ≤ 28V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 12. Reset output
32/197
Symbol
Parameter
VRT1falling
Reset threshold
voltage1
VRT2falling
Test condition
Min.
Typ.
Max.
Unit
VV1 decreasing
3.25
3.5
3.7
V
Reset threshold
voltage2
VV1 decreasing
3.55
3.8
4
V
VRT3falling
Reset threshold
voltage3
VV1 decreasing
3.75
4.0
4.2
V
VRT4falling
Reset threshold
voltage4
VV1 decreasing
4.1
4.3
4.5
V
VRTrising
Reset threshold
voltage4
VV1 increasing
4.67
4.8
4.87
V
VRESET
Reset Pin low output
V1 > 1 V; IRESET = 5 mA
voltage
0.2
0.4
V
RRESET
Reset pull up int.
resistor
20
30
kΩ
10
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Table 12. Reset output (continued)
Symbol
Parameter
Test condition
ILOAD = 1 mA
Min.
Typ.
6
Max.
Unit
40
µs
tRR
Reset reaction time
tUV1
V1 undervoltage
filter time
tV1R
Reset pulse duration
(V1 undervoltage
and V1 power on
reset)
1.5
2.0
2.5
ms
tWDR
Reset pulse duration
(watchdog failure)
3
4
5
ms
16
DS11546 Rev 5
µs
33/197
196
Electrical specifications
3.4.7
L99DZ100G, L99DZ100GP
Watchdog timing
4.5 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 13. Watchdog timing
Symbol
tLW
34/197
Parameter
Test condition
Long open window
Min.
Typ.
Max.
Unit
160
200
240
ms
4.5
ms
TEFW1
Early Failure Window 1
TLFW1
Late Failure Window 1
20
TSW1
Safe Window 1
7.5
TEFW2
Early Failure Window 2
TLFW2
Late Failure Window 2
100
TSW2
Safe Window 2
37.5
TEFW3
Early Failure Window 3
TLFW3
Late Failure Window 3
200
TSW3
Safe Window 3
75
TEFW4
Early Failure Window 4
TLFW4
Late Failure Window 4
400
TSW4
Safe Window 4
150
DS11546 Rev 5
ms
12
ms
22.3
ms
ms
60
ms
45
ms
ms
120
ms
90
ms
ms
240
ms
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 9. Watchdog timing
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DS11546 Rev 5
35/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Figure 10. Watchdog early, late and safe windows
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3.4.8
Current monitor output (CM)
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified
Table 14. Current monitor output (CM)
Symbol
VCM
Parameter
Test condition
Functional voltage range
36/197
ICM/IOUT8 (low on-resistance)
Typ.
0
Current monitor output ratio:
ICM/IOUT1,4,5,6 and 7 (low onresistance)
ICMr
Min.
1/10000
0 V ≤ VCM ≤ (V1 - 1 V)
1/6500
ICM/IOUT 2,3, 7,8 (high onresistance)
1/2000
ICM/IOUT9,10,11,12,13,14,15 and HS
1/1000
DS11546 Rev 5
Max.
Unit
V1-1V
V
L99DZ100G, L99DZ100GP
Electrical specifications
Table 14. Current monitor output (CM) (continued)
Symbol
ICM acc
Parameter
Current monitor accuracy
accICMOUT1,4,5,6 and 7(low onresistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 500 mA;
IOUT4,5max=7.4 A;
IOUT1,6max = 2.9 A;
IOUT7max = 1.4 A
Current monitor accuracy
accICMOUT 8 (low on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 100 mA;
IOUT8max=0.9 A
Current monitor accuracy
accICMOUT2,3, 9,10,11,12,13,14,15
,HS and OUT7,8 (high onresistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUT.min = 100 mA; IOUT11,12,
15 HS = 0.2 A; IOUT7,8
max = 0.3 A
Current monitor accuracy
accICMOUT1,4,5,6 and 7 (low onresistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 2 * IOLD;
IOUT4,5max = 7.4 A;
IOUT1,6max = 2.9 A;
IOUT7max = 1.4 A
Current monitor accuracy
accICMOUT 8(low on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 2 * IOLD;
IOUT8max = 0.9 A
Current monitor accuracy
accICMOUT2, 3, 9,11,12,13,14,15, HS
and OUT7,8 (high on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUT.min = 2 * IOLD;
IOUT2,3max = 0.4 A;
IOUT9,13,14max = 0.3 A;
IOUT11,12,15 HS = 0.2 A;
IOUT7,8 max = 0.3 A
Current monitor accuracy
accICMOUT10
0 V ≤ VCM ≤ (V1 - 1 V);
IOUT.min = 2 * IOLD;
IOUT10max = 0.4 A
ICM acc_2ol
tcmb
Test condition
Min.
Current monitor blanking time
Typ.
Max.
4% + 1%
FS(1)
8% + 2%
FS(1)
4% + 1%
FS(1)
8% + 2%
FS(1)
4% + 1%
FS(1)
8% + 4%
FS(1)
32
Unit
µs
1. FS (full scale) = IOUTmax * ICMr
3.4.9
Charge pump
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 15. Charge pump electrical characteristics
Symbol
Parameter
VCP
Charge pump output voltage
ICP
Charge pump output current(1)
Test condition
Min.
Typ.
VS = 6 V, ICP = -15 mA
VS+6
VS+7
VS ≥ 10 V, ICP = -15 mA
VS+11
VS+12
VCP = VS + 10 V;
VS = 13.5 V;
C1 = C2 = CCP = 100 nF
22.5
DS11546 Rev 5
Max.
Unit
V
VS+13.5
V
mA
37/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 15. Charge pump electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
VCP = VS;
VS = 13.5 V;
C1 = C2 = CCP = 100 nF
Max.
Unit
70
mA
VS+5.5
V
ICPlim
Charge pump output current
limitation(2)
VCP_low
Charge pump low threshold
voltage
TCP
Charge pump low filter time
64
µs
fCP
Charge Pump frequency
400
kHz
VS+4.5
VS+5
1. ICP is the minimum current the device can provide to an external circuit without VCP going below VS + 10 V.
2. ICPlim is the maximum current, which flows out of the device in case of a short to VS.
3.4.10
Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V, all outputs open;
Tj = -40 °C to 150 °C, unless otherwise specified.
Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR
Symbol
Parameter
rON OUT1,6
On-resistance to supply or
GND
rON OUT2,3
rON OUT4
rON OUT5
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply in
low resistance mode
rON OUT7
On-resistance to supply in
high resistance mode
38/197
Test condition
VS = 13.5 V; Tj = 25 °C;
IOUT1,6 = ±1.5A
Min.
Typ.
300
VS = 13.5V; Tj = 130°C
IOUT1,6 = ±1.5 A
VS = 13.5 V; Tj = 25 °C;
IOUT2,3 = ±0.25 A
2000
VS = 13.5 V; Tj = 25°C;
IOUT5 = ±3 A
150
VS = 13.5 V; Tj = 25 °C;
IOUT7 = -0.8 A
100
VS = 13.5 V; Tj = 25°C;
IOUT7 = -0.2 A
VS = 13.5 V; Tj = 130 °C;
IOUT7 = -0.2 A
DS11546 Rev 5
mΩ
mΩ
200
500
VS = 13.5 V; Tj = 130 °C;
IOUT7 = -0.8 A
mΩ
mΩ
300
VS = 13.5 V; Tj = 130 °C;
IOUT5 = 3 A
mΩ
mΩ
4000
VS = 13.5 V; Tj = 130 °C;
IOUT4 = ±3 A
Unit
mΩ
600
VS = 13.5 V; Tj = 130 °C;
IOUT2,3 = ±0.25 A
VS = 13.5V; Tj = 25 °C;
IOUT4 = ±3 A
Max.
mΩ
mΩ
1000
1600
mΩ
mΩ
3200
mΩ
L99DZ100G, L99DZ100GP
Electrical specifications
Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR (continued)
Symbol
Parameter
On-resistance to supply in
low resistance mode
rON OUT8
On-resistance to supply in
high resistance mode
rON OUT9,10,13,14
On-resistance to supply
rON OUT11,12,15, HS On-resistance to supply
rON ECV
On-resistance to GND
Test condition
VS = 13.5 V; Tj = 25 °C;
IOUT8 = -0.4 A
Typ.
Max.
800
VS = 13.5 V; Tj = 130 °C;
IOUT8 = -0.4 A
1600
VS = 13.5 V; Tj = 130 °C;
IOUT8 = -0.2 A
2000
VS = 13.5 V; Tj = 130 °C;
IOUT9,10,13,14 = -75 mA
5
VS = 13.5 V; Tj = 130 °C;
IOUT11,12,15, HS = -75 mA
mΩ
mΩ
4000
VS = 13.5 V; Tj = 25 °C;
IOUT11,12,15, HS = -75 mA
mΩ
mΩ
3200
VS = 13.5 V; Tj = 25 °C;
IOUT9,10,13,14 = -75 mA
Unit
mΩ
1600
VS = 13.5 V; Tj = 25 °C;
IOUT8 = -0.2 A
mΩ
Ω
10
Ω
VS = 13.5 V; Tj = 25 °C;
IOUTECV,ECFD = +0.4 A
1600
2200
mΩ
VS = 13.5 V; Tj = 130 °C;
IOUTECV,ECFD = +0.4 A
2500
3400
mΩ
IQLH
Switched-off output current VOUT = 0 V; standby mode
high-side drivers of OUT7VOUT = 0 V; active mode
15, OUT_HS
IQLH
Switched-off output current VOUT = 0 V; standby mode
high-side drivers of OUT1-6 V
OUT = 0 V; Active mode
VOUT = VS; standby mode
Switched-off output current
low-side drivers of OUT1-6 VOUT = VS - 0.5 V; active
mode
IQLL
Min.
VOUT = VS - 2.5 V with
Switched-off output current ECDR = VS; standby mode
low-side driver of ECV
VOUT = VS - 2.5 V with
ECDR = VS; active mode
DS11546 Rev 5
-5
µA
-10
µA
-5
µA
-100
µA
165
-100
-15
-10
µA
µA
15
µA
µA
39/197
196
Electrical specifications
3.4.11
L99DZ100G, L99DZ100GP
Power outputs switching times
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 17. Power outputs switching times
Symbol
td ON H
td OFF H
Parameter
Output delay time high-side driver
on (OUT1,2,3,4,5,6)
Output delay time high-side driver
on (OUT7,8)
Output delay time high-side driver
off (OUT1,4,5,6)
Output delay time high-side driver
off (OUT2,3, 7,8)
Test condition
VS = 13.5 V; V1 = 5 V;
corresponding low-side
driver is not active (1)(2)(3)
(from CSN 50% to OUT
50%) see Figure 18
VS = 13.5 V;
(1)(2)(3) (from
V1 = 5 V
CSN 50% to
OUT 50%) see Figure 18
Min.
Typ.
Max.
Unit
15
40
80
µs
20
40
90
µs
50
150
300
µs
20
70
130
µs
td ON H
Output delay time high-side driver
on (OUT9 …OUT15, OUT_HS)
VS/VSREG = 13.5 V;
V1 = 5 V; (from CSN 80% to
OUT 80%)
30
µs
td OFF H
Output switch off delay time highside driver on (OUT9 …OUT15,
OUT_HS)
VS/VSREG = 13.5 V;
V1 = 5 V; (from CSN 80% to
OUT 20%)
35
µs
Output delay time low-side driver
(OUT1-6, ECV) on
VS = 13.5 V; V1 = 5 V;
corresponding high-side
driver is not active (1)(2)(3)
(from CSN 50% to OUT
50%) see Figure 18
td ON L
td HL
td LH
30
70
µs
Output delay time low-side driver
(OUT1-6) off
V1 = 5 V
CSN 50% to
OUT 50%) see Figure 18
40
150
300
µs
Output delay time low-side driver
(ECV) off
VS = 13.5 V; V1 = 5 V
(1)(2)(3) (from CSN 50% to
OUT 50%) see Figure 18
15
45
110
µs
50
200
400
µs
0.1
0.2
0.6
V/µs
td OFF L
Cross current protection time
(OUT1-6)
VS = 13.5 V;
(1)(2)(3) (from
15
tcc ONLS_OFFHS – td OFF H(4)
tcc ONHS_OFFLS – td OFF L (4)
VS = 13.5 V; V1 = 5 V
dVOUT/dt
Slew rate of OUT1-OUT8, ECV
dVmax/dt
Maximum external applied slew
rate on OUT1-OUT6 without
Guaranteed by design
switching on the LS and HS (only in
Active mode)
dVOUT/dt
Slew rate of OUT9-OUT15,
OUT_HS
VS/VSREG = 13.5 V;
V1 = 5 V (1)(2)(3)
2
V/µs
fPWMx(00)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
100
Hz
40/197
(1)(2)(3)
DS11546 Rev 5
20
V/µs
L99DZ100G, L99DZ100GP
Electrical specifications
Table 17. Power outputs switching times (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
fPWMx(01)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
200
Hz
fPWMx(10)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
330
Hz
fPWMx(11)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
500
Hz
1. RLOAD = 16 Ω at OUT1,6 and OUT7,8 in low on-resistance mode
2. RLOAD = 4 Ω at OUT4,5
3. RLOAD = 128 Ω at OUT2,3,4,9,10,11,12,13,15,15,HS, ECV and OUT7,8 in high on-resistance mode
4. tCC is the switch-on delay time if complement in half bridge has to switch off
3.4.12
Current monitoring
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 18. Current monitoring
Symbol
Parameter
|IOC1|,
|IOC6|
Test condition
VS = 13.5 V; V1 = 5 V; sink
and source
|IOC2|,
|IOC3|
Min.
Typ.
Max.
Unit
3
5
A
0.5
1.0
A
7.5
10
A
6
10
A
VS = 13.5 V; V1 = 5 V; sink
and source; Tj = -40 °C to
|IOC4|
Overcurrent threshold HS & LS
70 °C
VS = 13.5 V; V1 = 5 V; sink
and source; Tj = 130 °C
|IOC5_1|
|IOC5_2|
VS = 13.5 V; V1 = 5 V; sink
and source
|IOC5_3|
3
4
5
A
4.5
6
7.5
A
10
A
7.5
DS11546 Rev 5
41/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 18. Current monitoring (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Overcurrent threshold HS in low onresistance mode
1.5
2.5
A
Overcurrent threshold HS in high
on-resistance mode
0.35
0.65
A
Overcurrent threshold HS in low onresistance mode
0.7
1.3
A
Overcurrent threshold HS in high
on-resistance mode
0.35
0.65
A
0.35
0.7
A
0.15
0.3
A
Overcurrent threshold HS in high
current mode
0.5
1
A
Overcurrent threshold HS in low
current mode
0.25
0.5
A
|IOC11|,
|IOC12|,
|IOC15|,
|IOC_HS|
Overcurrent threshold HS in high
current mode
0.25
0.5
A
Overcurrent threshold HS in low
current mode
0.15
0.3
A
|IOCECV|
output current threshold LS
VS = 13.5 V; V1= 5 V; sink
0.5
1.0
A
tFOC
Filter time of overcurrent signal
Duration of overcurrent
condition to set the status
bit
10
100
µs
frec0
Recovery frequency for OC;
OCR_FREQ (CR 7) = 0
1
4
kHz
frec1
Recovery frequency for OC;
OCR_FREQ (CR 7) = 1
2
6
kHz
tAR
Auto recovery time limit
|IOC7|
|IOC8|
|IOC9|,
|IOC13|,
|IOC14|
|IOC10|
Overcurrent threshold HS in high
current mode
Overcurrent threshold to HS in low
current mode
VS/VSREG = 13.5 V;
V1 = 5 V; source
OUT1 to OUT6
100
ms
OUT7, OUT8, OUT_HS
120
ms
|IOLD1|,
|IOLD6|
|IOLD2|,
|IOLD3|
Under-current threshold HS & LS
VS = 13.5 V; V1 = 5 V; sink
and source
|IOLD4|,
|IOLD5|
42/197
55
DS11546 Rev 5
6
30
80
mA
6
20
30
mA
40
150
300
mA
L99DZ100G, L99DZ100GP
Electrical specifications
Table 18. Current monitoring (continued)
Symbol
|IOLD7|
|IOLD8|
IOLD9|,
|IOLD13|,
|IOLD14|
|IOLD10|
Parameter
Test condition
Min.
Typ.
Max.
Unit
Under-current threshold HS in low
on-resistance mode
15
40
60
mA
Under-current threshold HS in high
on-resistance mode
5
10
15
mA
Under-current threshold HS in low
on-resistance mode
10
30
45
mA
Under-current threshold HS in high
on-resistance mode
5
10
15
mA
6
12
mA
0.5
4
mA
Under -current threshold HS in high
current mode
10
30
mA
Under -current threshold HS in low
current mode
0.3
4
mA
Under-current threshold HS in high
current mode
Under-current threshold HS in low
current mode
VS/VSREG = 13.5 V;
V1 = 5 V; source
|IOLD11|,
|IOLD12|,
|IOLD15|,
|IOLD_HS|
Under -current threshold HS in high
current mode
6
12
mA
Under -current threshold HS in low
current mode
0.85
4
mA
|IOLDECV|
Under-current threshold LS
VS = 13.5 V; V1 = 5 V; sink
6
20
30
mA
Filter time of open-load signal
Duration of open-load
condition to set the status
bit
150
200
250
µs
tOL_out
3.4.13
Heater
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 19. Heater
Symbol
Parameter
IGHheater
Average charge-current
(charge stage)
RGLheater
On-resistance (dischargestage)
VGHheater
Test condition
Min.
Tj = 25 °C
VSLx = 0 V; IGHx = 50 mA;
Tj = 25 °C
4
VS = SH= 6 V; ICP = 15 mA
VSHheater +
6
VS = SH = 12 V; ICP = 15 mA
VSHeahter +
8
DS11546 Rev 5
Max.
0.3
VSLx = 0 V; IGHx = 50 mA;
Tj = 130 °C
Gate-on voltage
Typ.
Unit
A
8
10
Ω
11
14
Ω
V
VSHeater VSHeater
+ 10
+ 11.5
V
43/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 19. Heater (continued)
Symbol
Parameter
Test condition
RGSHeater
Passive gate-clamp
resistance
TG(HL)xHL
Propagation delay time
high to low (switch mode)
Min.
Typ.
Max.
Unit
15
kΩ
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
1.5
µs
TG(HL)xLH
Propagation delay time low VS = 13.5 V; VSLx = 0;
to high (switch mode)
RG = 0 Ω; CG = 2.7 nF
1.5
µs
t0GHheaterr
Rise time (switch mode)
VS = 13.5 V; VSheater = 0;
RG = 0 Ω; CG = 2.7 nF
45
ns
t0GHheaterf
Fall time (switch mode)
VS = 13.5 V; VSheater = 0;
RG = 0 Ω; CG = 2.7 nF
85
ns
3.4.14
H-bridge driver
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40°C to 150 °C, unless
otherwise specified.
Table 20. H-bridge driver
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Drivers for external high-side PowerMOS
IGHx(Ch)
RGHx
Average charge current
(charge stage)
Tj = 25 °C
On-resistance (dischargestage)
VGHHx
Gate-on voltage
RGSHx
Passive gate-clamp
resistance
VSHx = 0 V; IGHx = 50 mA;
Tj = 25 °C
0.3
6
VSHx = 0 V; IGHx = 50 mA;
Tj = 130 °C
VS = SH = 6 V; ICP = 15 mA
VSHx + 6
VS = SH = 12 V; ICP = 15 mA
VSHx + 8
VGHx = 0.5 V
A
10
14
Ω
14
20
Ω
V
VSHx + 10 VSHx + 11.5
V
15
kΩ
0.3
A
Drivers for external low-side Power-MOS
IGLx(Ch)
RGLx
Average charge-current
(charge stage)
On-resistance (dischargestage)
VGHLx
Gate-on voltage
RGSLx
Passive gate-clamp
resistance
44/197
Tj = 25 °C
VSLx = 0 V; IGHx = 50 mA;
Tj = 25 °C
6
VSLx = 0 V; IGHx = 50 mA;
Tj = 130 °C
VS = 6 V; ICP = 15 mA
VSLx + 6
VS = 12 V; ICP = 15 mA
VSLx + 8
10
14
Ω
14
20
Ω
V
VSLx + 10 VSLx + 11.5
15
DS11546 Rev 5
V
kΩ
L99DZ100G, L99DZ100GP
3.4.15
Electrical specifications
Gate drivers for the external Power-MOS switching times
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 21. Gate drivers for the external Power-MOS switching times
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
TG(HL)xHL
Propagation delay time high to low
(switch mode(1)
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
1.5
µs
TG(HL)xLH
Propagation delay time low to high
(switch mode)(1)
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF
1.5
µs
IGHxrmax
Maximum source current (current
mode)
VS = 13.5 V; VSHx = 0;
VGHx = 1 V;
SLEW = 1 FH
32
mA
IGHxfmax
Maximum sink current (current
mode)
VS = 13.5 V, VSHx = 0;
VGHx = 2 V;
SLEW = 1 FH
32
mA
dIIGHxr
Source current accuracy
VS = 13.5 V; VSHx = 0;
VGHx = 1 V
See Figure 12: IGHxr
ranges
dIIGHxf
Sink current accuracy
VS = 13.5 V; VSHx = 0;
VGHx = 2 V
See Figure 13: IGHxf
ranges
Switching voltage (VS-VSH)
VDSHxrSW between current mode and switch
mode (rising)
VS = 13.5 V
2.8
V
Switching voltage (VS-VSH)
VDSHxfSW between switch mode and current
mode (falling)
VS = 13.5 V
2.8
V
t0GHxr
Rise time (switch mode)
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
45
ns
t0GHxf
Fall time (switch mode)
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
85
ns
t0GLxr
Rise time
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF
45
ns
t0GLxf
Fall time
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF
85
ns
tccp0001
Programmable cross-current
protection time
500
ns
tccp0010
Programmable cross-current
protection time
750
ns
tccp0011
Programmable cross-current
protection time
1000
ns
tccp0100
Programmable cross-current
protection time
1250
ns
tccp0101
Programmable cross-current
protection time
1500
ns
DS11546 Rev 5
45/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 21. Gate drivers for the external Power-MOS switching times (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tccp0110
Programmable cross-current
protection time
1750
ns
tccp0111
Programmable cross-current
protection time
2000
ns
tccp1000
Programmable cross-current
protection time
2250
ns
tccp1001
Programmable cross-current
protection time
2500
ns
tccp1010
Programmable cross-current
protection time
2750
ns
tccp1011
Programmable cross-current
protection time
3000
ns
tccp1100
Programmable cross-current
protection time
3250
ns
tccp1101
Programmable cross-current
protection time
3500
ns
tccp1110
Programmable cross-current
protection time
3750
ns
tccp1111
Programmable cross-current
protection time
4000
ns
fPWMH
PWMH switching frequency(1)
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF;
PWMH-Duty-Cycle = 50%
1. Without cross-current protection time tCCP.
46/197
DS11546 Rev 5
50
kHz
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 11. H-driver delay times
7* +/ [/+
7* +/ [+/
9 &613:0+',5
W
9&613:0+',5
W
9 *6 +/ [
W
*$3*&)7
Figure 12. IGHxr ranges
,*+[U DFFXUDF\
,*+[U0D[
,*+[U7\S
,*+[U0LQ
'DWDLQSXW
("1($'5
DS11546 Rev 5
47/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Figure 13. IGHxf ranges
,*+[I DFFXUDF\
,*+[I0D[
,*+[I7\S
,*+[I0LQ
'DWDLQSXW
3.4.16
("1($'5
Drain source monitoring external H-bridge
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40°C to 150 °C, unless
otherwise specified.
Table 22. Drain source monitoring external H-bridge
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSCd1_HB
Drain-source threshold voltage
0.375
0,5
0.625
V
VSCd2_HB
Drain-source threshold voltage
0.6
0,75
0.9
V
VSCd3_HB
Drain-source threshold voltage
0,85
1
1,15
V
VSCd4_HB
Drain-source threshold voltage
1,06
1,25
1,43
V
VSCd5_HB
Drain-source threshold voltage
1,27
1,5
1,73
V
VSCd6_HB
Drain-source threshold voltage
1,49
1,75
2,01
V
VSCd7_HB
Drain-source threshold voltage
1,7
2
2,3
V
tSCd_HB
Drain-source monitor filter time
tscs_HB
Drain-source comparator settling
time
48/197
6
VS = 13.5 V;
VSH = jump from GND to VS
DS11546 Rev 5
µs
5
µs
L99DZ100G, L99DZ100GP
3.4.17
Electrical specifications
Drain source monitoring external heater MOSFET
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 23. Drain source monitoring external heater MOSFET
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSCd1_HE
Drain-source threshold voltage
160
200
250
mV
VSCd2_HE
Drain-source threshold voltage
200
250
305
mV
VSCd3_HE
Drain-source threshold voltage
240
300
360
mV
VSCd4_HE
Drain-source threshold voltage
280
350
420
mV
VSCd5_HE
Drain-source threshold voltage
320
400
480
mV
VSCd6_HE
Drain-source threshold voltage
360
450
540
mV
VSCd7_HE
Drain-source threshold voltage
400
500
600
mV
VSCd8_HE
Drain-source threshold voltage
440
550
660
mV
tSCd_HE
Drain-source monitor filter time
tscs_HE
Drain-source comparator settling
time
tscbl_HE
Drain-source monitoring blanking
time
3.4.18
6
VS = 13.5 V; VSH = jump
from GND to VS
µs
5
8
µs
µs
Open-load monitoring external H-bridge
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 24. Open-load monitoring external H-bridge
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VODSL
Low-side drain-source monitor low
off-threshold voltage
VSLx = 0 V; VS = 13.5 V
0.15 VS
V
VODSH
Low-side drain-source monitor high
off-threshold voltage
VSLx = 0 V; VS = 13.5 V
0.85 VS
V
VOLSHx
Output voltage of selected SHx in
open-load test mode
VSLx = 0 V; VS = 13.5 V
0.5 VS
V
RpdOL
Pull-down resistance of the nonVSLx = 0 V; VS = 13.5 V;
selected SHx pin in open-load mode VSHX = 4.5 V
20
kΩ
tOL_HB
Open-load filter time
2
ms
DS11546 Rev 5
49/197
196
Electrical specifications
3.4.19
L99DZ100G, L99DZ100GP
Open-load monitoring external heater MOSFET
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 25. Open-load monitoring external heater MOSFET
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VOLheater
Open-load -threshold voltage
VSLx = 0 V; VS = 13.5 V
2
V
IOLheater
Pull-up current source open-load
diagnosis activated
VSLx = 0 V; VS = 13.5 V;
VSHheater = 4.5 V
1
mA
2
ms
tOL_HE
3.4.20
Open-load filter time
Electro-chrome mirror driver
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V ≤ VS ≤ 28V; 6V ≤ VSREG ≤ 28V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 26. Electro-chrome mirror driver
Symbol
Parameter
Test condition
ECV_HV (Config Reg) = 1
VCTRLmax
Maximum EC-control
voltage
(1)
ECV_HV (Config Reg) = 0
(1)
Min.
Typ.
Max.
Unit
1.4
1.6
V
1.12
1.28
V
-2
2
-5% 1LSB(2)
+5% +
1LSB(2)
LSB
DNLECV
Differential Non Linearity
IdVECVI
Voltage deviation between
target and ECV
dVECVnr
Difference voltage between
dVECV = Vtarget(3) - VECV;
target and ECV sets flag if
toggle bitx = 1; status reg. x
VECV is below it
120
mV
dVECVhi
Difference voltage between
dVECV = Vtarget(3) - VECV;
target and ECV sets flag if
toggle bitx = 1; status reg. x
VECV is above it
-180
mV
tFECVNR
ECVNR filter time
32
µs
tFECVHI
ECVHI filter time
32
µs
VECDRminHIGH
VECDRmaxLOW
50/197
Output voltage range
dVECV = Vtarget(3) - VECV;
IIECDRI < 1 µA
(2)
mV
IECDR = -10 µA
V1 0.3 V
V1
V
IECDR = 10 µA
0
0.7
V
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Table 26. Electro-chrome mirror driver (continued)
Symbol
Parameter
Test condition
Vtarget(3) >
IECDR
Recdrdis
Current into ECDR
Pull-down resistance at
ECDR in fast discharge
mode and while EC-mode
is off
Min.
Typ.
Max.
Unit
VECV + 500 mV;
VECDR = 3.5 V
-100
-10
µA
Vtarget(3) < VECV - 500 mV;
VECDR = 1.0 V; Vtarget = 0 V;
VECV = 0.5 V
10
100
µA
10
kΩ
VECDR = 0.7 V; ECON = ‘1’,
EC = 0 or ECON = ‘0’
1. Bit ECV_HV (Config Reg) ='1' or ‘0’: ECV voltage, where IIECDR can change sign.
2. 1 LSB (Least Significant Bit) = 23.8 mV typ
3. Vtarget is set by bits EC (CR 11) and bit ECV_HV (Config Reg); tested for each individual bit.
3.4.21
Fail safe low-side switch
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 18 V; Tj = 40 °C to 150 °C, unless otherwise specified.
Table 27. Fail safe low-side switch
Symbol
VOUT_max
Parameter
Max output voltage in
case of missing supply
RDSON
DC output resistance
IOLimit
Overcurrent limitation
tONHL
Test condition
Min.
IOUT = 1 mA; VS = VSREG = 0 V
ILOAD = 250 mA; Tj = 25 °C
Typ.
Max.
Unit
2
2.5
V
1.4
ILOAD = 250 mA; Tj = 130 °C
Ω
2.2
Ω
1500
mA
Turn on delay time to
10% VOUT
100
µs
tOFFLH
Turn off delay time to
90% VOUT
100
µs
tSCF
Short circuit filter time
dVmax/dt
8 V < VS < 16 V
500
64
Maximum external
applied slew rate on
Guaranteed by design
LS1_FSO and LS2_FSO
without switching on LS
DS11546 Rev 5
60
µs
V/µs
51/197
196
Electrical specifications
3.4.22
L99DZ100G, L99DZ100GP
Wake up input WU
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 28 V; Tj = 40 °C to 150 °C, unless otherwise specified.
Table 28. Wake-up inputs
Symbol
Parameter
VWUthn
Min.
Typ.
Max.
Unit
Wake-up negative
edge threshold voltage
0.4
VSREG
0.45
VSREG
0.5
VSREG
V
VWUthp
Wake-up positive edge
threshold voltage
0.5
VSREG
0.55
VSREG
0.6
VSREG
V
VHYST
Hysteresis
0.05
VSREG
0.1
VSREG
0.15
VSREG
V
tWU_stat
Static wake filter time
IWU_stdby
Input current in
standby mode
RWU_act
Input resistor to GND
in Active mode and in
Standby mode during
Wake-up input sensing
tWU_cyc
Cyclic wake filter time
3.4.23
Test condition
64
VWU < 1 V or
VWU > (VSREG – 1.5 V)
µs
5
30
60
μA
80
160
300
kΩ
16
µs
High speed CAN transceiver
ISO 11898-2:2003 and ISO 11898-5:2007 compliant.
SAE J2284 compliant.
Selective wake functionality according to ISO 11898-6:2013.
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
5.5 V ≤ VSREG ≤ 18 V; VCANSUP = V1; Tjunction = -40 °C to 150 °C, unless otherwise
specified. -12 V ≤ (VCANH + VCANL) / 2 ≤ 12 V
Table 29. CAN communication operating range
Symbol
Parameter
Test condition
VSREG_COM
Supply voltage operating
range for CAN
communication
VCANSUPlow
CAN supply low voltage flag VV1 = VCANSUP decreasing
VCANHL,CM
Common mode Bus voltage
52/197
VV1 = VCANSUP
Measured with respect to the
ground of each CAN node
DS11546 Rev 5
Min.
Typ.
5.5
4.5
-12
4.65
Max.
Unit
18
V
4.8
V
12
V
L99DZ100G, L99DZ100GP
Electrical specifications
Table 30. CAN transmit data input: pin TxDC
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTXDCLOW
Input voltage dominant
level
1.0
1.45
2.0
V
VTXDCHIGH
Input voltage recessive
level
1.2
1.85
2.3
V
VTXDCHYS
VTXDCHIGH-VTXDCLOW
0.2
0.4
0.7
V
RTXDCPU
TXDC pull up resistor
16
35
60
kΩ
TXDC - CANH,L delay
td,TXDC(dom-rec) time dominant recessive
RL = 60 Ω; CL = 100 pF; 70 %
VRXD – 30% VDIFF; TXDC rise
time = 10 ns (10% - 90%)(1)
0
120
ns
TXDC - CANH,L delay
time recessive dominant
RL = 60 Ω; CL = 100 pF; 30 %
VRXD – 70% VDIFF; TXDC fall
time = 10 ns (90% - 10%)(1)
0
120
ns
5
ms
td,TXDC(rec-diff)
tdom(TXDC)
TXDC dominant time-out
0.8
2
1. Guaranteed by design.
Table 31. CAN receive data output: Pin RxDC
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
0
0.2
0.5
V
V1
V
VRXDCLOW
Output voltage dominant level IRXDC = 2 mA
VRXDCHIGH
Output voltage recessive
level
IRXDC = -2 mA
tr,RXDC
RXDC rise time
CL = 15 pF;
30% - 70% VRXDC(1)
0
25
ns
tf,RXDC
RXDC fall time
CL = 15 pF;
70% - 30% VRXDC(1)
0
25
ns
td,RXDC(dom-rec)
CANH,L – RXDC delay time
dominant - recessive
CL = 15 pF;
30% VDIFF – 70% VRXDC(1)
0
120
ns
td,RXDC(rec - dom)
CANH,L – RXDC delay time
recessive - dominant
CL = 15 pF;
70% VDIFF – 30% VRXDC(1)
0
120
ns
V1 - 0.5 V1 - 0.2
1. Guaranteed by design.
Table 32. CAN transmitter dominant output characteristics
Symbol
Parameter
VCANHdom
Single ended CANH voltage
level in dominant state
VCANLdom
VDIFF,dom
Test condition
Min.
Typ.
VTXDC = VTXDCLOW; RL = 50 Ω;
65 Ω
2.75
3.5
4.5
V
Single ended CANL voltage
level in dominant state
VTXDC = VTXDCLOW;
RL = 50 Ω; 65 Ω
0.5
1.5
2.25
V
Differential output voltage in
dominant state: VCANHdomVCANLdom
VTXDC = VTXDCLOW;
RL = 50 Ω; 65 Ω
1.5
2.0
3
V
DS11546 Rev 5
Max. Unit
53/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 32. CAN transmitter dominant output characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
4.5
5
5.5
V
-100
-75
-45
mA
75
100
mA
Driver symmetry
VSYM = VCANHdom +
VCANLdom
Measured over one 250 kHz
period (4 µs) RL = 50 Ω; 65 Ω;
fTXDC = 250 kHz (square wave,
50% duty cycle); (1)
CSPLIT = 4.7 nF (+-5%)
IOCANH,dom (0V)
CANH output current in
dominant state
VTXDC = VTXDCLOW;
VCANH = 0 V
IOCANL,dom (5V)
CANL output current in
dominant state
VTXDC = VTXDCLOW; VCANL = 5 V
45
IOCANH,dom (40V)
CANH output current in
dominant state
VTXDC = VTXDCLOW;
VCANH = 40 V; RL = 65 Ω;
VS = 40 V
0
5
mA
IOCANL,dom (40V)
CANL output current in
dominant state
VTXDC = VTXDCLOW;
VCANL = 40 V;
RL = 65 Ω; VS = 40 V
0
100
mA
VSYM
1. Measurement equipment input load 1 MΩ.
Table 33. CAN transmitter recessive output characteristics, CAN normal mode
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCANHrec
CANH voltage level in
recessive state
TRX ready state;
VTXDC = VTXDCHIGH; No load
2
2.5
3
V
VCANLrec
CANL voltage level in
recessive state
TRX Ready state;
VTXDC = VTXDCHiGH; No load
2
2.5
3
V
50
mV
Differential output
TRX Ready state;
voltage in recessive state
VTXDC = VTXDCHIGH; No load
VCANHrec-VCANLrec
VDIFF,recOUT
Note:
-50
CAN normal mode: tested in TRX ready state while the device is in active mode.
Table 34. CAN transmitter recessive output characteristics, CAN low-power mode, biasing active
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCANHrecLPbias
CANH voltage level in
recessive state
TRX BIAS state;
VTXDC = VTXDCHIGH; No load
2
2.5
3
V
VCANLrecLPbias
CANL voltage level in
recessive state
TRX BIAS state;
VTXDC = VTXDCHiGH; No load
2
2.5
3
V
50
mV
Differential output voltage
TRX BIAS state;
VDIFF,recOUTLPbias in recessive state
VTXDC = VTXDCHIGH; No load
VCANHrec-VCANLrec
Note:
54/197
-50
CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active
mode, V1 Standby mode and Vbat_standby mode
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Table 35. CAN transmitter recessive output characteristics, CAN low-power mode, biasing
inactive
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCANHrecLP
CANH voltage level in
recessive state
TRX Sleep state;
VTXDC = VTXDCHIGH; No load
-0.1
0
0.1
V
VCANLrecLP
CANL voltage level in
recessive state
TRX Sleep state;
VTXDC = VTXDCHIGH; No load
-0.1
0
0.1
V
Differential output voltage
TRX Sleep state;
in recessive state
VTXDC = VTXDCHIGH; No load
VCANHrec -VCANLrec
-50
50
mV
VDIFF,recOUTLP
Note:
CAN Low Power mode, biasing inactive: tested in TRX sleep state while the device is in
active mode, V1 Standby mode and Vbat_standby mode.
Table 36. CAN receiver input characteristics during CAN normal mode
Symbol
Parameter
VTHdom
Differential receiver
threshold voltage recessive
to dominant state
VTHrec
Differential receiver
threshold voltage dominant
to recessive state
Test condition
Min.
Typ.
Max.
Unit
TRX ready state;
(VCANH + VCANL) / 2 = -12 V,
2.5 V, 12 V (1)
0.5
—
0.9
V
TRX Ready state;
(VCANH + VCANL) / 2 = -12 V,
2.5 V, 12 V (1)
0.5
—
0.9
V
1. Parameter evaluated with specific RL = 60 Ω; guaranteed by characterization.
Note:
CAN normal mode: tested in TRX ready state while the device is in active mode.
Table 37. CAN receiver input characteristics during CAN low power mode, biasing active
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTHdomLPbias
Differential receiver threshold TRX BIAS state;
voltage recessive to
(VCANH + VCANL) / 2 = -12 V,
2.5 V, 12 V(1)
dominant state
0.5
—
0.9
V
VTHrecLPbias
Differential receiver threshold TRX BIAS state;
voltage dominant to
(VCANH + VCANL) / 2 = -12 V,
2.5 V, 12 V(1)
recessive state
0.5
—
0.9
V
1. Parameter evaluated with specific RL = 60 Ω; guaranteed by characterization.
Note:
CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active
mode, V1 Standby mode and Vbat_standby mode.
DS11546 Rev 5
55/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 38. CAN Receiver input characteristics during CAN Low power mode, biasing inactive
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTHdomLP
Differential receiver
threshold voltage
recessive to dominant
state
TRX sleep state;
(VCANH + VCANL) / 2 = -12 V; 0 V; 12 V(1)
0.5
—
0.9
V
VTHrecLP
Differential receiver
threshold voltage
dominant to recessive
state
TRX Sleep state;
(VCANH + VCANL) / 2 = -12 V; 0 V; 12 V(1)
0.5
—
0.9
V
1. Parameter evaluated with specific RL = 60 Ω; guaranteed by characterization.
Note:
CAN Low Power mode, biasing inactive: Tested in TRX Sleep state while the device is in
active mode, V1 Standby mode and Vbat_standby mode.
Table 39. CAN receiver input resistance biasing active
Symbol
Parameter
Min.
Typ.
Max.
Unit
TRX Ready & TRX BIAS states;
VTXDC = VTXDCHIGH; no load
40
60
100
kΩ
RCANH, CANL
Single ended Internal TRX Ready & TRX BIAS states;
resistance
VTXDC = VTXDCHIGH; no load
20
30
50
kΩ
mR
TRX Ready & TRX BIAS states;
Internal Resistance
VTXDC = VTXDCHIGH; no load;
matching RCANH,CANL mR = 2 x (RCAN_H - RCAN_L) /
(RCAN_H + RCAN_L)
-0.03
Cin
Internal capacitance
Guaranteed by design
20
35
pF
Cin,diff
Differential internal
capacitance
Guaranteed by design
10
20
pF
Differential internal
resistance
Rdiff
Note:
Test condition
0.03
CAN Normal and Low Power mode, biasing active: Tested in TRX Ready and TRX BIAS
state while the device is in active and V1 Standby mode.
Table 40. CAN transceiver delay
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tTXpd,hl
Loop delay TXDC to
RXDC (High to Low)
RL = 60 Ω; CL = 100 pF;
30% VTXDC – 30% VRXDC;
TXDC fall time = 10 ns (90% - 10%);
CRXDC = 15 pF; fTXDC = 250 kHz
255
ns
tTXpd,lh
Loop delay TXDC to
RXDC (Low to High)
RL = 60Ω; CL = 100pF;
70% VTXD – 70% VRXD;
TXDC rise time = 10 ns (10% - 90%);
CRXDC = 15 pF; fTXDC = 250 kHz
255
ns
56/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Table 40. CAN transceiver delay (continued)
Symbol
Parameter
Recessive Bit
symmetry
TBitrec
Test condition
Min.
Typ.
Max.
Unit
RL = 60 Ω; CL = 100 pF;
70% VTXDC (rising) - 30% VRXDC
(falling); CRXD = 15 pF; 10 ns (10% 90%, 90% - 10%); Rectangular pulse
signal TTXDC = 6000 ns, high pulse
1000 ns, low pulse 5000 ns
765
1000
1255
ns
500
700
1000
μs
CAN permanent
dominant time-out
tCAN
tWUP-V1(1)
Time between WUP(2) Wake-Up according to ISO11898on the CAN bus until 5:2007 (Bit SWEN = 0);
V1 goes active
70% VDIFF – 90% V1(min)
0
200
µs
(1)
Time between WUF(3) Wake-Up according to ISO11898on the CAN bus until 6:2013 (Bit SWEN = 1);
V1 goes active
30% VDIFF – 90% V1(min)
0
200
µs
tWUF-V1
1. Guaranteed by characterization.
2. Time starts with the end of last dominant phase of the WUP.
3. Time starts with the end of CRC delimiter of the WUF.
Table 41. Maximum leakage currents on CAN_H and CAN_L, unpowered
Symbol
Parameter
Test condition
Min.
Unpowered device; VCANH = 5 V;
VCANL = 5 V; VSREG, VCANSUP connected
via
0 Ω to GND; VSREG, VCANSUP
Input leakage current
ILeakage, CANH
connected via 47 kΩ to GND(1)
CANH
Tj = -40 °C to 105 °C(2)
Tj = 130 °C(3)
Unpowered device; VCANH = 5 V;
VCANL = 5 V; VSREG, VCANSUP connected
Input leakage current via 0 Ω to GND; VSREG, VCANSUP connected
ILeakage, CANL
via 47 kΩ to GND(1)
CANL
Tj = -40 °C to 105 °C(2)
Tj = 130 °C(3)
Typ.
Max.
Unit
μA
-10
-12
10
12
-10
-12
10
12
μA
1. Guaranteed by design.
2. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified
ambient temperature range
3. Used for device test only.
Table 42. Biasing control timings
Symbol
Parameter
Test condition
Min.
tfilter
CAN activity filter time
0.5
twake
Wake-up time out
0.5
DS11546 Rev 5
Typ.
1
Max.
Unit
5
μs
5
ms
57/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 42. Biasing control timings (continued)
Symbol
tSilence
tBIAS
Parameter
Test condition
CAN timeout
RL = 50 Ω, 65 Ω; CL = 100 pF; CGND
(= CSPLIT) = 100 pF;
VTXDC = VTXDCLOW;
50% VDIFF - VCANH =
VCANL = VCAN(H,L)rec(min)(1);
Transition TRX Sleep to TRX BIAS in
Active, V1-Standby and Vbat_standby
modes
Bias reaction time
Min.
Typ.
Max.
Unit
600
700
1200
ms
200
µs
0
1. A wake-up-pattern is sent with a bit length of tfilter. TBIAS is measured from the rising edge after having released the bus at
the end of the 2nd dominant bit until CANH and CANL reach the minimum recessive output voltage (VCANHrec, VCANHrec).
3.4.24
LIN transceiver
LIN 2.2 compliant for bit-rates up to 20 kBit/s SAE J2602 compatible.
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V; Tjunction = -40 °C to 150°C unless otherwise
specified.
Table 43. LIN transmit data input: pin TxD
Symbol
Parameter
Test condition
Min.
VTXDLOW
Input voltage dominant level
Active mode
VTXDHIGH
Input voltage recessive level
Active mode
VTXDHYS
VTXDHIGH-VTXDLOW
Active mode
0.2
RTXDPU
TXD pull up resistor
Active mode
13
Typ.
Max.
1.0
Unit
V
2.3
V
V
29
46
kΩ
Typ.
Max.
Unit
0.2
0.5
V
Table 44. LIN receive data output: pin RxD
Symbol
Parameter
Test condition
VRXDLOW
Output voltage dominant level
Active mode
VRXDHIGH
Output voltage recessive level
Active mode
Min.
V1-0.5
V1-0.2
V
Table 45. LIN transmitter and receiver: pin LIN
Symbol
Parameter
VTHdom
Receiver threshold voltage
recessive to dominant state
VBusdom
Receiver dominant state
Test condition
Min.
Typ.
Max.
Unit
0.4
VSREG
0.45
VSREG
0.5
VSREG
V
0.4VSRE
G
VTHrec
Receiver threshold voltage
dominant to recessive state
0.5
VSREG
VBusrec
Receiver recessive state
0.6
VSREG
58/197
DS11546 Rev 5
0.55
VSREG
0.6
VSREG
V
V
V
L99DZ100G, L99DZ100GP
Electrical specifications
Table 45. LIN transmitter and receiver: pin LIN (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTHhys
Receiver threshold
hysteresis: VTHrec -VTHdom
0.07
VSREG
0.1
VSREG
0.175
VSREG
V
VTHcnt
Receiver tolerance center
value: (VTHrec +VTHdom)/2
0.475
VSREG
0.5
VSREG
0.525
VSREG
V
VTHwkup
Activation threshold for
wake-up comparator
1.0
1.5
2
V
VTHwkdwn
Activation threshold for
wake-up comparator
VSREG 3.5
VSREG 2.5
VSREG1.5
V
tLINBUS
LIN Bus Wake-up Dominant
Sleep mode; edge: rec-dom
Filter time
tdom_LIN
LIN Bus Wake-up Dominant Sleep mode; edge: rec-domFilter time
rec
28
Transmitter input current
limit in dominant state
40
ILINDomSC
VTXD = VTXDLOW;
VLIN = VBATMAX = 18 V
Ibus_PAS_dom
Input leakage current at the VTXD = VTXDHIGH; VLIN = 0 V;
receiver incl. pull-up resistor VBAT = 12 V; Slave mode
Ibus_PAS_rec
Transmitter input current in
recessive state
In standby modes;
VTXD = VTXDHIGH; VLIN > 8 V;
VBAT < 18 V; VLIN ≥ VBAT
Ibus_NO_GND
Input current if loss of GND
at device
GND = VSREG;
0 V < VLIN < 18 V;
VBAT = 12 V
Ibus
Input current if loss of VBAT
at device
μs
μs
100
180
mA
-1
mA
20
μA
1
mA
GND = VS; 0 V < VLIN < 18 V
Tj=-40 °C ....105 °C(1)
30
μA
GND = VS; 0 V < VLIN < 18 V
Tj = 130°C(2)
35
μA
1.2
V
VLINdom
LIN voltage level in
dominant state
Active mode;
VTXD = VTXDLOW
RBus=500 Ohm
VLINrec
LIN voltage level in
recessive state
Active mode;
VTXD = VTXDHIGH;
ILIN = 10 µA
RLINup
LIN output pull up resistor
VLIN = 0 V
CLIN
64
LIN input capacitance
-1
0.8*VS
20
V
40
60
kΩ
30
pF
1. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified
ambient temperature range.
2. Used for device test only.
DS11546 Rev 5
59/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 28V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 46. LIN transceiver timing
Symbol
tRXpd
tRXpd_sym
D1
D2
D3
D4
Parameter
Test condition
Min.
Receiver propagation
delay time
tRXpd = max(tRXpdr, tRXpdf);
tRXpdf = t(0.5 VRXD)-t(0.45 VLIN);
tRXpdr = t(0.5 VRXD)-t(0.55 VLIN);
VSREG = 12 V; CRXD=20 pF;
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Symmetry of receiver
propagation delay time
(rising vs. falling edge)
tRXpd_sym = tRXpdr - tRXpdf; VSRE = 12 V;
Rbus = 1 kΩ; Cbus = 1 nF; CRXD = 20 pF
-2
Duty Cycle 1
THRec(max) = 0.744 * VSREG;
THDom(max) = 0.581 * VSREG;
VSREG = 7 to 18 V, tbit = 50 µs;
D1 = tbus_rec(min) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
0.396
Duty Cycle 2
THRec(min) = 0.422* VSREG;
THDom(min) = 0.284* VSREG;
VSREG = 7.6 to 18 V, tbit = 50 µs;
D2 = tbus_rec(max) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Duty Cycle 3
THRec(max) = 0.778* VSREG;
THDom(max) = 0.616* VSREG; VSREG = 7
to 18 V, tbit = 96 µs;
D3 = tbus_rec(min) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Duty Cycle 4
THRec(min) = 0.389* VSREG;
THDom(min) = 0.251* VSREG;
VSREG = 7.6 to 18 V, tbit = 96 µs;
D4 = tbus_rec(max) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Typ.
Max.
Unit
6
μs
2
μs
0.581
0.417
0.590
TXDL dominant timeout
12
ms
tLIN
LIN permanent
recessive time-out
40
μs
tdom(bus)
LIN Bus permanent
dominant time-out
12
ms
tdom(TXDL)
60/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 14. LIN transmit, receive timing
W 7;SGI
W 7;SGU
9 7['
WLPH
9 /,1UHF
9 7+UHF
9 /,1
9 7+GRP
9 /,1GRP
WLPH
9 5['
WLPH
W 5;SGI
W 5;SGU
*$3*&)7
3.4.25
SPI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VSREG < 18 V; V1 = 5 V; all outputs open; Tj = -40 °C to 150 °C,
unless otherwise specified.
Table 47. Input: CSN
Symbol
Parameter
Test condition
Min.
Typ.
VCSNLOW
Input voltage low level
Normal mode
VCSNHIGH
Input voltage high level
Normal mode
VCSNHYS
VCSNHIGH - VCSNLOW
Normal mode
0.2
ICSNPU
CSN Pull up resistor
Normal mode
13
29
Min.
Typ.
Max.
1.0
Unit
V
2.3
V
V
46
kΩ
Max.
Unit
Table 48. Inputs: CLK, DI
Symbol
tset
Parameter
Test condition
Delay time from standby Time until SPI, ADC and
to Active mode
OUT15/OUT_HS are operative
10
Delay time from standby Time until power stages that are
to Active mode
supplied by the CP are operative
560
Vin_L
Input low level
1.0
Vin_H
Input high level
tset_CP
Pull down current at
input
960
0.2
Vin = 1.5 V
DS11546 Rev 5
5
µs
V
2.3
Vin_Hyst Input hysteresis
Ipdin
750
µs
V
V
30
60
µA
61/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Table 48. Inputs: CLK, DI (continued)
Symbol
Parameter
Test condition
Cin(1)
Input capacitance at
input CSN, CLK, DI and
PWM1,2
fCLK
SPI input frequency at
CLK
Min.
Typ.
Guaranteed by design
Max.
Unit
15
pF
4
MHz
Max.
Unit
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 49. DI, CLK and CSN timing
Symbol
Note:
Parameter
Test condition
Min.
Typ.
tCLK
Clock period
250
ns
tCLKH
Clock high time
100
ns
tCLKL
Clock low time
100
ns
tset_CSN
CSN setup time, CSN low
before rising edge of CLK
150
ns
tset_CLK
CLK setup time, CLK high
before rising edge of CSN
150
ns
tset_DI
DI setup time
25
ns
thold_DI
DI hold time
25
ns
tr_in
Rise time of input signal DI,
CLK, CSN
25
ns
tf_in
Fall time of input signal DI,
CLK, CSN
25
ns
Max.
Unit
0.5
V
See Figure 16: SPI input timing.
Table 50. Output: DO
Symbol
Parameter
Test condition
VDOL
Output low level
IDO = -4 mA
VDOH
Output high level
IDO = 4 mA
IDOLK
3-state leakage
current
VCSN = V1, 0 V < VDO < V1
CDO
3-state input
capacitance
Guaranteed by design
Min.
Typ.
V1 - 0.5
V
-10
10
μA
10
15
pF
Typ.
Max.
Unit
Table 51. DO timing
Symbol
62/197
Parameter
Test condition
Min.
tr DO
DO rise time
CL = 50 pF; ILOAD = -1 mA
25
ns
tf DO
DO fall time
CL = 50 pF; ILOAD = -1 mA
25
ns
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Table 51. DO timing (continued)
Symbol
Test condition
Min.
Typ.
Max.
Unit
ten DO tri L
DO enable time from
3-state to low level
CL = 50 pF; ILOAD = -1 mA;
pull-up load to V1
50
100
ns
tdis DO L tri
DO disable time from
low level to 3-state
CL = 50 pF; ILOAD = -1 mA;
pull-up load to V1
50
100
ns
ten DO tri H
DO enable time from
3-state to high level
CL = 50 pF; ILOAD = -1 mA;
pull-down load to GND
50
100
ns
tdis DO H tri
DO disable time from
high level to 3-state
CL = 50 pF; ILOAD = -1 mA;
pull-down load to GND
50
100
ns
DO delay time
VDO < 0.3 V1;
VDO > 0.7 V1; CL = 50 pF
30
60
ns
Typ.
Max.
Unit
td DO
Note:
Parameter
See Figure 17: SPI output timing.
Table 52. CSN timing
Symbol
Parameter
tCSN_HI,min
Minimum CSN
High time, active
mode
tCSNfail
CSN low timeout
Test condition
Transfer of SPI-command to
Input Register
Min.
6
μs
20
Note:
See Figure 18: SPI CSN - output timing.
3.4.26
Inputs TxD_C and TxD_L for Flash mode
35
50
ms
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V ≤ VSREG ≤ 18; V1 = 5 V; Tj = -40 °C to 150 °C.
Table 53. Inputs: TxD_C and TxD_L for Flash mode
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
VflashL
Input low level (VTXDC/L for
exit from Flash mode)
6.1
7.25
8.4
V
VflashH
Input high level (VTXDC/L for
transition into Flash mode)
7.4
8.4
9.4
V
Input voltage hysteresis
0.6
0.8
1.0
V
VflashHYS
DS11546 Rev 5
63/197
196
Electrical specifications
3.4.27
L99DZ100G, L99DZ100GP
Inputs DIRH, PWMH
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V; Tj = -40 °C to 150 °C.
Table 54. Inputs DIRH, PWMH
Symbol
Test condition
Min.
VIL
Input voltage low level
VSREG = 13.5 V
VIH
Input voltage high level
VSREG = 13.5 V
Input hysteresis
VSREG = 13.5 V
0.2
Input pull-down current
VSREG = 13.5 V
5
VIHYS
Iin
3.4.28
Parameter
Typ.
Max.
1
Unit
V
2.3
V
V
30
60
µA
Debug input
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V; Tj = -40 °C to 150 °C.
Table 55. Debug input
Symbol
Test condition
Min.
VdIL
Input voltage low level
VSREG = 13.5 V
VdIH
Input voltage high level
VSREG = 13.5 V
Input hysteresis
VSREG = 13.5 V
0.2
Pull-down resistor
VDEBUG = 6 to 18 V
2.5
VdIHYS
Rdin
3.4.29
Parameter
Typ.
Max.
1
Unit
V
2.3
V
V
5
7.5
kΩ
ADC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V, Tj = -40 °C to 150 °C.
Table 56. ADC characteristics
Symbol
Test condition
tcon
Conversion time
fADC
Clock frequency (see
fclk2)
Acc
64/197
Parameter
Accuracy
Min.
Typ.
Max.
2.5
µs
8
MHz
Voltage divider + reference(1)
-2
2
Overall accuracy for WU
input: VS = 22 V
-3
3
Overall accuracy for WU
input: VS = 18 V
-3.5
3.5
Overall accuracy for WU
input: VS = 6 V
-4
4
Overall accuracy for WU
input: VS = 4.5 V
-4.6
4.6
DS11546 Rev 5
Unit
%
L99DZ100G, L99DZ100GP
Electrical specifications
Table 56. ADC characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
IEII
Integral linearity error
4
LSB
IEDI
Differential linearity
error
2
LSB
VAINVS
Conversion voltage
range (VS, VSREG &
WU)
1
22
V
VAINTemp
Conversion voltage
range (TCL1 …TCL6)
0
2
V
1. Guaranteed by design.
3.4.30
Temperature diode characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V, Tj = -40 °C to 150 °C
Table 57. Temperature diode characteristics
Symbol
3.4.31
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTROOM 1-6
TSENSE output
voltage at 25 °C
VS = 12 V; T = 25 °C
—
1.4
V
VTSENSE1-6
TSENSE output
voltage 1 - 8
T = 25 °C; T = 130 °C;
T = -40 °C
—
-4
mV/K
Interrupt outputs
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V, Tj = -40 °C to 150°C
Table 58. Interrupt outputs
Symbol
Parameter
Test condition
VINTL
Output low level
IINT = -4 mA
VINTH
Output high level
IINT = 4 mA
IINTLK
3-state leakage current
0 V < VINT < V1
tInterrupt
Interrupt pulse duration
(NINT, RxD_L/NINT,
RxD_C/NINT
tInt_react
Interrupt reaction time
Min.
Typ.
Max.
Unit
0.5
V
V1 - 0.5
V
-10
10
s
56
Tested by scan chain
DS11546 Rev 5
6
μA
40
µs
65/197
196
Electrical specifications
3.4.32
L99DZ100G, L99DZ100GP
Timer1 and Timer2
6 V ≤ VSREG ≤ 18 V; Tj = -40 °C to 150 °C
Table 59. Timer1 and Timer2
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
ton 1
Timer on time
0.1
ms
ton 2
Timer on time
0.3
ms
ton 3
Timer on time
1
ms
ton 4
Timer on time
10
ms
ton 5
Timer on time
20
ms
T1
Timer period
10
ms
T2
Timer period
20
ms
T3
Timer period
50
ms
T4
Timer period
100
ms
T5
Timer period
200
ms
T6
Timer period
500
ms
T7
Timer period
1000
ms
T8
Timer period
2000
ms
Figure 15. SPI – transfer timing diagram
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The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
66/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 16. SPI input timing
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DS11546 Rev 5
67/197
196
Electrical specifications
L99DZ100G, L99DZ100GP
Figure 17. SPI output timing
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68/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Electrical specifications
Figure 18. SPI CSN - output timing
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Figure 19. SPI – CSN high to low transition and global status bit access
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3.4.33
SGND loss comparator
Tj = -40 °C to 150 °C, unless otherwise specified.
Table 60. SGND loss comparator
Symbol
Parameter
Test condition
VSGNDloss VSGND loss threshold (VSGND – VPGND )
tSGNDloss
VSGND loss filter time
DS11546 Rev 5
Min.
Typ.
Max.
Unit
100
270
500
mV
5
7
9
µs
69/197
196
Application information
L99DZ100G, L99DZ100GP
4
Application information
4.1
Supply VS, VSREG
VSREG supplies voltage regulators V1 and V2, all internal regulated voltages for analog and
digital functionality, LIN, CAN, the EC control block and both P-channel high-side switches
OUT15 and OUT_HS.
All other high-sides, Fail Safe block and the charge pump are supplied by VS.
In case the VSREG pin is disconnected, all power outputs connected to VS are automatically
switched off.
4.2
Voltage regulators
The device contains two independent and fully protected low drop voltage regulators
designed for very fast transient response and do not require electrolytic output capacitors
for stability.
The output voltage is stable with ceramic load capacitors >220 nF.
4.2.1
Voltage regulator: V1
The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load
current to supply the system microcontroller and the integrated CAN transceiver. The V1
regulator is embedded in the power management and fail-safe functionality of the device
and operates according to the selected operating mode. The V1 voltage regulator is
supplied by pin VSREG.
In addition, the V1 regulator supplies the devices internal loads. The voltage regulator is
protected against overload and overtemperature. An external reverse current protection has
to be provided by the application circuitry to prevent the input capacitor from being
discharged by negative transients or low input voltage. Current limitation of the regulator
ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic
load capacitors >220 nF.
In case the device temperature exceeds the TSD1 threshold (either cluster or grouped
mode) the V1 regulator remains on. The micro controller has the possibility for interaction or
error logging. If the chip temperature exceeds the TSD2 threshold (TSD2 > TSD1), V1 will
be deactivated and all wakeup sources (CAN, LIN, WU and Timer) are disabled. After tTSD,
the voltage regulator will restart automatically. If the restart fails 7 times within one minute
the devices enter the Forced Vbat_standby mode. The status bit
FORCED_SLEEP_TSD2/V1SC (SR1) is set.
70/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.2.2
Application information
Voltage regulator: V2
The voltage regulator V2 is supplied by pin VSREG and can supply additional 5 V loads such
as sensors or potentiometers. The maximum continuous load current is 50 mA. The
regulator is protected against:
4.2.3
Overload
Overtemperature
Short-circuit (short to ground and battery supply voltage)
Reverse biasing
Voltage regulator failure
The V1, and V2 regulator output voltages are monitored.
In case of a drop below the failure thresholds (V1 < V1fail for t > tV1fail, V2 < V2fail for
t > tV2fail), the failure bits V1FAIL, V2FAIL (SR 2) are latched.
4.2.4
Short to ground detection
At turn-on of the V1 and V2 regulators, a short-to-GND condition is detected by monitoring
the regulator output voltage.
If V1 or V2 is below the V1fail (or V2fail) threshold for t > tV1short (t > tV2short) after turn-on, the
devices will identify a short circuit condition at the related regulator will be switched off.
In case of V1 short-to-GND the device enters Forced Vbat_standby mode automatically. Bits
FORCED_SLEEP_TSD2/V1SC and (SR 1) V1FAIL (SR 2) are set.
In case of a V2 short-to-GND failure the V2SC (SR 2) and V2FAIL (SR 2) bits are set.
Once the output voltage of the corresponding regulator exceeded the V1fail (V2fail) threshold
the short-to-ground detection is disabled. In case of a short-to-ground condition, the
regulator is switched off due to thermal shutdown. V1 is switched off at TSD2, V2 is
switched off at TSD1.
DS11546 Rev 5
71/197
196
Application information
4.2.5
L99DZ100G, L99DZ100GP
Voltage regulator behavior
Figure 20. Voltage regulator behaviour and diagnosis during supply voltage
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4.3
Operating modes
The devices can be operated in the following operating modes:
4.3.1
Active
LIN Flash
CAN Flash
V1_standby
VBAT_standby
Debug
Active mode
All functions are available and the device is controlled by SPI.
72/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.3.2
Application information
Flash modes
To program the system microcontroller via LIN or HS CAN bus signals, the devices can be
operated in LIN Flash mode or CAN Flash mode. The watchdog is disabled in these modes.
The Flash modes are entered by applying an external voltage at the respective pin:
VTxDL ≥ VFlashH (CAN Flash mode)
VTxDC ≥ VFlashH (LIN Flash mode)
In CAN Flash mode the CAN transceiver is set in TRX bias mode
(CAN_GO_TO_TRX_RDY = 1) and TRX Normal mode automatically
During CAN Flash mode, the watchdog can be deactivated by setting CR34: WDEN = 0.
Write access to this bit is only possible during CAN Flash mode in order to prevent
accidental deactivation of the watchdog. After setting WDEN (CR 34) the CAN Flash mode
can be left (VTxDL < VFlashL) and the Watchdog will remain deactivated (see Figure 21)
Figure 21. Sequence to disable/enable the watchdog in CAN Flash mode
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In LIN Flash mode the maximum bitrate is increased to 100 kbit/s automatically
(LIN_HS_EN = 1).
A transition from Flash modes to V1_standby or Vbat_standby mode is not possible.
At exit from Flash modes (VTxDL < VFlashL, VTxDC < VFlashL) no NReset pulse is generated.
The watchdog starts with a Long Open Window (tLW).
Note:
Setting both TxDL and TxDC to high voltage levels (> VFlashH) is not allowed.
Communication at the respective TxD pin is not possible.
4.3.3
SW-debug mode
To allow software debugging, the watchdog can be deactivated by applying an external
voltage to the DEBUG input pin (Vdebug > VdiH).
In Debug mode, all device functionality and Operating modes are available. The watchdog
is deactivated. At Exit from Debug mode (Vdebug < VdiL) the watchdog starts with a Long
Open Window.
Note:
The device includes a test mode. This mode is activated by a dedicated sequence which
includes a high voltage at the Debug Pin. The Debug Pin must be kept at nominal voltage
levels in order to avoid accidental activation of the test mode.
DS11546 Rev 5
73/197
196
Application information
4.3.4
L99DZ100G, L99DZ100GP
V1_standby mode
The transition from Active mode to V1_standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the V1 voltage regulator remains active.
After the V1_standby command (CSN low to high transition), the device enters V1_standby
mode immediately and the watchdog starts a Long Open Window (tLW). The watchdog is
deactivated as soon as the V1 load current drops below the ICMP threshold (IV1< Icmp_fal).
The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration
the watchdog will be deactivated upon transition into V1_standby mode without monitoring
the V1 load current.
Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting
ICMP_CONFIG_EN (Config Reg) = 1.
The ICMP_CONFIG_EN bit is reset to 0 automatically with the next SPI command.
Power outputs (except OUT_HS & OUT15) are switched off in V1_standby mode. OUT_HS
& OUT15 remain in the configuration programmed prior to the standby command in order to
enable (cyclic) supply of external contacts. The timer signal (Timer1 or Timer2) can be
mirrored to the NINT output pin during V1_standby mode.
CAN and LIN transmitters (TxDL, TxDC) are off.
Wake-up capability by CAN and LIN can be disabled by SPI. The CAN transceiver can be
configured in Listen mode (TxDC disabled, RxDC enabled) in order to support pretended
networking concepts (for details see Section 4.10.6: Pretended networking)
4.3.5
Interrupt
Figure 22. NINT pins
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RxDL/NINT indicates:
a wake-up event from V1_standby mode (except wake-up by CAN) and the
programmable timer interrupt
RxDL/NINT pin is pulled low for t = tinterrupt.
74/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
RxDC/NINT indicates:
Mode transitions of the CAN transceiver according to Figure 31: CAN transceiver state
diagram
CAN communication timeout (no CAN communication for t > tSilence). The CANTO flag
is set. This interrupt can be masked by SPI (CR2: CANTO_IRQ_EN).
RxDC/NINT pin is pulled low for t = tinterrupt.
See also Section 4.3.6: CAN wake-up signalization
NINT indicates:
In Active mode:
VSREG dropped below the programmed early warning threshold in Control Register 3
(VSREG < VSREG_EW_TH); feature is deactivated if VSREG_EW_TH is set to 0 V.
In V1_standby mode
–
Programmable timer interrupt; An NINT pulse is generated at the beginning of the
timer on-time (Timer 1 or Timer2)
–
CAN communication timeout (no CAN communication for t > tSilence). The CANTO
flag is set. This interrupt can be masked by SPI (CR2: CANTO_IRQ_EN).
–
Wake-up from V1_standby mode by any wake-up source
NINT is pulled low for t = tinterrupt
In case of increasing V1 load current during V1_standby mode (IV1 > Icmp_ris), the device
remains in standby mode and the watchdog starts with a Long Open Window. No Interrupt
signal is generated.
4.3.6
CAN wake-up signalization
Table 61. CAN wake-up signalization
Operating
mode
Active
V1_standby
Vbat_standby
Event
Mode transition
Status flag
Interrupt pin
WUP or
WUP/WUF(1)
Transition to TRX_Ready
WAKE_CAN
WUP/WUF(1)
RxDC
CAN Timeout
Transition to TRX_Sleep
CANTO
RxDC (2)
WUP(3)
Transition into TRX_Bias
WUP
RxDC and NINT
WUP or
WUP/WUF(1)
Transition into Active
mode; TRX_Ready
WAKE_CAN
WUP/WUF(1)
RxDC and NINT
CAN Timeout
Transition to TRX_Sleep
CANTO
RxDC and NINT (2)
WUP(3)
Transition into TRX_Bias
WUP
RXDC and NINT
WUP or
WUP/WUF(1)
Transition into Active
mode; TRX_Ready
WAKE_CAN
WUP/WUF(1)
none
CAN Timeout
Transition to TRX_Sleep
CANTO
1. SW_EN = 0, PNW_EN = 0:
— wake-up according ISO 11898-5:2007 (on WUP)
— Flags: Wake_CAN, WUP
SW_EN = 1:
— wake-up according ISO 11898-6:2013 (on WUP/WUF combination)
— After the reception of a wake-up pattern (WUP) the CAN Enhanced Voltage Biasing is turned on until a CAN timeout is
detected
— Flags: Wake_CAN, WUP, WUF
DS11546 Rev 5
75/197
196
Application information
L99DZ100G, L99DZ100GP
2. Interrupt can be disabled by SPI (CANTO_IRQ_EN).
3. SW_EN = 0, PWN_EN = 1 (Pretended Networking mode)
— no wake-up
— after reception of a wake-up patter (WUP) the transceiver enters TRX Bias mode
— Flags: WUP
Note:
See also Figure 31: CAN transceiver state diagram.
4.3.7
VBAT_standby mode
The transition from Active mode to Vbat_standby mode is initiated by an SPI command. In
Vbat_standby mode, the voltage regulators V1 and V2 (depending on configuration in
CR 1), the power outputs (except OUT15 and OUT_HS) as well as LIN and CAN
transmitters are switched off.
An NReset pulse is generated upon wake-up from Vbat_standby mode. At transition into
Vbat_standby mode with selective wake-up enabled (SWEN = 1), the CAN transceiver is
automatically set to TRX_standby configuration (RXEN = 0).
4.4
Wake-up from Standby modes
A wake-up from standby mode will switch the device to Active mode. This can be initiated by
one or more of the following events:
Table 62. Wake-up events description
Wake up source
Description
LIN bus activity
Can be disabled by SPI
CAN bus activity
Can be disabled by SPI
Selective Wake-up can be enabled and configured by SPI
Level change of WU
IV1 >Icmp_ris
Can be configured or disabled by SPI
Device remains in V1_standby mode but watchdog is enabled (If
ICMP = 0). No interrupt is generated.
Programmable by SPI:
– V1_standby mode: configurable timer interrupt. NINT and RxDL/NINT
Timer Interrupt / Wake up
interrupt signals are generated
of µC by TIMER
– Vbat_standby mode: device wakes up after programmable timer
expiration, V1 regulator is turned on and NReset signal is generated
SPI Access
Always active (except in VBAT_STANDBY mode)
Wake up event: CSN is low and first rising edge on CLK
To prevent the system from a deadlock condition (no wake up from standby possible) a
configuration where the wake up by LIN and HS CAN are both disabled is not allowed. All
wake-up sources are configured to default values in case of such invalid setting. The SPI
Error Bit SPIE (Global Status Byte) is set.
76/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.4.1
Application information
Wake up input
The WU input can be configured as wake-up source. The wake-up input is sensitive to any
level transition (positive and negative edge) and can be configured for static or cyclic
monitoring of the input voltage level.
For static contact monitoring, a filter time of tWU_STAT is implemented. The filter is started
when the input voltage passes the specified threshold VWU_THP or VWU_THN.
Cyclic contact monitoring allows periodical activation of the wake-up input to read the status
of the external contact. The periodical activation can be configured to Timer 1 or Timer 2.
The input signal is filtered with a filter time of tWU_CYC after a delay (80% of the configured
Timer on-time. A Wake-up will be processed if the status has changed versus the previous
cycle. The buffered output OUT_HS can be used to supply the external contacts with the
timer setting according to the cyclic monitoring of the wake-up input.
In standby modes, the input WU is configurable with an internal pull-up or pull-down current
source according to the setup of the external contact. In Active mode the inputs have an
internal pull down resistor (RWU_act) and the input status can be read by SPI. Static sense
should be configured before the read operation is started in order to reflect the actual input
level.
4.5
Functional overview (truth table)
Table 63. Status of different functions/features vs operating modes
Operating modes
Function
Voltage regulator V1
Voltage regulator V2
Comments
VOUT = 5 V
VOUT = 5 V
Reset generator
Window watchdog
LIN
V1-standby static
mode (cyclic sense)
On
On(1)
On/
Off(2)
On(2)
/ Off
Vbat-standby static
mode (cyclic sense)
Off
On(2)
/ Off
On
On
Off
On
Off (on if IV1 > ICMP
and ICMP = 0)
Off
Off
Active(3)
Active(3)
Oscillator time
base
On / Off
On(2) / Off
On(2) / Off
LIN 2.2a
On
Off(4)
Off(4)
On / Off(5)
Off(4)
Off(4)
V1 monitor
Wake up
HS-cyclic supply
Active mode
HS_CAN
Oscillator OSC1
2 MHz
On
On/Off(6)
On/Off(6)
Oscillator OSC2
32 MHz
ON
ON/Off(7)
ON/Off(7)
VSREG-Monitor
On
(8)
(8)
VS-Monitor
On
Off
Off
DS11546 Rev 5
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196
Application information
L99DZ100G, L99DZ100GP
Table 63. Status of different functions/features vs operating modes (continued)
Operating modes
Function
Comments
Active mode
V1-standby static
mode (cyclic sense)
Vbat-standby static
mode (cyclic sense)
H Bridge Gate Driver, EC
control, bridge drivers, heater
driver, all high-side drivers
(except OUT_HS & OUT15)
supplied by VS
On/ Off(2)
Off
Off
Fail-safe low-side switches
On/ Off(9)
On
On
On
On
On
On/ Off(2)
On/ Off (2)
On/ Off(2)
Charge pump
On
Off
Off
ADC (SPI read out and
VSREG early warning
interrupt)
On
Off
Off
Thermal shutdown TSD2
On
On
Off
Thermal shutdown TSD1x for
OUT_HS and OUT15 (Pchannel HS)
On
On/ Off(2)
On/ Off(2)
Short circuit protection for
fail-safe low-side switches (in
case LS is switched on)
OUT_HS & OUT15 (Pchannel HS) supplied by
VSREG
1. Supply the processor in low current mode.
2. According to SPI setting and DIR.
3. Unless disabled by SPI.
4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding
of internal filter time (if wake-up by LIN or CAN is not disabled by SPI). Selective Wake functionality if enabled by SPI
5. After power-on, the HS CAN transceiver is in CAN_TRX_SLEEP mode. It is activated by SPI command
(CAN_GO_TRX_RDY= 1)
6. ON, if cyclic sense is enabled or during wake-up request.
7. ON if SWEN=1 (CAN partial networking enabled) and ongoing CAN communication on the bus.
8. Cyclic activation = pulsed ON during cyclic sense.
9. ON in Fail-Safe mode; if standby mode is entered with active Fail-safe mode the output remains ON in standby mode.
78/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Figure 23. Main operating modes
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4.6
Configurable window watchdog
During normal operation, the watchdog monitors the micro controller within a programmable
trigger cycle.
After power-on or standby mode, the watchdog is started with a timeout (Long Open
Window tLW). The timeout allows the micro controller to run its own setup and then to start
the window watchdog by setting TRIG (CR1,ConfigReg) =1
Subsequently, the micro controller has to serve the watchdog by alternating the watchdog
trigger bit TRIG (CR1,Config Reg) within the safe trigger area TSWX.
The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately
start the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off
for tV1OFF. After 7 additional watchdog failures the V1 regulator is turned off permanently
and the device goes into Forced Vbat_standby mode. The status bit FORCED_SLEEP_WD
(SR 1) is set. A wake-up is possible by any activated wake-up source.
After wake-up from Forced Vbat_standby mode and the watchdog trigger still fails, the
device enters Forced Vbat_standby mode again after one Long Open Window.
DS11546 Rev 5
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196
Application information
L99DZ100G, L99DZ100GP
This actually produces an additional watchdog failure but the watchdog fail counter will
remain at maximum value of 15 failures.
This sequence is repeated until a valid watchdog trigger event is performed by writing
TRIG = 1.
In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit
WDFAIL (SR 1) is set to 1. A reset pulse is generated at NReset output and the device
enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe
low-side switches are turned on. Please refer to chapter Section 4.7: Fail-safe mode for
more details.
The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are
split into 3 parts. First diagram shows the functional behavior of the watchdog without any
error. The second diagram covers the behavior covering all the error conditions, which can
affect the watchdog behavior. Figure 26: Watchdog in Flash mode shows the transition in
and out of Flash modes. Figure 24, Figure 25 and Figure 26 can be overlapped to get all the
possible state transitions under all circumstances. For a better readability, they were split in
normal operating, operating with errors and Flash mode.
Figure 24. Watchdog in normal operating mode (no errors)
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80/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Figure 25. Watchdog with error conditions
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Figure 26. Watchdog in Flash mode
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Note:
Whenever the device is operated without servicing the mandatory watchdog trigger events,
a sequence of 15 consecutive reset events is performed and the device enters the
Forced_Vbat_Stby mode with bit FORCED_SLEEP_WD in SR1 set.
If the device is woken up after such a forced VBAT_Standby condition and the watchdog is
still not serviced, the device, after one long open watchdog window will re-enter the same
Forced_Vbat_Stby mode until the next wake up event. In this case, an additional watchdog
failure is generated, but the fail counter is not cleared, keeping the maximum number of 15
failures. This sequence is repeated until a valid watchdog trigger event is performed by
writing TRIG = 1.
DS11546 Rev 5
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196
Application information
4.6.1
L99DZ100G, L99DZ100GP
Change watchdog timing
The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits
is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config
Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command.
4.7
Fail-safe mode
4.7.1
Temporary failures
The devices enter Fail-safe mode in case of:
Watchdog failure
V1 turn on failure
V1 failure (V1 < VRTxfalling for t > tV1FS)
Thermal Shutdown TSD2
–
V1 short (V1 < V1fail for t > tV1short)
The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode
the Fail Safe mode is entered in the following cases:
V1 failure (V1 < VRTxfalling for t > tV1FS)
Watchdog failure (if watchdog still running due to IV1 > Icmp_fal)
Thermal Shutdown TSD2
In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated
to the system in the Global Status Byte. The conditions during Fail Safe mode are:
All outputs beside LS1_FSO and LS2_FSO are turned off
All Control Registers are set to fail safe default values except:
82/197
–
SWEN (CR1): selective Wake-up enable
–
Partial Networking Configuration: CR23-CR29
Write operations to Control Registers are blocked until the Fail Safe condition is
cleared. The following bits are not WRITE protected:
–
TRIG (CR1, Config Register ): watchdog trigger bit
–
V2_x (CR1): Voltage Regulator V2 control
–
CAN_GO_TRX_RDY (CR1): activation of CAN transceiver
–
CR2 (bit ): Timer1 and Timer2 settings
–
OUT_HS_x (CR5 ): OUT_HS configuration
–
OUT15_x (CR6): OUT15 configuration
–
PWMx_freq_y (CR12): PWM frequency configuration
–
PWMx_DC_y (CR13 – CR17): PWM duty cycle configuration
LIN and HS CAN transmitter and SPI remain on (transmitters are deactivated in case of
thermal shutdown TSD1 (TSD1 cluster 5 or 6 in cluster mode)
Corresponding Failure Bits in Status Registers are set
FS Bit (Global Status Byte) is set
LS1_FSO and LS2_FSO will be turned on
Charge pump is switched off
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and
the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the
actions to exit Fail safe mode are as shown in the following table.
Table 64. Temporary failures description
Failure source
Failure condition
Microcontroller
(oscillator)
Watchdog early write
failure or expired
window
FS (Global Status Byte) =1;
WDFAIL (SR 1) =1;
WDFAIL_CNT_x (SR 1) = n+1
TRIG (CR 1) = 1 during long
open window Read&Clear
SR1
Short at turn-on
FS (Global Status Byte) =1;
FORCED_SLEEP_TSD2/V1SC
(SR 1) =1
Wake-up;
Read&Clear SR1
Undervoltage
FS (Global Status Byte) = 1; V1UV
(SR 1) = 1; V1fail (SR 2) = 1(1)
V1 >VRTrising;
Read&Clear SR1
Tj > TSD2
FS (Global Status Byte) = 1; TW
(SR 2) = 1;
TSD1 (SR 1) =1;
TSD2 (SR 1) =1
Tj < TSD2;
Read&Clear SR1
V1
Temperature
Diagnosis
Exit from Fail-safe mode
1. If V1 < V1fail (for t > tV1fail). The Fail-safe Bit is located in the Global Status Register.
4.7.2
Non-recoverable failures – forced Vbat_standby mode
If the Fail-safe condition persists and all attempts to return to normal system operation fail,
the devices enter the Forced Vbat_standby mode in order to prevent damage to the system.
The Forced Vbat_standby mode can be terminated by any wake-up source. The root cause
of the Forced Vbat_standby mode is indicated in the SPI Status Registers. In forced
Vbatstby mode and with Fail Safe conditions still present at wake-up, the Fails safe low side
outputs LSx_FSO are switched OFF for 25us after the wake up event.
In Forced Vbat_standby mode, all Control Registers are set to power-on default values
except:
SWEN (CR1)
All bits from CR23 to CR29
CP_DITH_DIS (Config. Reg )
The Forced Vbat_standby mode is entered in case of:
Multiple watchdog failures: FORCED_SLEEP_WD (SR 1) = 1 (15 x watchdog failure)
Multiple thermal shutdown 2: FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 (7 x TSD2)
V1 short at turn-on (V1 < V1fail for t > tV1short):
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
DS11546 Rev 5
83/197
196
Application information
L99DZ100G, L99DZ100GP
Table 65. Non-recoverable failure
Failure source
Failure condition
Temperature
4.8
Exit from Fail-safe mode
FS (Global Status Byte) = 1; WDFAIL (SR
1) = 1; FORCED_SLEEP_WD (SR 1) = 1
Wake-up;
TRIG (CR 1) = 1 during long
open window; Read&Clear
SR1
Short at turn-on
FS (Global Status Byte) = 1;
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Wake-up;
Read&Clear SR1
7 times TSD2
FS (Global Status Byte) =1; TW (SR 2) = 1;
Wake-up;
TSD1 (SR 1) = 1; TSD2 (SR 1) = 1;
Read&Clear SR1
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Microcontroller 15 consecutive
(Oscillator)
Watchdog Failures
V1
Diagnosis
Reset output (NReset)
Figure 27. NReset pin
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If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is
pulled up to V1 by an internal pull-up resistor after a reset delay time (tV1R). This is
necessary for a defined start of the micro controller when the application is switched on.
Since the NReset output is realized as an open drain output it is also possible to connect an
external NReset open drain NReset source to the output. As soon as the NReset is released
by the devices the watchdog starts with a long open window.
A reset pulse is generated in case of:
84/197
V1 drops below VRTxfalling (configurable by SPI) for t > tUV1
Watchdog failure
Turn-on of the V1 regulator (VSREG Power-on or wake-up from Vbat_standby mode)
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.9
Application information
LIN Bus Interface
Figure 28. RxDL pin
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4.9.1
Features
LIN 2.2a compliant (SAEJ2602 compatible) transceiver
LIN Cell has been designed according to “Hardware requirements for transceivers
(version 1.3)”
Bitrate up to 20 kbit/s
Dedicated LIN Flash mode with bitrate up to 100 kbit/s
GND disconnection fail safe at module level
Off mode: does not disturb network
GND shift operation at system level
Micro controller Interface with CMOS-compatible I/O pins
Internal pull-up resistor
Receive-only mode
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
Matched output slopes and propagation delay
Wake-up behaviour according to LIN2.2a and Hardware Requirements for LIN, CAN
and Flexray Interfaces (version 1.3)
At VSREG > VPOR (i.e. VSREG power-on reset threshold), the LIN transceiver is enabled. The
LIN transmitter is disabled in case of the following errors:
Dominant TxDL time out
LIN permanent recessive
Thermal shutdown 1
VSREG overvoltage/ undervoltage
The LIN receiver is not disabled in case of any failure condition.
The default bitrate of the transceiver allows communication up to 20 kbit/s. To enable fast
flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit
LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode.
DS11546 Rev 5
85/197
196
Application information
4.9.2
L99DZ100G, L99DZ100GP
Error handling
The devices LIN transceiver provides the following 3 error handling features.
Dominant TxDL time out
If TXD_L is in dominant state (low) for t > tdom(TXDL) the transmitter will be disabled, the
status bit LIN_TXD_DOM (SR 2) will be set.
The transmitter remains disabled until the status bit is cleared.
The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0).
Permanent recessive
If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < tLIN
the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set.
The transmitter remains disabled until the status bit is cleared.
Permanent dominant
If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure will be
detected. The status bit LIN_PERM_DOM (SR 2) will be set.
The transmitter will not be disabled.
4.9.3
Wake up from Standby modes
In low power modes (V1_standby mode and Vbat_standby mode) the devices can receive
two types of wake up signals from the LIN bus (configurable by SPI bit LIN_WU_CONFIG
(Config Reg)):
Recessive-Dominant-recessive pattern with t > tdom_LIN (default, according LIN 2.2a)
State Change recessive-to-dominant or dominant-to-recessive (according LIN 2.1)
Pattern Wake-up (default)
Figure 29. Wake-up behavior according to LIN 2.2a
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86/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Status change wake-up - Recessive-to-dominant
Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN
was in recessive (high) state. A dominant level at LIN for t > tLINBUS, will switch the devices
to Active mode.
Status change wake-up - Dominant-to-recessive
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for t > tLINBUS, will switch the devices to Active mode.
4.9.4
Receive-only mode
The LIN transmitter can be disabled in Active mode by setting the bit LIN_REC_ONLY
(CR2). In this mode it is possible to listen to the bus but not sending to it.
4.10
High-speed CAN bus transceiver
Figure 30. RxDC pin
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DS11546 Rev 5
87/197
196
Application information
4.10.1
88/197
L99DZ100G, L99DZ100GP
Features:
ISO 11898-2:2003 and ISO 11898-5:2007 compliant
ISO 11898-6: 2013 compliant (Selective wake-up functionality up to 500kbps); only
L99DZ100GP
HS-CAN cell has been designed according to “Requirements for partial networking
(version 2.2)” and “Hardware requirements for transceivers (version 1.3)”
Supports pretended networking
Listen mode (transmitter disabled)
Enhanced Voltage Biasing according to ISO 11898-6:2013
SAE J2284 compliant
Bitrate up to 1Mbit/s.
Function range from -27V to +40V DC at CAN pins.
GND disconnection fail safe at module level.
GND shift operation at system level.
Micro controller Interface with CMOS compatible I/O pins.
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
Matched output slopes and propagation delay
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.10.2
Application information
CAN transceiver operating modes
Figure 31. CAN transceiver state diagram
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Recovery of outputs after overvoltage condition is configurable by SPI:
94/197
–
VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2).
–
VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS overvoltage
condition has recovered.
The overvoltage bit VS_OV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and
the overvoltage condition has recovered.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
VS undervoltage
If the supply voltage VS drops below the under voltage threshold voltage (VSUV):
LIN remains enabled
CAN remains enabled
OUT1 to OUT14 are turned off (default).
The shutdown of outputs may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0)
Heater MOSFET gate driver switched into sink condition
ECV is switched in high impedance state and ECDR is discharged by RECDRDIS (to
ensure the gate of the external MOSFET is discharged => EC mode considered as off)
Recovery of outputs after undervoltage condition is configurable by SPI:
4.12.2
–
VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_UV (SR 2).
–
VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS undervoltage
condition has recovered.
The undervoltage bit VS_UV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The undervoltage bit is removed automatically if VS_LOCK_EN (CR 3) = 0
and the undervoltage condition has recovered.
VSREG supply failure
VSREG overvoltage
If the supply voltages VSREG reaches the overvoltage threshold VSREG_OV:
LIN is switched to high impedance
CAN remains enabled
OUT15 and OUT_HS are turned off (default).
The shutdown of outputs may be disabled by SPI (VSREG_OV_SD_EN (CR 3) = 0)
Recovery of outputs after overvoltage condition is configurable by SPI:
–
VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_OV
(SR 2).
–
VSREG_LOCK_EN (CR 3) = 0: outputs turned on automatically after VSREG
overvoltage condition has recovered.
The overvoltage bit VSREG_OV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The overvoltage bit is reset automatically if VSREG_LOCK_EN (CR 3) = 0
and the overvoltage condition has recovered.
DS11546 Rev 5
95/197
196
Application information
L99DZ100G, L99DZ100GP
VSREG undervoltage
If the supply voltage VSREG drops below the under voltage threshold voltage (VSREG_UV):
LIN is switched to high impedance
CAN remains enabled
OUT15 and OUT_HS are turned off (default).
The shutdown of outputs may be disabled by SPI (VSREG_UV_SD_EN (CR 3) = 0)
Recovery of outputs after undervoltage condition is configurable by SPI:
96/197
–
VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_UV
(SR 2).
–
VSREG_LOCK_EN (CR 3) = 0: Outputs turned on automatically after VSREG
undervoltage condition has recovered.
The undervoltage bit VSREG_UV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The undervoltage bit is removed automatically if
VSREG_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.13
Application information
Temperature warning and thermal shutdown
Figure 33. Thermal shutdown protection and diagnosis
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Note:
The Thermal State machine will recover the same state were it was before entering Standby
mode. In case of a TSD2 it will enter TSD1 state.
DS11546 Rev 5
97/197
196
Application information
4.14
L99DZ100G, L99DZ100GP
Power outputs OUT1..15 and OUT_HS
The component provides a total of 6 half bridges outputs OUT1..6 to drive motors and 10
stand alone high-side outputs OUT7..15 and OUT_HS to drive e.g. LED’s, bulbs or to supply
contacts. All high-side outputs beside OUT_HS and OUT15 are supplied by the pin VS and
OUT_HS and OUT15 are supplied by the buffered supply VSREG. OUT_HS is intended to be
used as contact supply. Beside OUT15 and OUT_HS the high-side switches can be
activated only in case of running charge pump. OUT15 and OUT_HS can be activated also
in standby modes.
All high-side and low-side outputs switch off in case of:
VS (VSREG) overvoltage and undervoltage (depending on configuration, see
Section 4.12.2: VSREG supply failure)
Overcurrent (depending on configuration, auto recovery mode (see below)
Overtemperature (TSD1x/ cluster or single mode)
Fail safe event
Loss of GND at SGND pin
In case of overcurrent or overtemperature (TSD1_CLx (SR 6)) condition, the drivers will
switch off. The according status bit will be latched and can be read and optionally cleared by
SPI. The drivers remain off until the status is cleared. In case overvoltage/ undervoltage
condition, the drivers will be switched off. The according status bit will be latched and can be
read and optionally cleared by SPI. If VSREG_LOCK_EN (CR 3) respectively
VS_LOCK_EN (CR 3) are set, the drivers remain off until the status is cleared. If the
VS_LOCK_EN or VSREG_LOCK_EN) bit is set to 0, the drivers will switch on automatically
if the error condition disappears. Undervoltage and overvoltage shutdown can be disabled
by SPI. In case of open-load condition, the according status register will be latched. The
status can be read and optionally cleared by SPI. The high and low-side outputs are not
switched off in case of open-load condition.
For OUT1..OUT8 and OUT_HS the auto recovery feature (OUTx_OCR (CR 7)) can be
enabled. If these bits are set to 1 the driver will automatically restart from an overload
condition. This overload recovery feature is intended for loads which have an initial current
higher than the overcurrent limit of the output (e.g. Inrush current of cold light bulbs). The
SPI bits OUTx_OCR_ALERT (SR4) indicate that the output reached auto-recovery
condition.
Note:
The maximum voltage and current applied to the High-side Outputs is specified in the
‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to
respect these limits under application conditions. In case of outputs switch off due to loss of
ground at SGND pin, the device has to be re-started through a power off on both VS and
VSREG.
Each of the stand alone high-side driver outputs OUT7 … OUT15 and OUT_HS can be
driven with an internally generated PWM signal, an internal Timer or with DIR1 respectively
DIR2. See table below.
98/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Table 66. Power output settings
OUTx_3 OUTx_2
4.15
OUTx_1
OUTx_0
Description
0
0
0
0
OFF
0
0
0
1
ON
0
0
1
0
Timer1 output is controlled by timer1; starting with ON
phase after timer restart
0
0
1
1
Timer2 output is controlled by timer2; starting with ON
phase after timer restart
0
1
0
0
PWM1
0
1
0
1
PWM2
0
1
1
0
PWM3
0
1
1
1
PWM4
1
0
0
0
PWM5
1
0
0
1
PWM6
1
0
1
0
PWM7
1
0
1
1
PWM8
1
1
0
0
PWM9
1
1
0
1
PWM10
1
1
1
0
DIR1
1
1
1
1
DIR2
Auto-recovery alert and thermal expiration
The thermal expiration feature provides a robust protection against possible microcontroller
malfunction, switching off a given channel if continuously driven in auto-recovery. If the
temperature of the related cluster increases by more than 30 °C after reaching the autorecovery time tAR, the channel is switched off. The thermal expiration status bit
OUTx_TH_EX (SR 3) is set.
During auto-recovery condition, OUTx_OCR_ALERT (SR 4) is set. The Alert bit indicates
that an overload condition (load in-rush, short-circuit, etc) is present.
The thermal expiration feature is controlled by SPI (OUTx_OCR_THX_EN (CR 8).
DS11546 Rev 5
99/197
196
Application information
L99DZ100G, L99DZ100GP
Figure 34. Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR,
thermal expiration occurs after a ∆T = 30°
100/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Figure 35. Block diagram of physical realization of AR alert and thermal expiration
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4.16
Charge pump
The charge pump uses two external capacitors, which are switched with fCP. The output of
the charge pump has a current limitation. In standby mode and after a thermal shutdown
has been triggered the charge pump is disabled. If the charge pump output voltage remains
too low for longer than TCP, the power-MOS outputs and the EC-control are switched off.
The H-bridge MOSFET gate drivers and the Heater MOSFET gate driver are switched to
resistive low and CP_LOW (SR 2) is set. This bit has to be cleared to reactivate the drivers.
If the bit CP_LOW_CONFIG (Configuration Register 0x3F) is set to ‘1’, CP_LOW (SR2)
behaves as a ‘live’ bit and the outputs are re-activated automatically upon recovery of the
charge pump output voltage.
In case of reaching the overvoltage shutdown threshold VSOV the charge pump is disabled
and automatically restarted after VS recovered to normal operating voltage.
Figure 36. Charge pump low filtering and start up implementation
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DS11546 Rev 5
101/197
196
Application information
4.17
L99DZ100G, L99DZ100GP
Inductive loads
Each of the half bridges is built by internally connected high-side and low-side power DMOS
transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can
be driven at the outputs OUT1 to OUT6 without external freewheeling diodes. The high-side
drivers OUT7 to OUT15 and OUT_HS are intended to drive resistive loads only. Therefore
only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in
freewheeling condition. For inductive loads (L > 100 μH) an external freewheeling diode
connected between GND and the corresponding output is required. The low-side driver at
ECV does not have a freewheel diode built into the device.
4.18
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for t > tOL_OUT the corresponding openload bit OUTx_OL (SR 5) is set in the status register.
4.19
Overcurrent detection
An overcurrent condition is detected after a filter time of tFOC and is indicated by the status
bit OUTx_OC (SR 3). In case of overcurrent, the corresponding driver switches off to reduce
the power dissipation and to protect the integrated circuit. If the outputs are not configured in
recovery mode, the microcontroller has to clear the according status bits to reactivate the
corresponding drivers.
4.20
Current monitor
The current monitor sources a current image of the power stage output current at the
current monitor pin CM, which has a fixed ratio (ICMr) of the instantaneous current of the
selected high-side driver. The signal at output CM is blanked for tcmb after switching on the
driver until correct settlement of the circuitry. The bits CM_SELx (CR 7) define which of the
outputs is multiplexed to the current monitor output CM. The current monitor output allows a
more precise analysis of the actual state of the load rather than the detection of an openload or overload condition. For example, it can be used to detect the motor state (starting,
free running, stalled). The current monitor output is enabled after the current-monitor
blanking time, when the selected output is switched on. If this output is off, the current
monitor output is in high impedance mode. The current monitor can be deactivated by
CM_EN (CR 7).
4.21
PWM mode of the power outputs
Description see Section 7.3: Status register overview.
4.22
Cross-current protection
The six half-brides of the device are cross-current protected by an internal delay time. If one
driver (LS or HS) is turned off, the activation of the other driver of the same half bridge will
be automatically delayed by the crosscurrent protection time. After the crosscurrent
102/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
protection time is expired the slew-rate limited switch-off phase of the driver is changed to a
fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this
behavior, it is always guaranteed that the previously activated driver is completely turned off
before the opposite driver starts to conduct.
4.23
Programmable soft-start function to drive loads with higher
inrush current
Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps,
start current of motors) can be driven by using the programmable soft-start function (i.e.
overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit
OUTx_OCR (CR 7). If this bit is set, the device automatically switches the outputs on again
after a programmable recovery time. The PWM modulated current will provide sufficient
average current to power up the load (e.g. heat up the bulb) until the load reaches operating
condition. The PWM frequency is defined by CR7 setting.
The device itself cannot distinguish between a real overload (e.g. short-circuit condition) and
a load characterized by operation currents exceeding the short-circuit threshold.
Examples are non-linear loads like a light bulb used on the HS outputs or a motor used on
the half bridge output with inrush and stall currents that shall be limited by the auto recovery
feature.
For the bulb, a real overload condition can only be qualified by time. For overload detection
the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for
the first e.g. 50 ms. After clearing the recovery bit, the output will be switched off
automatically if the overload condition remains.
For the half bridges the high current can be present during all motor activation and another
SW strategy must be applied to identify a SC to GND or Supply. Before running the motor
e.g. with a first SPI command all bridge LS are switched on (without auto recovery
functionality / cleared overcurrent recovery bit), all HS are switched off and a SC to Battery
can be diagnosed. With a next SPI command, all HS are switched on (without auto recovery
functionality/ cleared overcurrent recovery bit) and all LS are switched off. In this sequence,
a short to GND can be diagnosed. If in both sequences no overload condition is identified,
the motor can be run by switching on the according HS and LS each configured in auto
recovery mode (see Figure 37: Software strategy for half bridges before applying autorecovery mode). Such sequence can be applied before any motor activation to identify SC
just before operating the motor (in case the delay due to the 2 additional SPI commands is
not limiting the application) or in case of power up of the system resp. applied on a certain
time base.
DS11546 Rev 5
103/197
196
Application information
L99DZ100G, L99DZ100GP
Figure 37. Software strategy for half bridges before applying auto-recovery mode
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As soon as an output reaches auto-recovery condition, OUTx_OCR_ALERT (SR 4)) is set.
The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.
104/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Figure 38. Overcurrent recovery mode
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4.24
H-bridge control
The PWMH and DIRH inputs control the drivers of the external H-bridge transistors. In
single Motor mode the motor direction can be chosen with the direction input (DIRH), the
duty cycle and frequency with the PWMH input (single mode). With the SPI bits SD (CR 10)
and SDS (CR 10) four different slow-decay modes (via drivers and via diode) can be
selected using the high-side or the low-side transistors. Unconnected inputs are defined by
internal pull-down current.
Alternatively, the bridge can be driven in half bridge mode (dual mode). By setting the dual
mode bit DM (Config Reg) = 1, both half-bridges can be controlled independently.
DS11546 Rev 5
105/197
196
Application information
L99DZ100G, L99DZ100GP
Table 67. H-bridge control truth table
Output pins
VS_OV
VS_UV
DS
TSD1
GH1
x
0
x
x
x
x
x
x
x
x
RL RL RL RL
H-bridge disabled
2
x
x
1
x
x
0
1
0
0
0
0
RL RL RL RL
Charge pump voltage too low
3
x
x
1
x
x
0
0
x
x
x
1
RL RL RL RL
Thermal shutdown
4
x
x
1
x
x
0
0
1
0
0
0
L
L
L
L
L(1)
L(1)
L(1)
GL2
CP_LOW
x
GH2
DM
1
GL1
Nb
SDS
Comment
SD
Motor
config
HEN
Failure bits
PWMH
Control bits
DIRH
Control
pins
Overvoltage
5
x
x
1
x
x
0
0
0
0
1
0
L(1)
Short-circuit(1)
6
0
1
1
x
x
0
0
0
0
0
0
L
H
H
L
Bridge H2/L1 on
7
x
0
1
0
0
0
0
0
0
0
0
L
H
L
H
Slow-decay mode LS1 and
LS2 on
8
0
0
1
0
1
0
0
0
0
0
0
L
H
L
L
9
1
0
1
0
1
0
0
0
0
0
0
L
L
L
H
Slow-decay mode LS2 on
10
1
1
1
x
x
0
0
0
0
0
0
H
L
L
H
Bridge H1/L2 on
11
x
0
1
1
0
0
0
0
0
0
0
H
L
H
L
Slow-decay mode HS1 and
HS2 on
12
0
0
1
1
1
0
0
0
0
0
0
L
L
H
L
Slow-decay mode HS1 on
13
1
0
1
1
1
0
0
0
0
0
0
H
L
L
L
Slow-decay mode HS2 on
14
0
0
1
1
0
1
0
0
0
0
0
L
L
L
L
15
0
1
1
1
0
1
0
0
0
0
0
L
L
L
H
16
1
0
1
1
0
1
0
0
0
0
0
L
H
L
L
17
1
1
1
1
0
1
0
0
0
0
0
L
H
L
H
18
0
0
1
0
1
1
0
0
0
0
0
L
L
L
L
19
0
1
1
0
1
1
0
0
0
0
0
L
L
H
L
20
1
0
1
0
1
1
0
0
0
0
0
H
L
L
L
21
1
1
1
0
1
1
0
0
0
0
0
H
L
H
L
22
0
0
1
1
1
1
0
0
0
0
0
H
L
H
L
23
0
1
1
1
1
1
0
0
0
0
0
H
L
L
H
24
1
0
1
1
1
1
0
0
0
0
0
L
H
H
L
25
1
1
1
1
1
1
0
0
0
0
0
L
H
L
H
Single
Dual
Slow-decay mode LS1 on
Half bridge mode
1. Only the H-bridge (low-side and high-side), in which one MOSFET is in short-circuit condition is switched off. Both
MOSFETs of the other H-bridge remain active and driven by DIRH and PWMH.
106/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
During watchdog long-open window, the H-bridge drivers are forced off until the first valid
watchdog trigger in window mode (setting TRIG = 0 during safe window). The Control
Registers remain accessible during long open window.
4.25
H-bridge driver slew-rate control
The rising and falling slope of the drivers for the external high-side Power-MOS can be slew
rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is
driven by a current source instead of a low-impedance output driver switch as long as the
drain-source voltage over this Power-MOS is below the switch threshold. The current is
programmed using the bits SLEW_x (CR 10), which represent a binary number. This
number is multiplied by the minimum current step. This minimum current step is the
maximum source-/sink-current (IGHxrmax / IGHxfmax) divided by 31. Programming
SLEW_x to 0 disables the slew rate control and the output is driven by the lowimpedance output driver switch.
Figure 39. H-bridge GSHx slope
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4.26
Resistive low
The resistive output mode protects the devices and the H-bridge in the standby mode and in
some failure modes (thermal shutdown TSD1 (SR 1), charge pump low CP_LOW (SR 2)
and DI pin stuck at ‘1’ SPI_INV_CMD (SR 2)). When a gate driver changes into the resistive
output mode due to a failure a sequence is started. In this sequence the concerning driver is
DS11546 Rev 5
107/197
196
Application information
L99DZ100G, L99DZ100GP
switched into sink condition for 32 μs to 64 μs to ensure a fast switch-off of the H-bridge
transistor. If slew rate control is enabled, the sink condition is slew-rate controlled.
Afterwards the driver is switched into the resistive output mode (resistive path to source).
4.27
Short circuit detection / drain source monitoring
The Drain - Source voltage of each activated external MOSFET of the H-bridge is monitored
by comparators to detect shorts to ground or battery. If the voltage-drop over the external
MOSFET exceeds the configurable threshold voltage VSCd_HB (DIAG_x (CR 10) for longer
t > tSCd_HB the corresponding gate driver switches off the external MOSFET and the
corresponding drain source monitoring flag DS_MON_x (SR 2) is set. The DSMON_x bits
have to be cleared through the SPI to reactivate the gate drivers. This monitoring is only
active while the corresponding gate driver is activated. If a drain-source monitor event is
detected, the corresponding gate-driver remains activated for at maximum the filter time.
When the gate driver switches on, the drain-source comparator requires the specified
settling time until the drain-source monitoring is valid. During this time, this drain-source
monitor event may start the filter time. The threshold voltage VSCd_HB can be programmed
using the SPI bits DIAG_x (CR 10).
Figure 40. H-bridge diagnosis
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4.28
H-bridge monitoring in off-mode
The drain source voltages of the H-bridge driver external transistors can be monitored, while
the transistors are switched off. If either bit OL_H1L2 (CR 10) or OL_H2L1 (CR 10) is set to
108/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
1, while bit HEN (CR 1) = 1, the H-drivers enter resistive low mode and the drain-source
voltages can be monitored. Since the pull-up resistance is equal to the pull-down resistance
on both sides of the bridge a voltage of 2/3 VS on the pull-up highside and 1/3 VS on the lowside is expected, if they drive a low-resistive inductive load (e.g. motor). If the drain source
voltage on each of these Power-MOS is less than 1/6 VS, the drain-source monitor bit of the
associated driver is set.
The open-load filter time is tOL_HB.
Figure 41. H-bridge open-load-detection (no open-load detected)
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DS11546 Rev 5
109/197
196
Application information
L99DZ100G, L99DZ100GP
Figure 43. H-bridge open-load-detection (short to ground detected)
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Table 68. H-bridge monitoring in off-mode
Control bits
Failure bits
Comments
Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2
110/197
1
0
0
0
0
0
Drain-Source monitor
disabled
2
1
0
x
0
0
No open-load detected
3
1
0
0
0
1
Open-load SH2
4
1
0
0
1
1
Short to GND
5
1
0
1
1
1
Short to VS
6
0
1
x
0
0
No open-load detected
7
0
1
0
1
0
Open-load SH1
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Table 68. H-bridge monitoring in off-mode (continued)
Control bits
Failure bits
Comments
Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2
4.29
8
0
1
0
1
1
Short to GND
9
0
1
1
1
1
Short to VS
Programmable cross current protection
The external PowerMOSFETs transistors in H-bridge (two half-bridges) configuration are
switched on with an additional delay time tCCP to prevent cross current in the halfbridge. The
cross current protection time tCCP can be programmed with the SPI bits COPT_x
(CR 10). The timer is started when the gate driver is switched on in the device.
The PWMH module has 2 timers to configure locking time for high-side and freewheeling
low-side. The programmable time tCCP-TIM1 / tCCP-TIM2 is the same. Sequence for switching
in PWM mode is the following:
HS switch off after locking tCCP-TIM1
LS switch on after 2nd locking tCCP-TIM1
HS switch on after locking tCCP-TIM2 which starts with rising edge on PWM input
Figure 45. PWMH cross current protection time implementation
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4.30
Power window H-bridge safety switch off block
The two LS Switches LS1_FSO and LS2_FSO are intended to be used to switch off the
gates of the external high-side MOSFETs in the power window h-bridge if a fatal error
happens. This block must work also in case the MOSFET driver and the according control
blocks on the chip are destroyed. Therefore it is necessary to have a complete separated
safety block on the device, which has it’s own supply and GND connection, separated from
the other supplies and GNDs. In the block is implemented an own voltage regulator and
oscillator.
The safety block is surrounded by a GND isolation ring realized by deep trench isolation.
The LS driver must work down to a lower voltage than the other circuits. The block has its
DS11546 Rev 5
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196
Application information
L99DZ100G, L99DZ100GP
own internal supply and an own oscillator for monitoring the failure signals (WWD, V1 fail,
SPI fail & Tj) which are Manchester encoded and decoupled by high ohmic resistances. In
case of fail-safe event, both LS switches LS1_FSO and LS2_FSO are switched on.
In case of entering V1_standby mode or Vbat_standby mode both fail safe low-side
switches are switched on to minimize the current drawn by the fail safe block (e.g. oscillator
is switched off and Manchester Encoding is deactivated). Short circuit protection to VS is
active in both standby modes limiting the current to IOLimit for a filter of tSCF.
After this filter time the fail-safe switches are switched off and LSxFSO_OC (SR 3) is set. To
reactivate the low-side functionality this bit has to be set back by a read and clear command.
In case of VS loss the fail safe switches are biased by their own output voltage to turn on the
low-side switches down to VOUT_max.
To allow verification of the Fail-Safe path, the low-side switches LS1_FSO and LS2_FSO
can be turned on by SPI (Configuration Register 0x3F bit 4: FS_FORCED)
Figure 46. LSx_FSO: low-side driver “passively” turned on, taking supply from output
pin (if main supply fails), can guarantee VLSx_FSO < VOUT_max
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DS11546 Rev 5
L99DZ100G, L99DZ100GP
4.31
Application information
Heater MOSFET Driver
The Heater MOSFET Driver stage is controlled by control bit GH (CR 5). The driver contains
two diagnosis features to indicate short-circuit in active mode (external MOSFET switched
on) and open-load in off state (External MOSFET switched off).
Short circuit detection in on state is realized by monitoring the drain source voltage of the
activated external MOSFET by a comparator to detect a short-circuit of SHheater to ground. If
the voltage-drop over the external MOSFET exceeds the programmed threshold voltage
VSCd_HE for longer than the drain-source monitor filter time tSCd_HE the gate driver switches
off the external MOSFET and the corresponding drain source monitoring flag
DSMON_HEAT (SR 4) is set. The drain source-monitoring bit has to be cleared by SPI to
reactivate the gate driver. The drain source monitoring is only active while the gate driver is
activated. If a drain source monitoring event is detected, the gate-driver remains activated
for the maximum filter time. The threshold voltage can be programmed by SPI bits GH_THx
(CR 10).
Open-load detection in off state is realized by monitoring the voltage difference between
SHheater and GND and supplying SHheater by a pull up current source that can be controlled
by SPI bit GH_OL_EN (CR 10). When no load is connected to the external MOSFET
source, the voltage will be pulled to VS and in case of exceeding the threshold VOLheater for
a time longer than the open-load filter time tOL_He the open-load bit GH_OL (SR 5) will be
set.
Figure 48. Heater MOSFET open-load and short-circuit to GND detection
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196
Application information
L99DZ100G, L99DZ100GP
Table 69. Heater MOSFET control truth table
Control bit
Failure bits
Output pin
Comment
Nb
GH
ON/OFF
1
x
1
x
2
x
0
3
x
4
CP_LOW VS_OV VS_UV
DS
TSD1
GHheater
x
x
x
RL
Charge puump voltage too low
x
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1
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Thermal shutdown
0
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Overload
1
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x
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5
x
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Undervoltage
6
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0
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Heater MOFET driver enabled
7
0
0
0
0
0
0
L
Heater MOFET driver enabled
Note:
RL = resistive low, L = active low, H = active high.
4.32
Controller of electro-chromic glass
The voltage of an electro-chromic element connected at pin ECV can be controlled to a
target value, which is set by the bits EC_x (CR 11). Setting bit ECON (CR 11) enables
this function. An on-chip differential amplifier and an external MOS source follower, with its
gate connected to pin ECDR, and which drives the electro-chrome mirror voltage at pin
ECV, form the control loop. The drain of the external MOS transistor is supplied by OUT10.
A diode from pin ECV (anode) to pin ECDR (cathode) has been placed on the chip to
protect the external MOS source follower. A capacitor of at least 5 nF has to be added to pin
ECDR for loop-stability.
The target voltage is binary coded with a full-scale range of 1.5 V. If bit ECV_HV (Config
Reg) is set to 0, the maximum controller output voltage is clamped to 1.2 V without changing
the resolution of bits EC_x (CR 11). When programming the ECV low-side driver
ECV_LS (CR 11) to on-state, the voltage at pin ECV is pulled to ground by a 1.6 Ω low-side
switch until the voltage at pin ECV is less than dVECVhi higher than the target voltage (fast
discharge). The status of the voltage control loop is reported via SPI. Bit ECV_VHI (SR 6) is
set, if the voltage at pin ECV is higher, whereas Bit ECV_VNR (SR 6) is set, if the voltage at
pin ECV is lower than the target value. Both status bits are valid, if they are stable for at
least the filter time tFEC_VNR and tFEC_VHI. Since OUT10 is the output of a high-side driver, it
contains the same diagnose functions as the other high-side drivers (e.g. during an
overcurrent detection, the control loop is switched off). In electro-chrome mode, OUT10
cannot be controlled by PWM mode. For EMS reasons, the loop capacitor at pin ECDR as
well as the capacitor between ECV and GND has to be placed to the respective pins as
close as possible (seeFigure 49: Electro-chrome control block for details).
Pin ECDR is pulled resistively (RECDRDIS) to ground while not in electro-chrome mode.
EC glass control behavior in case of failure on OUT10:
114/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
ECON (CR11) = 1 (EC glass control enabled)
OUT10 is turned ON
OUT10 settings in CR5 are ignored (PWM, DIRx, TIMERx)
OUT10 settings in CR5 are recovered when ECON is set to 0.
In case of a failure on OUT10 while ECON = 1 (overcurrent, VS overvoltage /undervoltage,
TSD1)
OUT10 is turned OFF (regardless of VS_OV_SD_EN and VS_UV_SD_EN in CR3)
DAC is reset: EC_x (CR11) set to ‘000000’
ECDR pin is pulled to GND
ECON (CR11) remains ‘1’
ECV_LS (CR11) remains as programmed
Re-start of EC control after OUT10 failure
Read&Clear or automatic restart (if CR3 Vs_LOCK_EN = 0)
Write EC_x (CR11)
Figure 49. Electro-chrome control block
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4.33
Temperature warning and shutdown
If any of the cluster (see Section 4.34: Thermal clusters) junction temperatures rises above
the temperature warning threshold TW, the temperature warning flag TW (SR 2) is set after
the temperature warning filter time tjtft and can be read via SPI. If the junction temperature
increases above the temperature shutdown threshold (TSD1), the thermal shutdown bit
TSD1 (SR 1) is set and the power transistors of all output stages are switched off to protect
the device after the thermal shutdown filter time. The gates of the H-bridge and the heater
MOSFET are discharged by the ‘Resistive Low’ mode. After these bits have been cleared,
the output stages are reactivated. If the temperature is still above the thermal warning
threshold, the thermal warning bit is set after tjtft. Once this bit is set and the temperature is
above the temperature shutdown threshold, temperature shutdown is detected after tjtft and
DS11546 Rev 5
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196
Application information
L99DZ100G, L99DZ100GP
the outputs are switched off. Therefore the minimum time after which the outputs are
switched off after the bits have been cleared in case the temperature is still above the
thermal shutdown threshold is twice the thermal warning/ thermal shutdown filter time tjtft.
4.34
Thermal clusters
In order to provide an advanced on-chip temperature control, the power outputs are
grouped in six clusters with dedicated thermal sensors. The sensors are suitably located on
the device (see Figure 50: Thermal clusters identification). In case the temperature of an
output cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster
are shut down (all other outputs remain active). Each output cluster has a dedicated
temperature warning and shutdown flag (SR 6) and the cluster temperature can be read out
by SPI.
Hence, the thermal cluster concept allows to identify a group of outputs in which one or
more channels are in overload condition.
If thermal shutdown has occurred within an output cluster, or if temperature is rising within a
cluster, it may be desired to identify which of the output (s) is (are) determining the
temperature increase. An additional evaluation, based on current monitoring and cluster
temperature read-out, supports identification of the outputs mainly contributing to the
temperature increase. The cluster temperatures are available in SR 7, SR 8 and SR 9 and
can be calculated from the binary coded register value using the following formula:
Decimal code = (350 – Temp) / 0.488
Example:
T = -40 °C => decimal code is 799 (0x31F)
T = 25 °C => decimal code is 666 (0x29A)
Thermal clusters can be configured using bit TSD_CONFIG (Config Reg):
Standard mode (default): as soon as any cluster reaches thermal threshold the device
is switched off. V1 regulator remains on and is switched off reaching TSD2.
Cluster mode: only the cluster which reached shutdown temperature is switched off.
If Cluster Th_CL6 (global) or Cluster Th_CL5 (Voltage Regulators) reachTSD1, the whole
device is OFF (beside V1).
Note:
116/197
Clusters related to power outputs (clusters 1 to 4, see Figure 50: Thermal clusters
identification) will be managed digitally only, by mean of the ADC conversion of related
thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators)
since ADC can be off, e.g. in V1_standby mode. Temperature reading provided by ADC may
differ from real junction temperature of a specific output due to spatial placement of thermal
sensor. Such an effect is more visible during fast thermal increases of junction temperature.
For some of the Power outputs, located between two different sensors, it may happen that
temperature raising also affects the adjacent Cluster.
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
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Th_CL1
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4.35
VS compensation (duty cycle adjustment) module
All stand-alone HS outputs can be programmed to calculate some internal duty cycle
adjustment to adapt the duty cycle to a changing supply voltage at VS. This feature is aimed
to avoid LED brightness flickering in case of alternating supply voltage. The correction of the
duty cycle is based on the following formula:
Equation 1: Duty cycle correction
V th – V LED
DutyCycle = --------------------------------- DC nom
V Bat – V LED
Vth = Duty cycle reference voltage: defined as 10 V
DS11546 Rev 5
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196
Application information
L99DZ100G, L99DZ100GP
VBat = Reference voltage: defined as voltage at pin VS
VLED = Voltage drop on the external LED
DCnom = Nominal Duty Cycle programmed by SPI< PWMx DCx>
To be compatible to different LED load characteristics the value for VLED can be
programmed for each output by a dedicated control register OUT7_VLED …
OUT_HS_VLED (CR 18 to CR 22). Auto compensation features can be activated for all HS
outputs each by setting OUTx_AUTOCOMP_EN (CR 18 to CR 22).
The programmed LED voltage (OUTx_V_LED (CR18 to CR22)) must be lower than Vth
(10 V).
Figure 51. Block diagram VS compensation (duty cycle adjustment) module
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4.36
Analog digital converter
Voltage signals VS, VSREG, VWU and TH_CL1..6 are read out sequentially. The voltage
signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, that is sampled
with the main clock fclk2 / fADC.
Each channel will be converted with a conversion time tcon, therefore an update of the ADC
value is available every tcon * 9. In case of WU is directly connected to Clamp 30, the input
must be protected by a series resistance of typical 1kΩ to sustain reverse battery condition.
118/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Application information
Figure 52. Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6
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119/197
196
Serial Peripheral Interface (SPI)
5
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
A 32-bit SPI is used for bi-directional communication with the microcontroller.
The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK. This device is not limited to
microcontroller with a built-in SPI. Only three CMOS-compatible output Pins and one input
Pin will be needed to communicate with the device. A fault condition can be detected by
setting CSN to low. If CSN = 0, the DO-Pin will reflect the global error flag (fault condition) of
the device.
Chip Select Not (CSN)
The input Pin is used to select the serial interface of this device. When CSN is high, the
output Pin (DO) is in high impedance state. A low signal activates the output driver and
a serial communication can be started. The state during CSN = 0 is called a
communication frame. If CSN = low for t > tCSNfail the DO output will be switched to
high impedance in order to not block the signal line for other SPI nodes.
Serial Data In (DI)
The input Pin is used to transfer data serial into the device. The data applied to the DI
will be sampled at the rising edge of the CLK signal and shifted into an internal 32-bit
shift register. At the rising edge of the CSN signal the content of the shift register will be
transferred to Data Input Register. The writing to the selected Data Input Register is
only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN
low). If more or less clock pulses are counted within one frame the complete frame will
be ignored. This safety function is implemented to avoid an activation of the output
stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go
from high impedance to a low or high level depending on the global error flag (fault
condition). The first rising edge of the CLK input after a high to low transition of the
CSN Pin will transfer the content of the selected status register into the data out shift
register. Each subsequent falling edge of the CLK will shift the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data
input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change
with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up
to 4 MHz.
5.1
ST SPI 4.0
The ST-SPI is a standard used in ST Automotive ASSP devices.
120/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
This chapter describes the SPI protocol standardization. It defines a common structure of
the communication frames and defines specific addresses for product and status
information.
The ST-SPI allows usage of generic software to operate the devices while maintaining the
required flexibility to adapt it to the individual functionality of a particular product. In addition,
failsafe mechanisms are implemented to protect the communication from external
influences and wrong or unwanted usage.
The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0.
5.1.1
Physical layer
Figure 53. SPI pin description
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Signal description
Chip Select Not (CSN)
The communication interface is de-selected, when this input signal is logically high. A
falling edge on CSN enables and starts the communication while a rising edge finishes
the communication and the sent command is executed when a valid frame was sent.
During communication start and stop the Serial Clock (SCK) has to be logically low.
The Serial Data Out (SDO) is in high impedance when CSN is high or a communication
timeout was detected.
Serial Clock (SCK)
This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is
latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on
the falling edge data from the internal shift registers are shifted out to Serial Data Out
(SDO).
Serial Data Input (SDI)
This input is used to transfer data serially into the device. Data is latched on the rising
edge of Serial Clock (SCK).
Serial Data Output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out
on the falling edge of Serial Clock (SCK).
DS11546 Rev 5
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196
Serial Peripheral Interface (SPI)
L99DZ100G, L99DZ100GP
Figure 54. SDO pin
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Clock and Data Characteristics
The ST-SPI can be driven by a microcontroller with its SPI peripheral running in following
mode:
CPOL = 0
CPHA = 0
Figure 55. SPI signal description
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The communication frame starts with the falling edge of the CSN (Communication Start).
SCK has to be low.
The SDI data is then latched at all following rising SCK edges into the internal shift registers.
After Communication Start the SDO will leave 3-state mode and present the MSB of the
data shifted out to SDO. At all following falling SCK edges data is shifted out through the
internal shift registers to SDO.
122/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
The communication frame is finished with the rising edge of CSN. If a valid communication
took place (e.g. correct number of SCK cycles, access to a valid address), the requested
operation according to the Operating Code will be performed (Write or Clear operation).
5.2.2
Communication protocol
SDI Frame
The devices Data-In Frame consist of 32-bit (OpCode (2 bits) + Address (6 bits) + Data Byte
3 + Data Byte 2 + Data Byte 1). The first two transmitted bits (MSB, MSB-1) contain the
Operation Code which represents the instruction which will be performed. The following 6
bits (MSB-2 to MSB-7) represent the address on which the operation will be performed. The
subsequent bytes contain the payload.
Figure 56. SDI Frame
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Operating code
The operating code is used to distinguish between different access modes to the registers of
the slave device.
Table 71. Operation codes
OC1
OC0
Description
0
0
Write Operation
0
1
Read Operation
1
0
Read & Clear Operation
1
1
Read Device Information
A Write Operation will lead to a modification of the addressed data by the payload if a write
access is allowed (e.g. Control Register, valid data). Beside this a shift out of the content
(data present at Communication Start) of the registers is performed.
A Read Operation shifts out the data present in the addressed register at Communication
Start. The payload data will be ignored and internal data will not be modified. In addition a
Burst Read can be performed.
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196
Serial Peripheral Interface (SPI)
L99DZ100G, L99DZ100GP
A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared
are defined first by address, second by payload bits set to ‘1’. Beside this a shift out of the
content (data present at Communication Start) of the registers is performed.
Note:
Status registers which change status during communication could be cleared by the actual
Read & Clear Operation and are neither reported in actual communication nor in the
following communications. To avoid a loss of any reported status it is recommended just
clear status registers which are already reported in the previous communication (Selective
Bitwise Clear).
Advanced operation codes
To provide beside the separate write of all control registers and the bitwise clear of all status
registers, two Advanced Operation Codes can be used to set all control registers to the
default value and to clear all status registers. A ‘set all control registers to default’ command
is performed when an OpCode ‘11’ at address b’111111 is performed.
Note:
Please consider that potential device specific write protected registers cannot be cleared
with this command as therefore a device Power-on-Reset is needed.
A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address
b’111111 is performed.
Data-in payload
The Payload (Data Byte 1 to Data Byte 3) is the data transferred to the devices with every
SPI communication. The Payload always follows the OpCode and the Address bits. For
Write access the Payload represents the new data written to the addressed register. For
Read & Clear operations the Payload defines which bits of the adressed Status Register will
be cleared. In case of a ‘1’ at the corresponding bit position the bit will be cleared.
For a Read Operation the Payload is not used. For functional safety reasons it is
recommended to set unused Payload to ‘0’.
SDO frame
The data-out frame consists of 32-bit (GSB + Data Byte 1 to 3).
The first eight transmitted bits contain device related status information and are latched into
the shift register at the time of the Communication Start. These 8-bit are transmitted at every
SPI transaction. The subsequent bytes contain the payload data and are latched into the
shift register with the eighth positive SCK edge. This could lead to an inconsistency of data
between the GSB and Payload due to different shift register load times. Anyhow, no
unwanted Status Register clear should appear, as status information should just be cleared
with a dedicated bit clear after.
124/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
Figure 57. SDO frame
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Global Status Byte (GSB)
The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the Status
Registers. Therefore no direct Read & Clear can be performed on these bits inside the GSB.
Table 72. Global Status Byte
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
GSBN
RSTB
SPIE
PLE
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DE
GW
FS
Global Status Bit Not (GSBN)
The GSBN is a logically NOR combination of Bit 24 to Bit 30. This bit can also be used as
Global Status Flag without starting a complete communication frame as it is present directly
after pulling CSN low.
Reset Bit (RSTB)
The RSTB indicates a device reset. In case this bit is set, specific internal Control Registers
are set to default and kept in that state until the bit is cleared. The RSTB bit is cleared after
a Read & Clear of all the specific bits in the Status Registers which caused the reset event.
SPI Error (SPIE)
The SPIE is a logical OR combination of errors related to a wrong SPI communication.
Physical Layer Error (PLE)
The PLE is a logical OR combination of errors related to the LIN and HS CAN transceivers.
Functional Error (FE)
The FE is a logical OR combination of errors coming from functional blocks (e.g. High-side
overcurrent).
Device Error (DE)
The DE is a logical OR combination of errors related to device specific blocks (e.g. VS
overvoltage, overtemperature
DS11546 Rev 5
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Serial Peripheral Interface (SPI)
L99DZ100G, L99DZ100GP
Global Warning (GW)
The GW is a logical OR combination of warning flags (e.g. thermal warning).
Fail Safe (FS)
The FS bit indicates that the device was forced into a safe state due to mistreatment or
fundamental internal errors (e.g. Watchdog failure, Voltage regulator failure).
Data-Out Payload
The Payload (Data Bytes 1 to 3) is the data transferred from the slave device with every SPI
communication to the master device. The Payload always follows the OpCode and the
address bits of the actual shifted in data (In-frame-Response).
5.2.3
Address definition
Table 73. Device application access
Operating Code
OC1
OC0
0
0
0
1
1
0
Table 74. Device information read access
Operating Code
OC1
OC0
1
1
Table 75. RAM address range
RAM Address
Access
3FH
Configuration Register
R/W
3CH
Status Register 12
R/C
…
…
32H
Status Register 2
R/C
31H
Status Register 1
R/C
…
…
22H
Control Register 34
R/W
1DH
Control Register 29
R/W
…
02H
126/197
Description
…
Control Register 2
DS11546 Rev 5
R/W
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
Table 75. RAM address range (continued)
RAM Address
Description
01H
Control Register 1
00H
reserved
Access
R/W
Table 76. ROM address range
ROM Address
Description
Access
3FH
W
3EH
R
20H
R
16H
R
15H
R
14H
R
13H
R
12H
R
11H
R
10H
R
R
06H
R
05H
R
04H
R
03H
R
02H
R
01H
R
00H
R
…
…
0AH
…
Information registers
The Device Information Registers can be read by using OpCode ‘11’. After shifting out the
GSB the 8-bit wide payload will be transmitted. By reading Device Information Registers a
communication width which is minimum 16-bit plus a multiple by 8 can be used. After
shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the
SDO.
DS11546 Rev 5
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Serial Peripheral Interface (SPI)
L99DZ100G, L99DZ100GP
Table 77. Information Registers Map
ROM
Adress
Description
Access
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3FH
3EH
R
→
0
0
0
0
0
0
0
0
20H
R
→
0
1
0
1
0
1
0
1
16H
R
→
C0H
15H
R
→
7FH
14H
R
→
C0H
13H
R
→
41H
12H
R
→
91H
11H
R
→
28H
10H
R
→
B0H
…
…
0AH
→
R
…
→
major revision
minor revision
→
L99DZ100G: 01H
L99DZ100GP: 00H
06H
R
05H
R
→
09H
04H
R
→
46H
03H
R
→
42H
02H
R
→
55H
01H
R
→
01H
00H
R
→
00H
Device Identification Registers
These registers represent a unique signature to identify the device and silicon version.
: 00H (STMicroelectronics)
: 01H (BCD Power Management)
: 55H
: 42H
: 46H
: 09H
: for L99DZ100G: 01H for L99DZ100GP: 00H
128/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
SPI modes
By reading out the register general information of SPI usage of the Device
Application Registers can be read.
Table 78. SPI Mode Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BR
DL2
DL1
DL0
0
0
S1
S0
1
0
1
1
0
0
0
0
: B0H (Burst mode read available, 32-bit, no data consistency check)
SPI Burst Read
Table 79. Burst Read Bit
Bit 7
Description
0
BR not available
1
BR available
The SPI Burst Read bit indicates if a burst read operation is implemented. The intention of a
Burst Read is e.g. used to perform a device internal memory dump to the SPI Master.
The start of the Burst Read is like a normal Read Operation. The difference is, that after the
SPI Data Length the CSN is not pulled high and the SCK will be continuously clocked. When
the normal SCK max count is reached (SPI Data Length) the consecutive addressed data
will be latched into the shift register. This procedure is performed every time when the SCK
payload length is reached.
In case the automatic incremented address is not used by the device, undefined data is
shifted out. An automatic address overflow is implemented when address 3FH is reached.
The SPI Burst Read is limited by the CSN low timeout.
SPI Data Length
The SPI Data Length value indicates the length of the SCK count monitor which is running
for all accesses to the Device Application Registers. In case a communication frame with an
SCK count not equal to the reported one will lead to a SPI Error and the data will be
rejected.
DS11546 Rev 5
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196
Serial Peripheral Interface (SPI)
L99DZ100G, L99DZ100GP
Table 80. SPI Data Length
Bit 6
Bit 5
Bit 4
Description
DL2
DL1
DL0
0
0
0
invalid
0
0
1
16-bit SPI
0
1
0
24-bit SPI
0
1
1
32-bit SPI
…
1
1
1
64-bit SPI
Data Consistency Check (Parity/CRC)
N/A
Table 81. Data Consistency Check
Bit 1
Bit 0
Description
S1
S0
0
0
not used
0
1
Parity used
1
0
CRC used
1
1
Invalid
Watchdog Definition
In case a watchdog is implemented the default settings can be read out via the Device
Information Registers.
Table 82. WD Type/Timing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WD1
WD0
0
0
0
1
WT5
WT4
WT3
1
1
0
1
Bit 2
Bit 1
Bit 0
WT2
WT1
WT0
0
0
0
Register is not used
Watchdog Timeout / Long Open Window WT[5:0] * 5ms
1
0
OW2
OW1
OW0
CW2
CW1
CW0
1
0
0
1
0
0
0
1
Open Window OW[2:0] *
5ms
130/197
DS11546 Rev 5
Closed Window CW[2:0] *
5ms
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
Table 82. WD Type/Timing (continued)
Bit 7
Bit 6
1
1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Invalid
: 28H (Long Open Window: 200ms)
: 91H (Open Window. 10ms, Closed Window: 5ms)
indicates the Long Open Window (timeout) which is opened at the start of the
watchdog. The binary value of WT[5:0] times 5ms indicates the typical value of the Timeout
Time.
describes the default timing of the window watchdog.
The binary value of CW[2:0] times 5ms defines the typical Closed Window time and OW[2:0]
times 5ms defines the typical Open Window time.
Figure 58. Window watchdog operation
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The watchdog trigger bit location is defined by the registers.
Table 83. WD bit position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WB1
WB0
0
0
0
1
WBA5
WBA4
WBA3
0
1
0
0
0
1
1
1
Bit 2
Bit 1
Bit 0
WBA2
WBA1
WBA0
0
0
0
1
1
1
1
1
Register is not used
Defines the register addresses of the WD trigger bits
1
0
WBA5
DS11546 Rev 5
WBA4
WBA3
WBA2
WBA1
WBA0
131/197
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Serial Peripheral Interface (SPI)
L99DZ100G, L99DZ100GP
Table 83. WD bit position (continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Defines the stop address of the address range (previous
is a WB = ‘01’). The consecutive has to be a WB = ‘11’
1
1
0
WBP 4
WBP3
WBP2
WBP1
WBP0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Defines the binary bit position of the WD trigger
bit within the register
: 41H;watchdog trigger bit located at address 01H (CR1)
: C0H; watchdog trigger bit location is bit0
: 7FH;watchdog trigger bit located at address 3FH (Config Register)
: C0H; watchdog trigger bit location is bit0
Device Application Registers (RAM)
The Device Application Registers are all registers accessible using OpCode ‘00’, ‘01’ and
‘10’. The functions of these registers are defined in the device specification.
5.2.4
Protocol failure detection
To realize a protocol which covers certain failsafe requirements a basic set of failure
detection mechanisms are implemented.
Clock monitor
During communication (CSN low to high phase) a clock monitor counts the valid SCK clock
edges. If the SCK edges do not correlate with the SPI Data Length an SPIE is reported with
the next command and the actual communication is rejected.
By accessing the Device Information Registers (OpCode = ‘11’) the Clock Monitor is set to a
minimum of 16 SCK edges plus a multiple by 8 (e.g. 16, 25, 32, …). Providing no SCK edge
during a CSN low to high phase is not recognized as an SPIE. For a SPI Burst Read also
the SPI Data Length plus multiple numbers of Payloads SCK edges are assumed as a valid
communication.
SCK Polarity (CPOL) check
To detect the wrong polarity access via SCK the internal Clock monitor is used. Providing
first a negative edge on SCK during communication (CSN low to high phase) or a positive
edge at last will lead to an SPI Error reported in the next communication and the actual data
is rejected.
SCK Phase (CPHA) check
To verify, that the SCK Phase of the SPI master is set correctly a special Device Information
Register is implemented. By reading this register the data must be 55H. In case AAH is read
132/197
DS11546 Rev 5
L99DZ100G, L99DZ100GP
Serial Peripheral Interface (SPI)
the CPHA setting of the SPI master is wrong and a proper communication cannot be
guaranteed.
CSN timeout
By pulling CSN low the SDO is set active and leaves its 3-state condition. To ensure
communication between other SPI devices within the same bus even in case of CSN stuck
at low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After
timer end is reached the actual communication is rejected and the SDO is set to 3-state
condition.
SDI stuck at GND
As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be
distinguished between a valid command and a SDI stuck at GND this communication is not
allowed. Nevertheless, in case a stuck at GND is detected the communication will be
rejected and the SPIE will be set with the next communication.
SDI stuck at HIGH
As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be
distinguished between a valid command and a SDI stuck at HIGH this communication is not
allowed. In case a stuck at HIGH is detected the communication will be rejected and the
SPIE will be set with the next communication.
SDO stuck @
The SDO stuck at GND and stuck at HIGH has to be detected by the SPI master. As the
definition of the GSB guarantees at least one toggle, a GSB with all-‘0’ or all –‘1’ reports a
stuck at error.
DS11546 Rev 5
133/197
196
Application
6
L99DZ100G, L99DZ100GP
Application
Figure 59. Typical application diagram
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