L99LD01
High efficiency constant current LED driver for automotive
applications
Datasheet - production data
• Regulated output for micro supply 5 V ± 2 %
-20 mA
40
V
• Parameter programming and settings of
internal memory registers by the dedicated SPI
interface:
– LED current reference adjusting (± 66.7 %)
– Maximum input current limiter reference
adjusting (± 55.5 %)
– Random dither frequency sweeping,
modulation frequency and deviation
percentage
5.6 - 24
V
• Power on reset pin output
100 - 500
kHz
LQFP32
7x7 mm
GAPG1506151117CFT
Features
Max VBATT
Operation supply battery voltage
VBATT
Oscillator frequency range
• ESD protection
Applications
• Automotive qualified
Automotive day time running light, LED
HeadLamps
• Constant current operation
• Current LED settable by external sensing
resistor and adjustable via SPI
• Converter switching frequency adjustable by
external resistor (RSF)
• EMC reduction by internal spread spectrum
dither oscillator
• Low frequency PWM dimming operation.
• Maximum input current limiter
• Maximum switching duty cycle limiter
• Slope compensation adjustable by external
resistor (R9)
• Battery overvoltage shut down protection (ext.
R3, R4 resistors required)
• Led chain OV detection (ext. R5, R6)
• Multiplexed output for monitoring and control of
LED temperature (external NTC resistor
required), voltage of LED chain, and low
frequency PWM
• SPI communication serial interface transceiver
(SDI, SDO, SCK, CSN)
June 2015
This is information on a product in full production.
Description
L99LD01 is a precise constant current DC–DC
converter LED driver for automotive applications,
dedicated to the control of high-brightness LED
headlights and housed in a LQFP32™ package.
The device is designed to be used in Boost, BuckBoost and Fly back converter topologies. An
internal random dither oscillator works in low
frequency modulation, allowing the RF spectrum
of the switching frequency to spread so to reduce
EMC emissions. The slope compensation
ensures good converter loop stability whatever is
the duty cycle needed by the application.
The converter is able to work either in full power
mode or in low frequency dimming mode.
The device includes an internal low drop voltage
regulator, that can be used to supply a
microcontroller, and a reset pin, that is useful for
resetting the microcontroller at the start up and
every time that the regulated output voltage falls
down below an established voltage threshold.
DocID025319 Rev 3
1/69
www.st.com
Contents
L99LD01
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
3
2/69
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
Operation with an external microcontroller . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2
Stand alone operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3
Start-up fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5
Software limp home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.6
Limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1
LED current adjust and temperature control . . . . . . . . . . . . . . . . . . . . . 16
2.2.2
Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.3
LED chain overvoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.4
Battery overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.5
Regulators thermal shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.7
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.8
Standby and wake up by ENABLE pin . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.9
Frequency setting and dither effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.10
Start up LED overvoltage management . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.11
Programming the over/under voltage threshold . . . . . . . . . . . . . . . . . . . 27
2.2.12
Input overvoltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.1
Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 31
3.2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3
SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.1
SDI, SDO format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.2
Global status byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.3
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5
Control registers (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.6
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID025319 Rev 3
L99LD01
4
Contents
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6
SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.1
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7
Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8.2
LQFP32™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DocID025319 Rev 3
3/69
3
List of tables
L99LD01
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
4/69
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Limp home mode: recovery paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Suggested KL value and overvoltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Input data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Internal oscillator frequency deviation settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal oscillator frequency modulation settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Watchdog timer status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
VS and VCC1 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
VCC2 and C5V pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
NRES and LMODE pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
G1 driver 1 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
G2 pin characteristics (driver2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Converter oscillator and RSF pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PWM_L, PWM, MOUT pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ISENSE+, ISENSE- pin, and O.T.A. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SC pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VLED pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
INP_OV pin characteristics (input overvoltage shut down). . . . . . . . . . . . . . . . . . . . . . . . . 52
NTC pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ENABLE, LHM pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Watchdog and timers parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SPI AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LQFP32™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DocID025319 Rev 3
L99LD01
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection diagram (top view – not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Normal start up vs VS ramp up and VCC1 voltage dips. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VCC1_FAIL or VCC1 reset under voltage (VS > VSMIN) at start up . . . . . . . . . . . . . . . . . . . . 14
VCC1 reset under voltage at start up (VS < VSMIN) and fast VS ramp down . . . . . . . . . . . . 15
Slow vs ramp down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal structure of the slope compensation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operation with a standalone LIN and ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operation with PM device and ENABLE (FSO active Low) . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal structure of main converter oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Converter frequency range vs RSF and IRSF vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . 23
Correct start UP with no LED overvoltage failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LED overvoltage after tDStart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device behavior in case the low to high transition of PWM_L signal happens after tDStart
expiration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LED overvoltage event not caused by a VS overvoltage event . . . . . . . . . . . . . . . . . . . . . 26
LED overvoltage detection due to a possible battery VS overvoltage . . . . . . . . . . . . . . . . 27
Behavior of LED overvoltage recovery bit with low on-time of PWM_L . . . . . . . . . . . . . . . 27
LED chain overvoltage thresholds settings. An example for boost and fly back converters28
Input overvoltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SPI global error information output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SPI write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SPI read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SPI read and clear operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SPI read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Principle of the WD_Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Voltage and current conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SPI input and output timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SPI maximum clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
NRES pin open drain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Handshake procedure at start up with microcontroller on board . . . . . . . . . . . . . . . . . . . . 58
Boost application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Fly back application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Buck-boost application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Stand alone application example for boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reverse battery protection: an example for boost topology . . . . . . . . . . . . . . . . . . . . . . . . 63
External MOS required during PWM dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LQFP32™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DocID025319 Rev 3
5/69
5
Block diagram and pin description
1
L99LD01
Block diagram and pin description
Figure 1. Block diagram
9&&
96
56)
9ROWDJH5HJXODWRU
%DQGJDS5HI
0DLQ
2VFLOODWRU
9ROWDJH
5HJXODWRU
5&&203
&9
6&
9&&
'3B9
95()
4
6
'XW\0D[
26&B5$03
26&B5$03
,13B29
0287
3:0
(1$%/(
6WDWH0DFKLQH)RU3DUDPHWHU
6HWWLQJV'LDJQRVWLF :'
/+0
/('B2&
/('&XUUHQW
$GMXVW 17&
&RQWURO
(1B17&
9/5()
,6(16(
,6(16(
&KDUJH3XPS
917&B7+
7:
29
'5,9(5
/('2YHU
9ROWDJH
'HWHFWLRQ
9/('
9
,/02'(
/02'(
$QDORJ08;
/6
&3%
*
(;7B9&&
3:0B/
7:
(;7B9&&
,61
27$
0$;,13
&855(17
,17&
&61
%DWWB29
&RPS
/('B2&
6723B&219/+B2))
6&.
,63
3:0&RPS
6'2
6',
5DQGRPLF
'LWKHU
&B'LVFK
6:
15(6
6/23(B$'-
/$PS
3:0B/
/+B21
*
'5,9(5
))
5
6WGE\
%DWWB29
17&
*1'
*1'
*1'
("1($'5
,61
9&&
,63
*1'
(1$%/(
56)
6&
96
Figure 2. Connection diagram (top view – not in scale)
9&&
15(6
3:0B/
*
3*1'
&9
,6(16(
,6(16(
6',
-2'1
6'2
6&.
*
&3%
9/('
&61
0287
17&
5&&203
*1'
/+0
/02'(
3:0
,13B29
(;7B9&&
("1($'5
6/69
DocID025319 Rev 3
L99LD01
Block diagram and pin description
Table 1. Pin description
1.
Pin
number
Pin name
1
VCC1
5 V internal voltage regulator 1 output (external capacitor req.)
2
NRES
Reset I/O pin; active low
3
PWM_L
4
SDI
Serial SPI data input
5
SDO
Serial SPI data output
6
SCK
SPI clock
7
CSN
Chip select not
8
MOUT
9
EXT_VCC
10
INP_OV
11
PWM
Low frequency PWM input (battery compatible)
12
LHM
Limp home mode input pin
13
LMODE
14
GND2
15
NTC
16
RCCOMP
17
VLED
Input for LED chain overvoltage detection
18
CPB
Charge pump buffer capacitor
19
G2
20
ISENSE-
Negative terminal of the LED sense resistor
21
ISENSE+
Positive terminal of the LED sense resistor
22
C5V
23
PGND
24
G1
25
VCC2
10 V voltage regulator 2 output (ext. capacitor required)
26
ISN
Negative terminal of the shunt resistor
27
ISP
Positive terminal of the shunt resistor
28
GND1
29
ENABLE
30
VS
Supply voltage input pin
31
SC
Slope compensation setting resistor
32
RSF
Oscillator frequency setting resistor
Function
Logic low frequency PWM input
Multiplexed data output pin
Internal/external up supply voltage programming pin(1)
Battery overvoltage programming pin
Switch input pin (connect to GND if LED drop voltage is referred to GND
or open (5 V) if LED drop is referred to VS)
GND of controller
Output for external N.T.C. resistor
External R C compensation network
Gate 2 output for external PMOS M2
Output for 5 V buffer capacitor
Power ground
Gate 1 output for external PMOS M1
GND of controller
Enable pin
In case of externally supplied microcontroller, attach this pin to its external supply voltage pin.
DocID025319 Rev 3
7/69
68
Functional description
L99LD01
2
Functional description
2.1
Operating modes
The device is able to work both with a microcontroller and without it (stand alone
configuration).
2.1.1
Operation with an external microcontroller
This way allows parameters to be adjusted and checked by means of the SPI interface.
The adjusted device parameters, stored, i.e., inside the micro EEPROM, can be loaded into
device internal registers after the start up phase.
By means of a small 8 pins microcontroller it is possible to implement the following
functions:
•
Parameters setting:
–
LED current level and maximum input current limit can be adjusted according to
the application, the LED characteristic and spreads
–
Dither oscillator parameters as random, frequency modulation and deviation
percentage can be programmed
•
Flexible PWM operation with duty cycle and frequency managed by the microcontroller
•
Diagnostic feedback:
–
•
Advanced LED monitoring:
–
•
8/69
Fault condition is sent to the micro when the CSN pin is pulled down
LED voltage drop and temperature are multiplexed and sent to the microcontroller
through the dedicated MOUT pin in order to monitor the selected parameter with
the A/D of the microcontroller. The multiplexer is driven through a SPI command.
This function allows a sophisticated control of the LED status. For example, as an
alternative to the default overvoltage detection, it is possible to monitor the LED
drop voltage, reduced by the external R5/R6 resistor divider. So taking into
account the spread and temperature influence on the LED voltage drop, the
microcontroller is able to detect if there is one or more LED shorted.
Furthermore, it is possible to monitor the LED chain temperature, by means of the
voltage feedback through the dedicated NTC pin. The temperature limit control,
operated by the device by default, can be disabled via the SPI and the voltage
applied on the NTC pin can be sent back to the microcontroller via the multiplexed
output, MOUT, so allowing the microcontroller itself to control the LED chain either
acting on the internal current LED register or reducing the low frequency PWM
duty cycle.
In case of VR1 over temperature, its output will be switched off, the device enters in limp
home mode and a failsafe bit will be set in the internal status register (see details in the
following paragraph). In order to restart the normal operation, so clearing the
corresponding status register bit, the VS or ENABLE voltage has to be switched off and
then on. The mentioned bit can be cleared by the microcontroller only when it is
external supplied.
DocID025319 Rev 3
L99LD01
2.1.2
Functional description
Stand alone operation
The device operates with default parameters. The overall tolerance depends on the internal
references precision and the external resistors tolerance. In details:
•
LED current via external sensing resistor:
I LED = 150 mV/R SENSE
•
Maximum input current via an external shunt resistor.
•
Oscillator dither effects are set to its default parameters; a low level on the SDI allows
disabling the function.
•
Low frequency dimming operation is allowed either by PWM pin or by logic level
PWM_L input pin. Connecting the PWM control pin to the supply voltage via a resistor
divider, allows the converter to be synchronized to the low frequency PWM generated,
i.e., from the smart junction box.
•
Connecting the MOUT pin, which by default provides a logic level image of the control
input, to the PWM_L input, it is possible to drive the LED according to the PWM
frequency and duty cycle of control. (See application circuit of Figure 38).
•
In case of VR1 over temperature, its output will be permanently switched off. The device
still continues to work in normal mode but with VR1 = OFF.
The L99LD01 can operate in 4 different modes:
•
Start-up fail
•
Normal mode
•
Software limp home
•
Limp home
After the power on reset, the device stays in start-up phase until VCC1 reaches a specified
threshold, VCC1_TH. Then the device enters in normal mode either with microcontroller or
standalone, depending on the voltage level on the Nreset pin.
Note:
The information about the operation with microcontroller or standalone is latched until a new
power on reset.
If VCC1 does not reach both VCC1 fail and VCC1_TH thresholds within a given delay or if a
VCC1 over temperature event occurs, the device enters in a corresponding state.
2.1.3
Start-up fail
The device enters this mode in case a VCC1 under voltage event occurs during start-up
phase and VS < VSMIN, provided that a microcontroller is detected. In this case VCC1 is
turned off.
If VS remains below VSMIN, then the converter is switched off.
If VS rises above VSMIN, the converter behaves according to the PWM_L pin.
DocID025319 Rev 3
9/69
68
Functional description
2.1.4
L99LD01
Normal mode
•
Normal mode with microcontroller: the device enters this mode after a successful start
up (VCC1 > VCC1_TH) and a microcontroller is detected. The device keeps this mode as
long as the watchdog is retriggered before a timeout event.
•
Normal mode in standalone configuration: the device enters this mode if a standalone
configuration is detected, independently from VCC1 errors. The L99LD01 keeps this
mode even in case of watchdog timeouts.
In both cases, the converter behaves according to the PWM_L pin.
2.1.5
Software limp home
This device enters software limp home mode in case the Lh_Sw bit is set (see Section :
Control registers 3).
The control registers are set to their default values, with the exception of the Lh_Sw bit,
which remains unchanged.
The converter behaves according to the signal on the LHM pin:
2.1.6
–
Turned on if a high signal is detected at the LHM pin
–
Turned off if a low signal is detected at the LHM pin
Limp home mode
The device enters limp home mode, if a microcontroller is detected, in the following cases:
–
Watchdog timeout in normal mode
–
VCC1 under voltage (VCC1 < VCC1_TH) for more than 2 ms in normal mode
–
VCC1 is below the VCC1_FAIL threshold for more than 4 ms during start-up
–
VCC1 is below Vcc1uv for more than 100 ms during start-up and VS is above
VSMIN threshold
–
Thermal shutdown of VCC1
–
SDI stuck at 0 or 1
In Limp Home mode, all the control registers are set to their default values, except Lh_Sw
(see Section : Control registers 3), which remains unchanged.
The converter behaves according to the voltage level on the LHM pin:
•
Turned on if a High signal is detected at the LHM pin
•
Turned off if a Low signal is detected at the LHM pin
Depending on the root cause, the action taken to quit the limp home mode (provided that the
limp home condition has disappeared) is different. Some of the recovery paths require the
microcontroller to be supplied by external supply.
A power on reset is always possible.
10/69
DocID025319 Rev 3
L99LD01
Functional description
Figure 3. Operating modes, main states
325
1RX&
6WDQGDORQH
9&&6WDUWXS
9&&2.
9&
9& &8
9
&
)D 9
LO
RU 6!
9
&& 96P
L
27 Q
/KBVZRQ
6:
/LPSKRPH
/KBVZRII :'WULJJHU
9&&27
1RUPDOPRGH
)DLOXUH
QRW27
5 & :'WULJJHU
:'WULJJHU
6WDUWXSIDLO
YFFRII
9&&89 96 96PLQ
/LPS+RPH
YFFRII
5 & :'WULJJHU
9FFVWD\VRII
UH
OX
L
ID
'
:
H
7
LY 2
XW
HF &&
V
9
Q
FR 25
G
U
/LPS+RPH
YFFRQ
5 & 5HDGDQG&OHDUVWDWXVUHJLVWHU
)DLOXUH
6',6WXFNWR+LJKRU/RZ
25ZDWFKGRJWLPHRXW
259FF 9FFBWKIRUPRUHWKDQW\SPV
("1($'5
Table 2. Limp home mode: recovery paths
Transition
Root cause
Action to get back to
normal mode
Fail Safe bit = 0
WD_Fail bit = 0
WD timeout
(1st or 2nd WD timeout)
Normal mode
Limp Home VCC1 on
VCC1 < VCC1_TH for more than
2 ms
Response in the
next SPI command
Read and clear status1
AND WD trigger
Fail Safe bit = 0
Vcc1_Uv_To bit = 0
Fail Safe bit = 0
SDI_Stuck@ = 0
SDI stuck at 0 or 1
DocID025319 Rev 3
11/69
68
Functional description
L99LD01
Table 2. Limp home mode: recovery paths (continued)
Transition
Root cause
Action to get back to
normal mode
Response in the
next SPI command
3 consecutive WD timeouts
(microcontroller is supplied by
VCC1)
Fail Safe bit = 0
Power on reset OR toggling
WD_Fail bit = 0
of EN pin
Reset bit = 1
3 consecutive WD timeouts
(microcontroller is supplied by
another VREG)
Read and clear Status1
AND WD trigger
Fail Safe bit = 0
WD_Fail bit = 0
VCC1 < VCC1_FAIL during start up
for more than 4 ms
Power on reset
Failsafe bit = 0
Vcc1_Sc bit = 0
Reset bit = 1
VCC1 < VCC1_FAIL during start up
for more than 4 ms
(microcontroller supplied by
another VREG)
Read and clear Status1
AND WD trigger OR
Toggling of EN pin
Failsafe bit = 0
Vcc1_Sc bit = 0
Vcc1_Fail = 0
VCC1 < VCC1_TH for more than
100 ms during start up AND
VS > VSMIN
Fail Safe bit = 0
Power on reset OR toggling
Vcc1_Sc bit = 0
of EN pin
Reset bit = 1
VCC1 < VCC1_TH for more than
100 ms during start up AND
VS > VSMIN (microcontroller
supplied by another VREG)
Read and clear Status1
AND WD trigger
Fail Safe bit = 0
Vcc1_Sc bit = 0
Any state except normal
mode standalone limp
home VCC1 off
VCC1 over temperature
Read and clear Status1
AND WD trigger
Fail Safe bit = 0
Vcc1_Ot bit = 0
Normal mode
SW limp home
Software limp home is activated
Reset Lh_Sw bit AND
WD trigger
Fail Safe bit = 0
Lh_Sw_St = 0
Limp home VCC1 on
limp home VCC1 off
Start up limp home
VCC1 off
The following Figure 4, Figure 5 (a), (b) and Figure 6 (a) show the behavior of the device
and NRES during start-up in case of normal VS ramp up or in case of VCC1 failures (VCC1 fail
or reset under voltage), both with microcontroller and standalone. Figure 6 (b) and Figure 7
show the behavior at VS ramp down fast and slow respectively.
12/69
DocID025319 Rev 3
L99LD01
Functional description
Figure 4. Normal start up vs VS ramp up and VCC1 voltage dips
9V >9@
960,1
3RZHURQ5HVHW
WKUHVKROG
9325
6SHFLILFDWLRQ3DUDPHWHUV
W9) )LOWHUWLPHIRU9FF)DLO
GHWHFWLRQ
9FF >9@
W9) W W55
W W55
W55 9FF5HVHW7LPHILOWHUWLPH
W W55
W W)6
W5' 5HVHWGHOD\WLPH
W)6 9FFUHVHWWLPHRXWIRUIDLO
VDIHGHWHFWLRQ
W W)6
9&&B7+
PV
W6+79$ ILOWHUWLPHEHIRUH
GHWHFWLRQRIVKRUWFLUFXLWRQ9FF
DWWXUQRQ 9FF 9FF)$,/
9&&)$,/
W6+79%
9FFBXYBWRVWDWXVVHW
$1'
/LPS+RPHPRGHDFWLYDWHGLI&RQERDUG
9FFBIDLO
VWDWXVVHW
W6+79$
15HVHW
+LJK
W W5'
W W5'
W W5'
PV
PV
PV
W6+79% ILOWHUWLPHEHIRUH
GHWHFWLRQRIVKRUWFLUFXLWRQ9FF
DWWXUQRQ 9FF)$,/
9FF 9&&B7+
9&&B7+ UHVHWLQWHUYHQWLRQ
WKUHVKROG
960,1 PLQLPXP9VUHTXLUHGIRU
UHDFKLQJ9FFQRPLQDOYROWDJH
9&&B)$,/ 9FFIDLOGHWHFWLRQ
WKUHVKROG
/RZ
&RQERDUG
6WDQGE\
6WDUWXS
6WDQGDORQH
6WDQGE\
6WDUWXS
$FWLYHPRGH
/LPS+RPHLI&
$FWLYHPRGH
("1($'5
Note:
Normal start up with or without microcontroller.
DocID025319 Rev 3
13/69
68
Functional description
L99LD01
Figure 5. VCC1_FAIL or VCC1 reset under voltage (VS > VSMIN) at start up
9V >9@
9V >9@
960,1
960,1
3RZHURQ5HVHW
WKUHVKROG
9325
3RZHURQ5HVHW
WKUHVKROG
9325
9FFBIDLOVWDWXVVHW
9FFBVFVWDWXVVHW
9FFBVFVWDWXVVHW
9FF >9@
9FF >9@
9FFBRIIVWDWXVVHW
/LPS+RPHPRGHDFWLYDWHGLI&RQERDUG
9FFBRIIVWDWXVVHW
/LPS+RPHPRGHDFWLYDWHGLI&RQERDUG
9&&B7+
9&&B7+
9&&)$,/
9&&)$,/
W W6+79$
W W6+79$
15HVHW
W W6+79%
15HVHW
+LJK
+LJK
/RZ
/RZ
&RQERDUG
6WDQGE\
6WDUWXS
/LPS+RPH
&RQERDUG
6WDQGE\
6WDUWXS
/LPS+RPH
6WDQGDORQH
6WDQGE\
6WDUWXS
$FWLYH0RGH
6WDQGDORQH
6WDQGE\
6WDUWXS
$FWLYH0RGH
B
C
B
TUBSUVQ7$$GBJM C
7 $$VOEFSSFTFUUISFTIPMEEVSJOHTUBSUVQ
7 4 7 4.*/
14/69
DocID025319 Rev 3
("1($'5
L99LD01
Functional description
Figure 6. VCC1 reset under voltage at start up (VS < VSMIN) and fast VS ramp down
9V >9@
9V >9@
9VBXYVWDWXVVHW
960,1
960,1
9V 9VPLQ
3RZHURQ5HVHWWKUHVKROG
9325
9325
9FFBVFVWDWXVVHW
9FFBRIIVWDWXVVHW
9FF >9@
9VBXYVWDWXVVHW
1R/LPS+RPHPRGHDFWLYDWHG 9V 9VPLQ
9&&B7+
9&&B7+
9&&)$,/
9&&)$,/
W W6+79$
W W55
W W6+79%aPV
15HVHW
15HVHW
+LJK
+LJK
/RZ
/RZ
&RQERDUG
6WDQGE\
6WDUWXS
6WDUWXS9FFRII
&RQERDUG
$FWLYH0RGH
6WDQGE\
6WDQGDORQH
6WDQGE\
6WDUWXS
$FWLYH0RGH
6WDQGDORQH
$FWLYH0RGH
6WDQGE\
B
C
B
7 $$@67EVSJOHTUBSUVQ C
74 7 4.*/'BTU7 4SBNQEPXO
("1($'5
DocID025319 Rev 3
15/69
68
Functional description
L99LD01
Figure 7. Slow vs ramp down
9V >9@
W W960
960,1
9325
9VBXYVWDWXVVHW
9FF >9@
W W55
9&&B7+
W W)6
PV
9&&)$,/
15HVHW
9FFBXYBWRVWDWXVUHJLVWHU
+LJK
/RZ
&RQERDUG
6WDQGDORQH
1RUPDO0RGH
/LPS+RPH
1RUPDO0RGH
6WDQGE\
6WDQGE\
("1($'5
2.2
Protections and functions
2.2.1
LED current adjust and temperature control
The LED current can be adjusted within a range of ± 66.7 %, with respect to the default
value set by the LED current sense resistor, via the SPI input, so allowing the end of line
calibration. The LED chain temperature measurement is achieved by means of an external
NTC resistor connected between the NTC pin and GND. The NTC resistor is supplied
through a resistor connected to the 5 V internal regulator output. As soon as the voltage on
the NTC resistor becomes lower than the internal threshold, VNTC_TH, (due to an
overtemperature in the LED chain) an internal circuitry is activated and the internal LED
current reference voltage decreases proportionally, so that the LED current is progressively
16/69
DocID025319 Rev 3
L99LD01
Functional description
reduced (maximum 50 % of the nominal LED current), not allowing the LED temperature to
increase over the programmed limit.
Thermal limit intervention is reported by properly setting a bit inside the internal status
register.
2.2.2
Slope compensation
Slope compensation is needed to ensure the stability of the control loop with all possible
values of duty cycle
T ON
D = ----------T
(0 < D < 1)
especially for duty cycle greater than 0.5. The recommended slope SADD of the additional
ramp is proportional to the inductor current slope during the turn off phase, that is:
S ADD = α ⋅ S L
where SADD is the additional slope introduced by the circuit,
dI L
S L = -------dt
OFF
is the off-time inductor slope and
0.5 < α < 1
SL is also given by the formula:
G LA ⋅ R SHUNT ⋅ ( V OUT – V IN )
S L = -------------------------------------------------------------------------------L
Being GLA the gain of the linear amplifier (see Chapter 5: Electrical characteristics for GLA
parameter values) and RSHUNT is the resistor across pin ISP and ISN (see Chapter 7:
Application circuits).
The simplified internal circuit structure for the slope compensation is shown in Figure 8.
The additional slope is obtained from the internal oscillator ramp voltage. A fraction of the
oscillator voltage ramp is added to the output voltage of the sensing amplifier, which is
proportional to the sense resistor voltage drop, and therefore, to the current flowing through
power mosfet M1.
The added ramp voltage is
V ADD = I ⋅ R SLOPE
where
DocID025319 Rev 3
17/69
68
Functional description
L99LD01
V OSC
I = 2 ⋅ ---------------RT
and RSLOPE and RT are defined in the Figure 8, together with their typical values.
Therefore, will result:
R SLOPE
V ADD = 2 ⋅ V OSC ⋅ ----------------------RT
and consequently:
2 ⋅ V OSC ⋅ R SLOPE
V ADD
S ADD = --------------- = --------------------------------------------------RT ⋅ T
T
where T is the period of the converter oscillator.
The additional compensating current slope can be simply adjusted by properly setting the
value of the external resistor R9 (and consequently RT).
Figure 8. Internal structure of the slope compensation circuit
,
/$PS
56/23( .
5(6
,
926&57
,63
,61
27$
,6(16(
,6(16(
3:0&RPS
.
5&&203
57
56& 56& 9
56&PLQ.2+0
926&
6&
56& 5
.
("1($'5
2.2.3
LED chain overvoltage detection
Via the external resistor divider (R5, R6) it is possible to detect LED overvoltage events, by
programming a threshold for the maximum drop voltage of the LED chain for a specific LED
board (see Section 2.2.12 for details). In case Boost or Fly back topology is used, the
LMODE pin must be connected to GND. In this case the voltage at pin VLED will be referred to
ground. Instead, if Buck Boost topology is used, the LMODE pin must be connected to 5 V or
left open. An internal pull up current source keep this pin high, and in this case, the voltage
applied by the resistor divider R5/R6 at pin VLED will be referred to the battery voltage
applied at pin VS. If a valid overvoltage event occurs, which is detected if the LED drop
voltage reaches a value VLED ≥ OV_TH1, the device is switched off immediately forcing the
18/69
DocID025319 Rev 3
L99LD01
Functional description
pins G1 and G2 to zero voltage and the event is registered in the status register of the SPI
interface and read by the micro.
In case of LED overvoltage, immediately after stopping the device, an internal resistor is
applied between pin ISENSE+ and GND trough the switch “C_disch” (see Figure 1), in order
to discharge capacitors C1 and C4, avoiding LED flashing when the converter restarts. Any
LED_OV event will be written in the GSB (Global Status Byte) bit 7 and also in the SR1
(Status Register 1) bit 18.
2.2.4
Battery overvoltage shutdown
In case supply voltage applied to the VS pin rises above a maximum voltage threshold,
sensed by a resistor divider attached at pin INP_OV, the converter is switched off
immediately, forcing outputs pin G1 and G2, to zero voltage. This prevents a LED over
current in case of load-dump.
If, following the input overvoltage event, the battery voltage decreases under a second
threshold, lower than the former, the converter starts again.
2.2.5
Regulators thermal shut down
Both voltage regulators inside the chip are provided with over temperature detection circuits.
If VR1 reaches its maximum temperature, VR1 will be switched off. After that, the behavior of
the device depends on the application (see Section 2.2.1: LED current adjust and
temperature control).
If instead, is VR2 to reach its maximum temperature (typ 175 °C), then the device will be
completely switched off (VCC1 and VCC2 = 0).
Only the internal temperature monitoring of VCC2 remains alive and when the temperature
falls down under a second lower temperature threshold (150 °C typ.), the device tries to
restart again.
2.2.6
Reset
The NRES pin (active low), generates a reset signal for the microcontroller.
An external pull up resistor (typ. 100 k) maintain normally high the voltage at pin NRES (see
Figure 32).
Following a power up condition, the NRES pin is forced low while the voltage provided by
regulator 1 (VCC1) is below an internal fixed threshold VCC1_TH of typ 4.5 V. After VCC1 has
reached the above mentioned internal threshold, NRES voltage is kept low for a fixed
default time of 2 ms; after that, the NRES pin will be released reaching the normal high
state. However, this time can be externally extended by an additional capacitance
connected between NRES and GND (see C6 in the application circuits), which is charged by
the external pull-up. Depending on the reset-input-threshold of the µP (UTR), the required
capacitance for a typical TRD can be calculated as follows:
C6 = – T RD ⁄ ( R PU ⋅ lg ( 1 – U TR ⁄ V CC1 ) )
RPU is the pull up resistor (value in ohm)
DocID025319 Rev 3
19/69
68
Functional description
L99LD01
In case VCC1 voltage drops below the internal threshold during the normal functioning, or
when the device is put in standby, the NRES pin is forced to low, but after a time interval TRR
has expired and kept low until the VCC1 has gone back again to the internal threshold (see
Figure 4 for more details).
2.2.7
Watchdog
In case the application uses a microcontroller, during the device power-up a reset pulse is
generated periodically every 200 ms (default) for 2.0 ms waiting for microcontroller
acknowledgment. Timeout window is selectable by SPI (100 ms or 200 ms) and the reset
time could be extended by the external capacitor C6.
2.2.8
•
Timeout WD is refreshed by bit toggling.
•
After the 1st WD timeout, a reset pulse is generated and the device enters in Limp
Home mode. After the second WD timeout, another reset pulse cycle is generated,
waiting for microcontroller response.
•
After 3 consecutive reset cycles without WD refresh, which means that microcontroller
is not responding, the voltage regulator, VCC1, is turned off and the device keeps
working in “Limp Home Mode” (see Figure 33). Safety critical functions like Low Beam
application require the LED Driver to be turned on if the microcontroller fails, while in
case of high beam application, it is required the driver to be switched off in case of
microcontroller failure. As a consequence, the device operates according to the state of
LHM pin which is enabled during the recognition of the microcontroller failure. In
particular, if LHM pin is kept low the device will be always OFF. If instead, LHM pin is
high or left open, the device will be switched permanently ON, regardless of the status
of PWM_L pin.If the application doesn’t use a microcontroller (stand alone operation),
the start-up WD control must to be deactivated. This can be done by connecting NRES
pin to the battery supply voltage VS. In such a case the driver will operate in normal
mode as above mentioned (see stand alone operation).
Standby and wake up by ENABLE pin
A low consumption mode is required in case of applications directly connected to the
battery.
The device enters in standby mode, that is the default operating modes because of an
internal pull down, in case of low level signal at the ENABLE pin and it wakes up in case of
high level signal.During standby mode, VCC1 and VCC2 are switched off. Figure 9 and
Figure 10 show two possible application schematics in case of direct connection to the
battery.
In case of Figure 9 the microcontroller of the application goes in standby when the
microcontroller sets the LIN transceiver in standby mode: NSLP = Low→INH goes
Low→the DRL driver goes in standby.
The application is waken up from the standby when a wake up source is detected by the LIN
transceiver. That means INH goes high and so ENABLE, then the DRL driver restarts and
consequently VCC1 is activated and supplies the microcontroller.
In case of Figure 10, a power management device is present, which supplies the
microcontroller. Normally the inverted FSO signal coming from the power management
device is high. This output is inverted by an external logic and applied to one of the two input
OR diodes and therefore, at the input of the OR the voltage is normally at logical zero.
20/69
DocID025319 Rev 3
L99LD01
Functional description
So in this case the LED driver goes:
•
In stand-by mode with a low level on ENABLE pin operated by the microcontroller
•
In normal mode with a high level on ENABLE pin operated by the microcontroller
The inverted FSO signal, coming from the power management device ensures, putting
trough the inverter and the external OR diode ENABLE pin high, that the LED driver
correctly restarts even if the microcontroller fails.
Figure 9. Operation with a standalone LIN and ENABLE
/('0RGXOH
9%$77
9
'5/
'ULYHU
16/3
&
/,1
(1$%/(
,1+
("1($'5
Figure 10. Operation with PM device and ENABLE (FSO active Low)
/('0RGXOH
9%$77
9
3RZHU
PDQDJHPHQW
'5/
'ULYHU
&
/,1
(1$%/(
)62
)62
("1($'5
1. An inverter network is required.
2.2.9
Frequency setting and dither effect
The internal main converter oscillator structure is reported in Figure 11.
DocID025319 Rev 3
21/69
68
Functional description
L99LD01
The external resistor applied between pin RSF and ground is setting the converter working
frequency. The voltage applied on pin RSF is the internal reference reported by the source
follower structure which is a constant voltage of 1.21 V. The converter frequency is directly
related to the current flowing through the RSF pin. Figure 12 reports the behavior of
frequency converter as function of the external resistor RSF and IRSF as function of
converter frequency. As above mentioned the converter oscillator spread parameters (dither
effect) are adjustable via SPI.
Dither effect is disabled by default during standalone operation, but it is possible enabling it
simply connecting the SDI pin to 5 V voltage.
Figure 11. Internal structure of main converter oscillator
,56) 56)
,F .,56)
9
2VFLOODWRU
,56)
56)
("1($'5
22/69
DocID025319 Rev 3
L99LD01
Functional description
Figure 12. Converter frequency range vs RSF and IRSF vs frequency
)UHTXHQF\YV56)
)5(4>.K]@
56)>.@
,56)YV)UHTXHQF\
,56)>X$@
,56)
)5(4
)5(4>.K]@
("1($'5
2.2.10
Start up LED overvoltage management
The following diagram shows the purpose of delay time windows “tDStart” and “tEnRecov”.
The first delay window tDStart has been thought to ensure an initial time period for charging
the external buffer capacitor of the charge pump C9. When VS is below VSMIN, the LED
overvoltage recovery bit is set. During this time interval, triggered as soon as the battery
voltage VS overcomes VSMIN threshold, the converter remain in a stop condition,
independently from PWM_L. When the tDStart is elapsed (typ. 5 ms), the converter is
released and behaves according to the PWM_L signal provided, that no failure occurs.
If no LED overvoltage comes during the 2nd time interval tEnRecov, LED ov recovery bit is
reset.
DocID025319 Rev 3
23/69
68
Functional description
L99LD01
If a LED overvoltage failure occurs afterwards, the failure will be latched and the converter is
stopped until a read and clear of the status register 1.
Note that during tDStart, the converter is stopped to enable the buffer capacitor C9 to charge
at a sufficient voltage to correctly drive the mosfet M2. This delay prevents the converter to
turn on, while M2 stays off, avoiding a LED overvoltage event.
If the application uses a big capacitor(a), it is recommended to keep the PWM_L signal low
after a power on reset or after a VS under voltage, until C9 is totally charged, to avoid a LED
overvoltage. Figure 13 shows the device behavior in case of no LED overvoltage failure,
after tDStart.
If C9, after tDStart time, should be not enough charged to allow correct driving operation, a
possible LED overvoltage will appear when, the converter will be released. Figure 14 shows
what happens in this case.
After tDStart, the converter is released while the C9 capacitor is only partially charged.
Consequently, VLED increases up to LED OV_TH1 and a LED overvoltage event is detected
during the tEnRecov phase. The LED_Ov_Rec bit is not reset at the end of the tEnRecov phase
due to the LED overvoltage event. The discharge path is activated until VLED crosses LED
OV_TH2. Then, the LED_Ov_Rec bit is reset, the converter is released, and the buffer
capacitor C9 is now fully charged, enabling the dimming mosfet M2 to turn on.
Figure 15 shows the case of LED_Ov_Rec bit during a start up with a rising edge on
PWM_L = High after the expiration of tDStart. In this case, the tEnRecov phase starts only
when the PWM_L signal goes High. Figure 16 shows the case of LED overvoltage event,
which could appear during normal functioning.
The LED overvoltage status bit is set (latched) and the discharge path is activated until VLED
crosses LED OV_TH2. The converter is stopped, independently from PWM_L, until a read
and clear command of the status register 1 (LED_Ov_Rec bit is reset).
If a LED overvoltage failure event occurs during VS overvoltage, (battery OV), the discharge
path for the output capacitor is inhibited and the LED overvoltage status bit is not set.
When the VS overvoltage event disappears, (VS crosses VS OV_TH2), the LED overvoltage
status bit is set (latched) and the discharge path is activated until VLED crosses LED
OV_TH2. The converter is stopped, independently from PWM_L, until the LED ov status bit
is cleared (read and clear of the status register 1). Figure 17 shows such a case.
Finally Figure 18 shows how will be managed the LED_Ov_Rec bit in case signal PWM_L
has a low on-time. In this case the LED_Ov_Rec bit is reset when the cumulated running
time of tEnRecov exceeds typ. 5 ms. This feature enables a single recovery of a LED
overvoltage event, due to a too fast regulation loop (set by the resistor and capacitor
connected to RCCOMP pin), even in PWM operation with low on-time. However, a proper
choice of RC network values, avoiding fast transients on the LED string voltage, when the
converter is switched ON, it is carefully recommended
a. More than 22 nF
24/69
DocID025319 Rev 3
L99LD01
Functional description
Figure 13. Correct start UP with no LED overvoltage failure
325
9V
9VBPLQ
7LPHU
W'6WDUW
aPV
W(Q5HFRY
aPV
2))
21
3:0B/
&RQYHUWHU
/('RY
UHFRYELW
6LQJOH/('RYUHFRYHU\HQDEOHG
5HFGLVDEOHG
("1($'5
Figure 14. LED overvoltage after tDStart
325
/('RYHUYROWDJHGXULQJWKH 7KHHQGRIWKHW(Q5HFRYSKDVHLVLJQRUHG
EHFDXVHGRIWKH/('RYHYHQW WKH/('RY
W(Q5HFRYSKDVH
UHFRYHU\ELWLVQRWUHVHW
9V
9VBPLQ
7LPHU
W'6WDUW
aPV
W(Q5HFRY
aPV
3:0B/
&RQYHUWHU
2))
2))
21
/('RY
UHFRYELW
/('2YBWK
/('2YBWK
2XWSXWFDS
'LVFKDUJH
("1($'5
DocID025319 Rev 3
25/69
68
Functional description
L99LD01
Figure 15. Device behavior in case the low to high transition of PWM_L signal
happens after tDStart expiration
325
9V
9VBPLQ
7LPHU
W'6WDUW
aPV
:DLWLQJIRU
3:0B/ULVLQJ
W(Q5HFRY
aPV
3:0B/
&RQYHUWHU
2))
/('2Y
UHFRYELW
21
6LQJOH/('RYUHFRYHU\HQDEOHG
/('RYUHFRYHU\GLVDEOHG
("1($'5
Figure 16. LED overvoltage event not caused by a VS overvoltage event
9V
9V2YBWK
9VPLQ
9/('
/('2YBWK
/('2YBWK
&RQYHUWHU
21
2XWSXWFDS
'LVFKDUJH
2))
2))
21
21
2))
/('RY
VWDWXVELW
5HDGDQG&OHDU
6WDWXV5HJ
("1($'5
26/69
DocID025319 Rev 3
L99LD01
Functional description
Figure 17. LED overvoltage detection due to a possible battery VS overvoltage
9V
9V2YBWK
9V2YBWK
9/('
/('2YBWK
/('2YBWK
&RQYHUWHU
2))
21
'LVFKDUJH
21
2))
2))
/('RY
VWDWXVELW
5HDGDQG&OHDU
6WDWXV5HJ
("1($'5
Figure 18. Behavior of LED overvoltage recovery bit with low on-time of PWM_L
325
([SLUDWLRQRIW(Q5HFRY
FXPXODWHGUXQQLQJWLPHaPV
([SLUDWLRQRIW'VWDUW
9V
9VBPLQ
7LPHU
W'6WDUW
aPV
:DLW
3:0/
5LVLQJ
W(Q5HFRY W(Q5HFRY W(Q5HFRY W(Q5HFRY W(Q5HFRY W(Q5HFRY W(Q5HFRY
5XQQLQJ
5XQQLQJ
5XQQLQJ
5XQQLQJ
+DOW
+DOW
+DOW
3:0B/
&RQYHUWHU
/('RY
UHFRYELW
21
2))
6LQJOH/('RYUHFRYHU\HQDEOHG
5HFRYHU\GLVDEOHG
("1($'5
2.2.11
Programming the over/under voltage threshold
The voltage across the LED string is continuously sensed by the external resistor divider
R5/R6 and reported inside the chip trough the apposite pin VLED. Considering negligible the
voltage drop due to the sense resistor and the VDS of external mosfet M2 respect to the LED
DocID025319 Rev 3
27/69
68
Functional description
L99LD01
voltage string, according to the equation reported below, the LED overvoltage thresholds
are given by the following formulas:
VLED_OV = OV_TH1 / KL; being KL = R6 / (R5+R6);
OV_TH1 is the reference for the OV internal comparator. Typical value for OV_TH1 is 3.5 V.
LED OV event makes the converter and also mosfet M2 immediately switched OFF, in order
to prevent any damage to the LED string or to the driver. Furthermore, following an OV
event, the LED_OV status register is set and an internal load is applied between ISENSE+ pin
and ground in order to fast discharge the voltage across capacitor C4.
In the boost topology application, if a short circuit between the source of external mosfet M2
and GND occurs, an uncontrolled current could flow. In order to avoid this situation, a
maximum LED current protection has been inserted, which continuously monitors the
voltage across the sense resistor RSENSE. If this voltage reaches a value in excess of an
internal fixed threshold of (see Table 24 - LED over current protection threshold parameter),
the status bit LED_OC (led over current) is set and the converter and also mosfet M2 will be
immediately switched OFF.
Following a stop of the converter due to an OV event, the device can not be restarted before
of C4 discharge (VLED is below OV_TH2).
After an OV event, the converter could restart if a read and clear command of the LED_OV
status bit is done. Table 3 summarizes the suggested value of KL resistor ratio, supposing to
have a LED_OV event, when the voltage across LED string, reaches a value in excess of
50 % of its nominal value.
Figure 19. LED chain overvoltage thresholds settings. An example for boost and fly
back converters
9%$77
&
29B&203
29
29B7+
56(16(
0
0
9/('
9/('675,1*
5
9/(' §./
9/('675,1*
1
9/('B29 29B7+./
5
./ 5 55
("1($'5
28/69
DocID025319 Rev 3
L99LD01
Functional description
Table 3. Suggested KL value and overvoltage thresholds
N
KL
LED CHAIN nominal
DROP N*VF [V]
overvoltage VLED_OV [V]
1(1)
0.583
4
6
2(1)
0.292
8
12
3(1)
0.194
12
18
4(1)
0.146
16
24
5
0.117
20
30
6
0.097
24
36
7
0.083
28
42
8
0.073
32
48
9
0.065
36
54(2)
10
0.0583
40
60(2)
Number of LED
1. Not Applicable on boost converter topology, since the chain LED Drop must be always larger as the maximum battery
voltage.
2. Theoretical value; effective value will be clamped to 52 V (typ) by the OV protection.
2.2.12
Input overvoltage programming
Supply overvoltage is programmed by the external partition ratio KI = R3/R4
According to the Figure 20 input overvoltage thresholds depend on the internal reference
voltages VOVTH1 and VOVTH2 (being VOVTH2 < VOVTH1)
Typical values of these internally generated references are 3.5 V and 3 V.
When the Battery voltage reaches a value in excess to VS_TH1 the converter is immediately
stopped. When the battery voltage, going down, reaches a value just lower to VS_TH2, the
converter restarts again.
Figure 20. Input overvoltage programming
9%$77
96
&
5
,13B29
5
9297+
96B7+ 55
9297+
96B7+ 55
9297+
("1($'5
DocID025319 Rev 3
29/69
68
Functional description
L99LD01
As an example, if we want VS_TH1 = 20 V, according to the formula of Figure 20, R3/R4 will
result equal to 4.7 and consequently the deactivation threshold VS_TH2 will result ~ 17 V.(b)
b. Notice that the deactivation threshold must be always greater than the maximum allowed battery value in
normal conditions.
30/69
DocID025319 Rev 3
L99LD01
SPI functional description
3
SPI functional description
3.1
Serial peripheral interface (ST SPI standard)
The SPI communication is based on a standard ST-SPI 24-bit interface, using CSN, SDI,
SDO and SCK signal lines.
Input data are shifted into SDI, MSB first while output data are shifted out on SDO, MSB
first.
During active mode, the SPI:
Note:
•
Triggers the watchdog
•
Controls the modes and status of all internal modules (incl. input and output drivers)
•
Provides driver output diagnostic
•
Provides device diagnostic (incl. over temperature warning, device operation status)
During standby modes, the SPI is generally deactivated.
The SPI can be driven by a microcontroller with its SPI peripheral running in following mode:
Figure 21. Clock polarity and clock phase
&32/&3+$
&61
6&.
06%
6',
6'2
+,
06%
/6%
/6%
+,
*$3*&)7
According to the standard, a generic input bit is sampled by the low to high transition of the
clock CLK and a generic output bit changes synchronously to the high to low transition of
CLK.
This device is not limited to micro controller through a built-in SPI. Only three CMOScompatible output pins and one input pin will be needed to communicate with the device. A
fault condition can be detected by setting CSN low. If CSN = 0, the DO pin will reflect the
global error flag (fault condition) of the device (see Figure 22). This operation does not
cause a communication error bit in the global status byte to be set.
DocID025319 Rev 3
31/69
68
SPI functional description
L99LD01
Figure 22. SPI global error information output
& 6 1 KLJ K WR OR Z D Q G &/ . V WD\V OR Z VWDWXV LQIRU PDWLR Q RI G DWD ELW ID XOW F R Q GLWLR Q LV WUD QV IHUH G WR ' 2
&61
WLP H
&/.
WLP H
',
WLP H
', G DWD LV Q RW DFF H SWH G
'2
WLP H
' 2 VWDWXV LQIRU P DWLRQ RI GDWD ELW IDXOW F R QGLWLR Q ZLOO VWD\ DV OR QJ DV & 6 1 LV OR Z
$*9
3.2
Signal description
•
Serial Clock (SCK): this input signal provides the timing of the serial interface. Data
present at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK).
Data on Serial Data Out (SDO) is shifted out at the falling edge of Serial Clock (SCK).
•
Serial Data Input (SDI): This input is used to transfer data serially into the device. It
receives the data to be written. Values are latched on the rising edge of Serial Clock
(SCK).
•
Serial Data Output (SDO): this output signal is used to transfer data serially out of the
device. Data is shifted out on the falling edge of Serial Clock (SCK). SDO also reflects
the status of the (Bit 7 of the ) while CSN
is low and no clock signal is present
•
Chip Select Not (CSN): when this input signal is High, the device is deselected and
Serial Data Output (SDO) is high impedance. Driving this input Low enables the
communication. The communication must start and stop on a Low level of Serial Clock
(SCK).
3.3
SPI protocol
3.3.1
SDI, SDO format
SDI format during each communication frame starts with a command byte.
It begins with two bits of operating code (OC0, OC1) which specify the type of operation
(read, write, read and clear status, read device information) and is followed by a 6 bit
address (A0:A5). The command byte is followed by an input data byte (D0:D15).
32/69
DocID025319 Rev 3
L99LD01
SPI functional description
At the beginning of each communication the master device read the contents of the register (ROM address 3Eh) of the slave device. This 8 bit register indicates the
SPI frame length (24 bit) and the availability of additional features.
Each communication frame consists of a command byte which is followed by 2 data bytes.
The data returned on SDO within the same frame always starts with the . It provides general status information about the device. It is followed by 2 data bytes
(i.e. "in-frame-response").
For write cycles the is followed by the previous content of the
addressed register.
Table 4. Command byte (8 bit)
Bit
23
22
21
20
19
18
17
16
Name
OC1
OC0
A5
A4
A3
A2
A1
A0
Table 5. Input data byte
Data Byte 1
Data Byte 0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDO format during each communication frame starts with a specific byte called Global
Status Byte (see Section 3.3.2). This byte is followed by two output data byte (D0:D7,
D8:D15).
Table 6. Global status byte
Bit
23
22
21
20
Name
GEF
Comm_Err
Not (chip reset or
Comm_Error)
19
18
LED overload Temp. warning Overvoltage
17
16
VCC1
Fail safe
Error
Table 7. Output data byte
Data Byte 1
Bit
15
Name D15
3.3.2
Data Byte 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Global status byte description
The data shifted out on SDO during each communication starts with a specific byte called
Global Status Byte. This one is used to inform the microcontroller about global faults which
can be happened on the channel part (like thermal warning, OVL,...) or on the SPI interface
(like communication error,...). This specific register has the following format.
DocID025319 Rev 3
33/69
68
SPI functional description
L99LD01
Table 8. Global status byte
Bit
Name
Description
23
Global Error
Flag (GEF)
This bit is an OR combination of the remaining bits of the register OR (Vs_uv) OR
(Lmode_err)
22
Comm_Err
The right number of SPI clocks within any valid spi command is 24.
If not, then this bit is set to ‘1’.
This bit goes to ‘0’ automatically after any valid spi command
21
Not (Chip reset
OR Comm Err)
After a POR phase this bit is active (‘0’).
It becomes inactive (‘1’) after the first valid spi command,
provided that any communication error occurs.
20
LED Overload
This bit is set when an LED overcurrent event is detected
19
Temp. warning
Temperature Warning for the LED
18
Overvoltage
LED chain overvoltage or Vs overvoltage via INP_OV
(Led_Ov OR Vs_Overvoltage)
17
VCC1 Error
This bit is an OR combination of all the errors related to VCC1
16
Fail Safe
This bit is set if the device is in a limp home mode
(Data In stuck at ‘0’ or ‘1’, watchdog time out, software limp home), VCC1 undervoltage for
more than 2 ms in active mode.
3.3.3
Operating code definition
The SPI interface features four different addressing modes which are listed in Table 10.
Table 9. Operation code definition
OC1
OC0
Meaning
0
0
Write operation
0
1
Read operation
1
0
Read and clear status operation
1
1
Read device information
The and operations allow access to the RAM of the device.
A operation is used to read a status register and subsequently
clears its content.
The allows access to the ROM area which contains device
related information such as , , and .
Write mode
The write mode of the device allows writing the content of the input data byte into the
addressed register. Incoming data are sampled on the rising edge of the serial clock (SCK),
MSB first.
34/69
DocID025319 Rev 3
L99LD01
SPI functional description
During the same sequence outgoing data are shifted out MSB first on the falling edge of the
CSN pin and subsequent bits on the falling edge of the serial clock (SCK). The first byte
corresponds to the Global Status Byte and the second to the previous content of the
addressed register.
Figure 23. SPI write operation
CSN
SDI
SDO
Data
(8 bit)
Command Byte
0
0
MSB
Address
Global Status Byte
(8 bit)
MSB
LSB MSB
LSB MSB
LSB
Data
(previous content of register)
LSB
Read mode
The read mode of the device allows to read and to check the state of any register. Incoming
data are sampled on the rising edge of the serial clock (SCK), MSB first. Outgoing data are
shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the
serial clock (SCK). The first byte corresponds to the Global Status Byte and the second to
the content of the addressed register. In case of a read mode on an unused address, the
‘global status/error’ byte on the SDO pin is following by 00H byte.
In order to avoid inconsistency between the Global status byte and the status register, the
status register contents are frozen during SPI communication.
Figure 24. SPI read operation
CSN
SDI
SDO
Don’t care
(8 bit)
Command Byte
0
MSB
1
MSB
Address
Global Status Byte
(8 bit)
LSB MSB
LSB MSB
LSB
Data
(8 bit)
LSB
Read and clear status command
The read and clear status operation is used to clear the content of the addressed status
register (see Section : Status registers 1). A read and clear status operation with address
DocID025319 Rev 3
35/69
68
SPI functional description
L99LD01
3Fh clears all status registers simultaneously and reads back the configuration register
(GLOBCTR).
Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The
command byte allows to determine which register content is read then erased while the data
byte is ‘don’t care’.
Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the
falling edge of the serial clock (SCK). The first byte corresponds to the Global Status byte
and the second to the content of the addressed register.
In order to avoid inconsistency between the Global status byte and the status register, the
status register contents are frozen during SPI communication.
Figure 25. SPI read and clear operation
CSN
SDI
SDO
Don’t care
(8 bit)
Command Byte
1
MSB
0
MSB
Address
Global Status Byte
(8 bit)
LSB MSB
LSB MSB
LSB
Data
(8 bit)
LSB
Read device information
Specific information can be read but not modified during this mode.
Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The
command byte allows to determine which information is read while the data byte is ‘don’t
care’.
Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the
falling edge of the serial clock (SCK). The first byte corresponds to the Global Status byte
and the second to the content of the addressed register.
36/69
DocID025319 Rev 3
L99LD01
SPI functional description
Figure 26. SPI read device information
CSN
1
SDO
3.4
MSB
1
MSB
LSB MSB
Address
Global Status Byte
(8 bit)
LSB MSB
LSB
Data
(8 bit)
LSB
Address mapping
T
Address
Don’t care
(8 bit)
Command Byte
SDI
Table 10. RAM memory map
Name
Access
Content
00h
Reserved
Read/write
Reserved
01h
Control register 1
Read/write
Mux settings, WD period and retrigger
02h
Control register 2
Read/write
Spread spectrum settings, max input current and LED current
settings
03h
Control register 3
Read/write
SW Limp Home, OTA/driver and converter delay control
04h
Status register 1
Read
Detailed status information
05h
Status register 2
Read
WD status, operation mode and LMode error
3E
Trimming and test
Read
Trimming bus and test mode select
3F
Configuration reg.
Read/write
WD retrigger bit
Table 11. ROM memory map
Address
Name
Access
Content
00h
ID header
Read only
4300h (ASSP ST_SPI)
01h
Version
Read only
0100h
02h
Product code 1
Read only
3100h (dec. 49)
03h
Product code 2
Read only
5100h (ASCII ‘Q’)
3Eh
SPI frame ID
Read only
4200h (Watchdog available, 24 bit ST-SPI)
DocID025319 Rev 3
37/69
68
SPI functional description
3.5
L99LD01
Control registers (RAM)
13
12
11
10
9
8
7
Reserved
Address:
0x01h
Type:
R/W
Reset:
0000 0000 0000 1110b
6
4
3
2
1
0
Mux[[1:0]
En_Ntc
WD_trig
14
WD_Period
15
Mux_En
Control registers 1
5
Bit [6:15] Reserved
Bit [5:4] Mux[1:0]:
00 (default): the signal on the PWM pin is reflected on Mout pin
01: the signal on the VLED is reflected on Mout pin
10: the signal on NTC is selected
11: the signal on Lmode pin is selected
Bit [3] Mux_En:
0: the Mout pin is inactive (tristate)
1: the Mout pin is active (default)
Bit [2] En_Ntc:
When set, the current fold back feature enabled in case of LED overtemperature
conditions.
This bit is ignored in case of any LIMP MODE and the LED temperature monitoring is
activated (the NTC control is internal)
Bit [1] WD_Period:
0: WD timeout = 100 ms
1: WD timeout = 200 ms (default)
Bit [0] WD_trig:
This bit must be toggled within the WD period to refresh the WD
38/69
DocID025319 Rev 3
L99LD01
SPI functional description
Control registers 2
15
14
Fdev[2:0]
13
12
11
Fmod[1:0]
10
9
8
Dith_En
7
6
5
4
Led_Curr[4:0]
Address:
0x02h
Type:
R/W
Reset:
0101 1110 0001 1111b
3
2
1
0
Max_Curr[4:0]
Bit [15:13] Fdev[2:0]: frequency deviation of the internal oscillator (see Table 12)
Bit [12:11] Fmod[1:0]: frequency modulation of the internal oscillator (see Table 13)
Bit [10] Dith_En: enable or disable random dither effect.
If this bit is set Dithering is enabled;
If the bit is reset, the dithering is disabled
Bit [9:5] Led_Curr[4:0]: these bits set the LED current.
The LED current is given by:
0.05 + (0.2 * Led_Curr[4:0]d) / 31) / (RSENSE) [A] (typ)
Where Led_Curr[4:0]d = decimal value of Led_Curr[4:0]
Bit [4:0] Max_Curr[4:0]: these bits set the maximum input current.
The internal current limiter voltage threshold is:
1 + (2.5 * Max_Curr[4:0]d) / 31 in [V] (typ)
Considering the gain of the amplifier of 10, the current limitation is:
(1 + 2.5 * Max_Curr[4:0]d / 31) / (10 RSHUNT) (typ);
Where Max _Curr[4:0]d = decimal value of Max_Curr[4:0]
Table 12. Internal oscillator frequency deviation settings
Fdev[2]
Fdev[1]
Fdev[0]
Frequency deviation
0
0
0
0%
0
0
1
5%
0
1
0
10 %
0
1
1
15 %
1
0
0
20 %
1
0
1
25 %
1
1
0
30 %
Table 13. Internal oscillator frequency modulation settings
Fmod[1]
Fmod[0]
Frequency modulation
0
0
1.95 kHz
0
1
3.9 kHz
1
0
7.8 kHz
1
1
15.6 kHz
DocID025319 Rev 3
39/69
68
SPI functional description
L99LD01
Control registers 3
15
14
Reserved
13
12
Lh_Sw
11
10
9
8
Ctrl_Ota[3:0]
Address:
0x03h
Type:
R/W
Reset:
0000 1000 0000 0000b
7
6
5
4
3
2
1
0
Ctrl_Drv[3:0]
Bit [15:13] Reserved
Bit [12] Lh_Sw:
The device goes in Limp Home mode without WD supervision (VCC1 stays on) when
the bit is set
Bit [11:8] Ctrl_Ota[3:0]: these bits set the delay between a rising edge of the PWM_L signal and
a connection of the output of the operation transconductance amplifier.
The delay is given by Ctrl_Ota[3:0]d * 3.3 µs (typ.)
Where Ctrl_Ota[3:0]d is the decimal value of Ctrl_Ota[3:0]
The default of these bits are loaded from the corresponding control bus
Bit [7:4] Ctrl_Drv[3:0]: these bits set the delay between a rising edge of the PWM_L signal and
the activation of the converter
The delay is given by:
Ctrl_Drv[3:0]d * 1.67 µs (typ.)
Where Ctrl_Drv[3:0]d is the decimal value of Ctrl_Drv[3:0]
The default of these bits are loaded from the corresponding control bus
Bit [3:0] Ctrl_Sw[3]: these bits set the delay between the falling edge of the PWM_L signal and
the turn off of the dimming mosfet M2.
The delay is given by:
Ctrl_Sw[3:0]d * 1.67 µs (typ.)
Where Ctrl_Sw[3:0]d is the decimal value of Ctrl_Sw[3:0]
The default of these bits are loaded from the corresponding control bus.
40/69
DocID025319 Rev 3
L99LD01
3.6
SPI functional description
Status registers
8
Reserved
Vs_Ov
Vs_Uv
—
R(1)
R
R(1)
7
Led_Oc Led_Ov
6
5
4
3
2
1
0
SDI_stuck@
9
Vcc1_Sc
10
Vcc1_Ot
11
Vcc1_Uv_To
13
Vcc1_Fail
14
Vcc1_Off
12
Led_Temp_War
15
Lmode_Err
Status registers 1
WD_fail
R/C(2)
R
R/C(2)
1. “Read only”, real time bit.
2. These bits are latched until a “Read and Clear” access.
Address:
0x04h
Type:
R/C
Bit [15:13] Reserved
Bit [12] Lmode_Err: this bit is set if a mismatch between the signal on LMODE pin and VLED
pin is detected.
Bit [11] Vs_Ov: is set if an overvoltage event at the supply line is detected
Bit [10] Vs_Uv: is set if an under voltage event at the supply line is detected
Bit [9] Led_Temp_Warn: temperature warning for the LED
Bit [8] Led_Oc: Is set if an over current event across the LED chain is detected
Bit [7] Led_Ov: is set if an overvoltage event across the LED chain is detected
Bit [6] Vcc1_Off: when set, this bit indicated that VCC1 is off
Bit [5] Vcc1_Fail
Indicates that:
VCC1 is below VCC1_FAIL threshold for typ. 2 µs in active mode
VCC1 is below VCC1_FAIL threshold for more than 4 ms typ. during start up
Bit [4] Vcc1_Uv_To: this bit is set in active mode if VCC1 is below the reset threshold for more
than typ. 2 ms
Bit [3] Vcc1_Ot: set if an overtemperature condition has been detected on VCC1
Bit [2] Vcc1_Sc: indicates a short circuit on VCC1.
This bit is set if VCC1 stays below the VCC1_FAIL threshold 4 ms (typ.) after the power
on reset or below the reset threshold 100 ms after the POR (Power On Reset)
Bit [1] SDI_stuck@
Bit [0] WD_fail
DocID025319 Rev 3
41/69
68
SPI functional description
L99LD01
8
7
6
5
4
3
Reserved
PWM_L
Standalone
LHM
Lh_Sw_St
14
Ext_Vcc
15
Led_Ov_Rec
Status registers 2
13
12
11
10
9
WD_Status[2:0]
—
R
R
R(1)
R
R(2)
R(1)
2
1
0
1. “Read only”, real time bit.
2. “Read only” bit. These bits are cleared by a WD re-trigger.
Address:
0x05h
Type:
R
Bit [15:9] Reserved
Bit [8] Led_Ov_Rec
Once this bit is set, the device will make a single trial to recover from an LED
overvoltage.
Bit [7] Ext_Vcc: this bit reflects the signal on the Ext_Vcc pin,
Bit [6] PWM_L: this bit reflects the signal on the PWM_L pin
Bit [5] Standalone: this bit is set if the device operates in standalone mode, without
microcontroller
Bit [4] LHM: reflects the level at LHM pin
Bit [3] Lh_Sw_St: is set if the software limp home mode is activated
Bit [2:0] WD_status[2:0]: these bits indicate the status of the watchdog timer (see Table 14 and
see Figure 27)
Table 14. Watchdog timer status
42/69
WD_Status[1]
WD_Status[1]
WD_Status[0]
WD timer status
0
0
0
[0…25 %[
0
0
1
[25 % … 50 %[
0
1
1
[50 % … 75 %[
1
1
1
[75 % … 100 %[
DocID025319 Rev 3
L99LD01
SPI functional description
Figure 27. Principle of the WD_Status bits
:'5HIUHVK
:'5HIUHVK
:'7LPHU
7LPHRXW
:'6WDWXV> @
("1($'5
Trimming and test register
15
14
13
12
11
10
9
8
7
6
5
4
TM[5:0]
Trim_Bus[9:0]
R/W
R
Address:
0x3Eh
Type:
R/W
Reset:
0000 0000 0000 0000b
3
2
1
0
Bit [15:10] TM[5:0]: test mode selection (refer to the UQ49 test controller)
Bit [9:0] Trim_Bus[9:0]: copy of the data stored in the trimming fuse cells
Configuration register
15
14
13
12
11
10
9
Address:
0x3Fh
Type:
R/W
Reset:
0000 0000 0000 0000b
8
7
6
5
4
3
2
1
0
Reserved
WD_Trig
—
R/W
Bit [15:1] Reserved
Bit [0] WD_Trig: this bit must be toggled within the WD period to refresh the WD.
Note that this bit is copied in the Control register 1, bit 0
DocID025319 Rev 3
43/69
68
Electrical specifications
4
L99LD01
Electrical specifications
Figure 28. Voltage and current conventions
956)
,&203
,56)
,&9
9&9
9&203
,6&
96&
,&&
9&&
9&&
,96
,&&
9&&
&9 56) 5&&203 6& 9&&
96
,15(6
915(6
,*
,3:0B/
93:0B/
,6',
96',
,6'2
96'2
15(6
3:0B/
*
,63
6',
,61
,&61
9&61
,0287
90287
93:0
9,13B29
,(1$%/(
9(1$%/(
,/+0
9/+0
,61
961
,6(16(
6&.
,6(16(
,6(16(
&61
*
/02'(
3:0
,,13B29
963
,6(16(
0287
,3:0
9*
,63
6'2
,6&.
96&.
96
(;7B9&&
9/('
,13B29
(1$%/(
&3%
/+0
17&
*1'
,*1'
*1'
96(16(
96(16(
,*
9*
,/02'(
9/02'(
,(;79&&
9(;79&
,9/('
,&3%
&
9/('
9&3%
,17&
917&
*1'
,*1'
,*1'
("1($'5
4.1
Absolute maximum ratings
Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.
Table 15. Absolute maximum ratings
Symbol
VS
VS_TR
Parameter
Value
Unit
DC operating supply voltage
5.6 / 24
V
Transient operating supply voltage (T < 400 ms)
-0.3 / 40
V
VSDI
SPI data input voltage range
-0.3 / +5.3
V
VSDO
SPI data output voltage range
-0.3 / +5.3
V
VSCK
SPI clock voltage range
-0.3 / +5.3
V
VCSN
SPI chip select not voltage range
-0.3 /+5.3
V
VNRES
Reset output pin voltage range
-0.3 ÷ VS+0.3
V
VCC1
Regulator1 supply voltage output
-0.3 / + 5.5
V
VCC2
Regulator 2 supply voltage output
-0.3 / + 10.5
V
-0.3 ÷ VS+0.3
V
VENABLE
44/69
Enable input pin voltage range
DocID025319 Rev 3
L99LD01
Electrical specifications
Table 15. Absolute maximum ratings (continued)
Symbol
Parameter
Value
Unit
VSC
Slope compensation input voltage range
-0.3 / + 5.3
V
VLHM
Limp home mode input pin voltage range
-0.3 ÷ VS+0.3
V
VPWM
Input L.F. PWM voltage range
-0.3 ÷ VS+0.3
V
VPWM_L
Logic level L.F. PWM input voltage range
-0.3 / +5.3
V
VMOUT
Multiplexed data output pin voltage range
-0.3 / +5.3
V
-0.3 / (VCC2 + 0.3)
V
-0.3 /
min (VCPB + 0.3, 68)
V
-0.3 / 5.3
V
VISENSE+ - 0.8 V /
min (VISENSE+ + 16 V, 68 V)
V
VG1
Driver 1 output voltage range
VG2
Driver 2 gate output voltage range
VEXT_VCC
VCPB
External VCC voltage range
External capacitor voltage range
VISENSE+
Positive sensing res. voltage range
-0.3 / 55
V
VISENSE-
Negative sensing res. voltage range
VISENSE+ - 5 V /
VISENSE+ + 0.3 V
V
VSP
Sensing positive shunt res voltage range
-0.3 / +5.3
V
VSN
Sensing negative shunt res voltage range
-0.3 / +5.3
V
-0.3 ÷ VS+0.3
V
VINP_OV
overvoltage input pin voltage range
VRSF
External set frequency resistor voltage range
-0.3 / 5.5
V
VC5V
C5V ext capacitor voltage range
-0.3 / 5.5
V
External RC network input pin voltage range
-0.3 / 5.5
V
VNTC
External NTC resistor input voltage range
-0.3 / 5.5
V
VLED
LED chain drop voltage detection input range
-0.3 / + 65
V
LED Mode switch voltage range
-0.3 / +5.3
V
VRC COMP
VLMODE
VESD
Electrostatic discharge (HBM R = 1.5 kΩ; C = 100 pF)
±2
kV
VESD
CDM model all pin
500
V
VESD
CDM for corner pin
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Value
Unit
Tj
Tstg
Table 16. Thermal data
Symbol
Parameter
RThj-case
Thermal resistance junction to case
27
°C/W
RThj-amb
Thermal resistance junction to ambient
90
°C/W
DocID025319 Rev 3
45/69
68
Electrical characteristics
5
L99LD01
Electrical characteristics
Values specified in this section are for 5.6 V ≤ VS ≤ 24 V; -40 °C ≤ Tj ≤ 150 °C, unless
otherwise specified
Table 17. VS and VCC1 pin characteristics
Symbol
Parameter
Test condition
Min
Typ
Unit
24
V
VS
Operative battery voltage
IS
Supply current consumption in
continuous mode (L.F.
PWM = 100 %)
VS = 13.5 V; FREQ = 300 kHz;
ICC1 = ICC2 = IC5V = 0
20
mA
IS_STBY
Supply current consumption in
stand by mode
Enable = Low; LHM,CSN,PWM,
INP_OV = open; VNRES ≤ 5.5 V;
VS = 13.5 V; Tj = 25 ºC
12
µA
Minimum VS required for
reaching VCC1 nominal value
VS ramp up
5.6
V
VSMIN hysteresis
VS ramp down
VSMIN
VSMIN_HYS
5.6
Max
4.8
5.2
0.2
V
tVSM
VSMIN filtering time
13
16
23
µs
VCC1
D.C. logic supply output voltage 1 < -ICC1 < 10 mA
4.9
5
5.1
V
-ICC1
Output current capability
VS = 13.5 V; VCC1 = VCC1_1mA 0.1 V(1)
VCC1_DROP
Min voltage drop of VCC1
respect to VS:
VCC1_DROP = min (VS - VCC1)
-ICC1 = 10 mA
VCC1_LINE
Line regulation voltage
VCC1_LOAD
Load regulation voltage
VCC1_FAIL
VCC1 fail detection threshold(2)
tLMODERR
50
mA
500
mV
-ICC1 = 10 mA;
VCC1@5.6 – VCC1@24
5
mV
-ICC1 = 1 to 10 mA; VS = 13.5 V
10
mV
VS ≥VSMIN; VCC1 rising
2.4
2.6
2.8
V
VS ≥VSMIN; VCC1 falling
1.9
2.1
2.3
V
Filtering time for LMODE error
13
16
23
µs
tOC
Filtering time for LED
overcurrent
13
16
23
µs
tLEDOV
Filtering time for LED
overvoltage
12
15
22
µs
tWD1
1st watchdog time-out period
85
100
135
ms
tWD2
2nd watchdog time-out period
170
200
275
ms
tV1F
Internal filtering time for vcc1 fail
VS ≥ VSMIN
detection
1.7
2
2.75
µs
tSHTV1A
Time to detect a short on V1
regulator at turn-on
VS ≥ VSMIN; VCC1 < VCC1_FAIL;
t ≥ tSHTV1A
tSHTV1B
Time to detect a short on V1
regulator at turn-on
VS ≥ VSMIN;
VCC1_FAIL ≤ VCC1 ≤ VCC1_TH;
t ≥ tSHTV1B
46/69
DocID025319 Rev 3
4
ms
100
ms
L99LD01
Electrical characteristics
Table 17. VS and VCC1 pin characteristics (continued)
Symbol
CVCC1
VCC1_OT
VCC1_OT_HYS
tV1OT
Parameter
Test condition
Min
Typ
1
10
Regulator 1 over temperature
detection level
150
175
190
°C
Hysteresis
20
25
30
°C
0.75
1
1.55
ms
A good quality (Low ESR)
capacitor is recommended
Load capacitance
Filtering time for regulator 1
over temperature detection
1.
VCC1_1mA is VCC1 at ILOAD = 1 mA; VS = 13.5 V.
2.
Minimum VCC1 voltage for keep RAM data.
Max
Unit
µF
Table 18. VCC2 and C5V pin characteristics
Symbol
Parameter
VCC2
D.C. logic supply output voltage
-ICC2
VCC2_DROP
-ICC2_SHT
CVCC2
VCC2_OT
VCC2_OT_HYS
VC5V
-IC5V
-IC5V_SHT
C5V
1.
Test condition
Min
Typ
Max
Units
1 ≤ -ICC2 ≤ 10 mA;
VS = 13.5 V; VPWM_L = 0
9.5
10
10.5
V
Output current capability
VS = 13.5 V;
VCC2 = VCC2_1mA - 0.1 V(1);
VPWM_L = 0
20
Drop voltage to VS:
VCC2_DROP = (VS - VCC2)
-ICC2 = 1 mA; VCC2 = 9.5 V;
VPWM_L = 0
100
mV
Short output current limitation
0 ≤ VCC2 ≤ VCC2_1mA;
VS = 13.5 V; VPWM_L = 0
100
mA
Load capacitance
A good quality (Low ESR)
capacitor is recommended for
correct managing gate peaks
current during switching On
and OFF of G1
mA
10
µF
Regulator 2 over temperature
detection level
150
175
190
°C
Over temperature detection level
hysteresis
20
25
30
°C
4.75
5
5.25
V
0 ≤ -IC5V ≤ 2.5 mA
Internal 5 V output voltage
(2)
5 V output current
VC5V = VC5V_1mA
- 0.1
Short output current limitation
0 ≤ VC5V ≤ VC5V_1mA(3)
(pulsed s.c. no continuous short)
Load capacitance See Figure 34
2.5
mA
50
1
mA
µF
VCC2_1mA is the value of VCC2 at I load = 1 mA, VS = 13.5 V; Tj = 25 °C.
2.
VC5V_1mA is the value of VC5V at external IC5V load = 1 mA, VS = 13.5 V; Tj = 25 °C.
3.
VC5V_1mA is the value of VC5V at external IC5V load = 1 mA, VS = 13.5 V; Tj = 25 °C.
DocID025319 Rev 3
47/69
68
Electrical characteristics
L99LD01
Table 19. NRES and LMODE pin characteristics
Symbol
Parameter
Test condition
Reset intervention threshold
VCC1_TH
Min
Typ
Max
Unit
4.6
4.7
4.8
V
TRR
VCC1 reset filtering time
VCC1 < VCC1_TH
13
16
23
µs
tFS
VCC1 reset time-out for fail safe
detection
VS ≥ VSMIN;
VCC1 < VCC1_TH; t ≥ tFS
1.6
2
2.9
ms
TRD
Reset delay time
VCC1 ≥ VCC1_TH
1.6
2
2.9
ms
INRES
High state reset sink current
VNRES = VS; NRES active
0.5
1.7
3.5
mA
INRES
High state reset leakage current
VNRES = VS; NRES
inactive
300
μA
Reset I/O low state level
VCC1 ≤ VCC1_TH;
INRES = 1 mA
0.5
V
VNRES_L
VLMODE_H
Led mode switch high state input
VLMODE_L
Led mode switch low state input
-ILMODE
4
Internal pull up current source
VLMODE = 0
V
10
1
V
25
µA
Max
Unit
VCC2
V
0.5
V
18
Table 20. G1 driver 1 pin characteristics
Symbol
Parameter
Test condition
Min Typ
VG1_H
Gate1 high level
5
VG1_L
Gate1 low level
tr_G1
Gate1 charging rise time
CG = 4.7 nF; VGS1 rising from
10 % to 90 %; VS ≥ 10 V
40
ns
tf_G1
Gate1 discharging fall time
CG = 4.7 nF; VGS1 falling from
90 % to 10 %; VS ≥ 10 V
40
ns
Table 21. G2 pin characteristics (driver2)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
V(ISENSE+) +14
V
0.05
V
VG2_H
High state output
VG2 voltage
PWM_L = High;
V(ISENSE+) = 30 V
VG2_L
Low state output
voltage VG2
PWM_L = Low;
V(ISENSE+) = 30 V
-IG2_H
Gate 2 high state
output current
PWM_L = High;
VGS_M2 = 6 V(1); CGS_M2 = 1 nF;
V(ISENSE+) = 30 V
200
µA
IG2_L
Gate 2 low state
output current
PWM_L = Low; VGS_M2 = 6 V(2);
CGS_M2 = 1 nF;
V(ISENSE+) = 30 V
200
µA
V(ISENSE+) +10
1. IG2_H current is measured when the voltage across gate and source of Mosfet M2 (VGS_M2) reaches a value of 6 V during
its rising transient.
2. IG2_L current is measured when the voltage across gate and source of Mosfet M2 (VGS_M2) reaches a value of 6 V during
its falling transient.
48/69
DocID025319 Rev 3
L99LD01
Electrical characteristics
Table 22. Converter oscillator and RSF pin characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
1.21
1.25
V
520
kHz
Voltage at pin RSF
IRSF = 42 µA
1.12
DC-DC converter frequency range
See Figure 12
100
FO_S
Oscillator frequency spread at
125 kHz
IRSF = 17 µA
(FO ≈ 125 kHz)
100
125
150
kHz
FO_S
Oscillator frequency spread at
300 kHz
IRSF = 42 µA
(FO ≈ 300 kHz)
240
300
360
kHz
FO_S
Oscillator frequency spread at
470 kHz
IRSF = 67 µA
(FO ≈ 470 kHz)
420
470
520
kHz
VRSF
FO
Duty cycle
max
DC-DC converter max duty cycle
limit
90
%
Duty cycle min
DC-DC converter min duty cycle
limit
10
%
FMOD
Modulation frequency of the internal See Section 3.5: Control
oscillator
registers (RAM) FMOD[0:1]
See Section 3.5: Control
registers (RAM) FDEV[0:2]
D% = ∆F0 / F0 Frequency deviation factor
1.95, 3.9, 7.8, 15.6
kHz
0 to ±35 (step ±5 %)
%
Table 23. PWM_L, PWM, MOUT pin characteristics
Symbol
Parameter
Test condition
TONPWM_L
Minimum PWM_L on time
PWM_LLOW
Low level PWM_L input voltage
PWM_LHIGH
High level PWM_L input voltage
4
IPWM_L_PD
Pull down current source
20
PWMLOW
Low level PWM input voltage
PWMHIGH
High level PWM input voltage
4
RPWM_PD
Pull Down resistor
50
VMOUT_H
High state output voltage (digital mode)
-IMOUT = 0.1 mA
VMOUT_L
Low state output voltage (digital mode)
IMOUT = 0.1 mA
ZMOUT
QG = 9 nC
Min
Typ
Max
100
µs
1
V
V
28
35
µA
1
V
V
230
500
4
kΩ
V
1
Analogue mode output impedance
Unit
10
V
kΩ
Table 24. ISENSE+, ISENSE- pin, and O.T.A. characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Units
VISENSE+
VISENSE-
Common mode input
range
VS - 0.3
49
V
(VISENSE+ VISENSE-)
Operative differential
input voltage range
-1
0.3
V
DocID025319 Rev 3
49/69
68
Electrical characteristics
L99LD01
Table 24. ISENSE+, ISENSE- pin, and O.T.A. characteristics (continued)
Symbol
Parameter
(VISENSE+ - LED over current
VISENSE-)_TH protection threshold
ISENSE_CD
Current consumption
from ISENSE+
(LED_OV)
Test condition
V(ISENSE+) = 25 V;
VLREF = VLREF_16;
VRCCOMP = 2 V
VSENSE+ = VSENSE- = 25 V
Threshold at pin
VSENSE_MAX_1 ISENSE+ for overvoltage
protection (activation)
VSENSE_MAX_2
Threshold at pin
ISENSE+ for overvoltage
protection (deactivation)
VOFFS
OTA input offset voltage
VLREF = 0 V; V(ISENSE+) = 25 V;
VRCCOMP = 2 V
IOFFS
OTA input offset current
V(ISENSE+) = 25 V;
VRCCOMP = 2 V
GM
Transconductance gain
V(ISENSE+) = 25 V;
VRCCOMP = 2 V
-ICOMP
Sourced output current
ICOMP
VCOMP
VLREF_16
Sunk output current
Max
Units
VLREF +
VLREF +
VLREF +
0.03
0.08
0.14
V
3
5
10
mA
49.5
52
54
V
25
33
35
V
10
mV
10
µA
-10
1.2
mS
VLREF = VLREF_16;
(VISENSE+ - VISENSE-) = 0
50
175
µA
VLREF = VLREF_16;
(VISENSE+ - VISENSE-) = 300 mV
50
175
VLREF = VLREF_16;
(VISENSE+ - VISENSE-) = 1 V
100
300
µA
0
Internal LED current
register = 16d; VNTC = 5 V;
VISENSE+ = 25 V
Internal voltage
reference range for
setting output LED
current(1)
VNTC = 5 V
VLREF_NTC
Max internal VLREF
reduction caused by
NTC intervention
(thermal LED current
reduction)
VNTC = 0 V
VLREF_STEP
Internal voltage
reference step
VLREF
Typ
0.95
Output voltage range
Default internal voltage
reference for constant
LED current regulation
Min
138
150
3.5
V
162
mV
(8 + N) /
24 *
VLREF_16
mV
(2)
0.5 *
VLREF
mV
4/3*
(VLREF_16
/ 31)
mV
ISP, ISN pin characteristics
VSP, VSN
50/69
Shunt resistor input
voltage range
-0.3
DocID025319 Rev 3
5
V
L99LD01
Electrical characteristics
Table 24. ISENSE+, ISENSE- pin, and O.T.A. characteristics (continued)
Symbol
Test condition
VSP-VSN
Differential input
voltage range
GLA_CPK
Gain of internal linear
amplifier
VSP = 100 mV; VSN = 0 V; Pin
SC floating
VLA_OFFS
Linear amplifier output
offset voltage
Default internal
reference for the
current limiter(3)
VCL_31
(VSP-VSN)TH
1.
Parameter
Internal C.L. voltage
reference range
VCL_STEP
Internal C.L. voltage
reference step
Typ
Max
Units
0.5
V
-0.3
9.8
12
VSP = VSN = 0
150
350
Internal C.L. register = 31
3.5
Differential threshold
Internal C.L. register = 31;
voltage for activate max
VSC = 5 V
input current prot.
VCL
Min
8
300
V
350
0.279 *
VCL_31
mV
400
mV
VCL_31
V
(0.721 *
VCL_31 /
31)
V
Writing into 5 bit LED Current Register via SPI.
2. N is the number corresponding to the 5 bits of LED_CURR control register.
3.
Settable by loading the 5 bit C.L. Register via SPI.
Table 25. SC pin characteristics
Symbol
Parameter
Test condition
VSC_low
Min ramp voltage at pin SC
ISC = 0
VSC_HIGH
Max ramp voltage at pin SC
ISC = 0
RSC
Min
Typ
Max
Units
0.2
0.45
V
2
2.6
V
1000
kΩ
1.4
Ext. resistor range
10
Table 26. VLED pin characteristics
Symbol
Parameter
VLED
Operative input voltage range for OV
detection
RVLED_PD
Pull down resistor
OV_TH1
LED overvoltage threshold 1
boost application
OV_TH2
LED overvoltage threshold 2
boost application
Test condition
Min
Typ
Max
LMODE = low
0
5
LMODE = high
VS
VS+5
Units
V
0.4
0.8
1.2
mΩ
LMODE = low
3.4
3.5
3.6
V
LMODE = low
2.3
2.5
2.7
V
DocID025319 Rev 3
51/69
68
Electrical characteristics
L99LD01
Table 26. VLED pin characteristics (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Units
OV_TH1_VS
LED overvoltage threshold 1
buck-boost application
LMODE = high
VS +
3.2
VS +
3.55
VS +
3.8
V
OV_TH2_VS
LED overvoltage threshold 2
buck-boost application
LMODE = high
VS +
2.2
VS +
2.45
VS +
2.8
V
Table 27. INP_OV pin characteristics (input overvoltage shut down)
Symbol
Parameter
Test condition
Min
Typ
Max
Units
5
V
VINP_OV
Operative input overvoltage range
0
-IINP_OV
Pull UP current source at input INP_OV VINP_OV = 0 V
10
18
25
µA
VINP_OV_TH1
Internal voltage reference 1
3.4
3.6
3.7
V
VINP_OV_TH2
Internal voltage reference 2
2.7
2.9
3.1
V
Min
Typ
Max
Units
5
V
Table 28. NTC pin characteristics
Symbol
Parameter
Test condition
VNTC
Operative NTC voltage range
INTC
Pull down current source
0
VNTC=5 V
5
10
15
µA
VNTC_TH1
Reference for current LED thermal
LED temp ramp up
regulation, temp ramp up
1.13
1.2
1.27
V
VNTC_TH2
Reference for current LED thermal
LED temp ramp down
regulation, temp ramp down
1.38
1.45
1.52
V
Table 29. ENABLE, LHM pin characteristics
Symbol
Parameter
Test condition
Min
VENABLE_L
Low level ENABLE input voltage
VENABLE_H
High level ENABLE input voltage
4
RENABLE_PD
Enable pull down resistor
50
Typ
Max Units
1
VLHM_L
Low level limp home mode input pin
VLHM_H
High level limp home mode input pin
ILHM_PU
Limp home pin pull up current
V
250
500
kΩ
1
V
4
VHLM = 0
10
V
V
18
25
µA
Table 30. Power on reset
Symbol
Parameter
Test condition
Min
Typ
Max
Units
POR_TH1
Internal power on reset threshold
VC5V rising; VS = 13.5 V;
C5V = 10 µF
3.2
3.7
4.2
V
POR_TH2
Internal power on reset threshold
VC5V falling; VS = 13.5 V;
C5V = 10 µF
2.7
3.4
3.7
V
52/69
DocID025319 Rev 3
L99LD01
Electrical characteristics
Table 31. Watchdog and timers parameters
Symbol
Parameter
tWDTO
Watchdog timeout window
tDStart
Start time window
Test condition
tEnRecov
1.
Min
Typ
Max
Units
100 or 200(1)
ms
5
ms
5
ms
Selectable by SPI command.
DocID025319 Rev 3
53/69
68
SPI electrical characteristics
L99LD01
6
SPI electrical characteristics
6.1
DC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 24 V; all outputs open; Tj = -40 °C to 150 °C, unless otherwise
specified.
Table 32. SPI DC characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
0.3
VC5V
V
Inputs: CSN, CLK, DI
VIL
Input voltage low level
VS = 13.5 V
VIH
Input voltage high level
VS = 13.5 V
0.7
VC5V
V
VIHYS
Input hysteresis
VS = 13.5 V
500
mV
ICSN in
CSN pull-up current source
VS = 13.5 V
10
18
25
µA
ICLK in
CLK pull-down current source
VS = 13.5 V
20
25
35
µA
DI pull-down current source
VS = 13.5 V
20
25
35
µA
VOL
Output voltage low level
IOL = 5 mA;
VS = 13.5 V
0.3
VC5V
V
VOH
Output voltage high level
IOH = -5 mA;
VS = 13.5 V
IDI in
Output: DO
6.2
0.7
VC5V
V
AC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 24 V; all outputs open; Tj = -40 °C to 150 °C, unless otherwise
specified.
Table 33. SPI AC characteristics
Symbol
COUT(1)
CIN
(1)
Parameter
Test condition
Min
Typ
Max
Unit
Output capacitance (DO)
—
—
10
pF
Input capacitance (DI, CSN, CLK)
—
—
10
pF
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
54/69
DocID025319 Rev 3
L99LD01
6.3
SPI electrical characteristics
Dynamic characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 24 V; all outputs open; Tj = -40 °C to 150 °C, unless otherwise
specified.
For definition of the parameters please see Figure 29 and Figure 30.
Table 34. SPI dynamic characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
tCSNQVL
DO enable from tristate to
low level
CDO = 100 pF; IDO = 1 mA;
pull-up load to VCC;
VCC1 = 5.0 V
100
250
ns
tCSNQVH
DO enable from tristate to
high level
CDO = 100 pF; IDO = 1 mA; pull-down load to
GND; VCC1 = 5.0 V
100
250
ns
tCSNQTL
DO disable from low level
to tristate
CDO = 100 pF; IDO = 4 mA;
pull-up load to VCC;
VCC1 = 5.0 V
380
450
ns
tCSNQTH
DO disable from high level
to tristate
CDO = 100 pF, IDO = -4 mA;
pull-down load to GND;
VCC1 = 5.0 V
380
450
ns
tCLKQV
CLK falling until DO valid
VDO < 0.3 VCC or
VDO > 0.7 VCC; CDO = 5 pF;
VCC1 = 5.0 V
ns
VDO < 0.3 VCC or
VDO > 0.7 VCC;
CDO = 100 pF; VCC1 = 5.0 V
ns
tSCSN
CSN setup time, CSN low
before rising edge of CLK
VCC1 = 5.0 V
400
ns
tSDI
DI setup time, DI stable
before rising edge of CLK
VCC1 = 5.0 V
200
ns
tHCLK
minimum CLK high time
VCC1 = 5.0 V
115
ns
tLCLK
minimum CLK low time
VCC1 = 5.0 V
115
ns
tHCSN
minimum CSN high time
VCC1 = 5.0 V
4
µs
tSCLK
CLK setup time before
CSN rising
VCC1 = 5.0 V
400
ns
tr DO
DO rise time
CDO = 100 pF; VCC1 = 5.0 V
80
140
ns
tf DO
DO fall time
CDO = 100 pF; VCC1 = 5.0 V
50
100
ns
tr in
rise time of input signal
DI, CLK, CSN
VCC1 = 5.0 V
100
ns
tf in
fall time of input signal
DI, CLK, CSN
VCC1 = 5.0 V
100
ns
DocID025319 Rev 3
55/69
68
SPI electrical characteristics
L99LD01
Figure 29. SPI timing parameters
W+&61
&61
W&6149
W&6147
'DWDRXW
'2
'DWDRXW
W&/.49
W6&61
W6&/.
&/.
W6',
',
W+&/.
W/&/.
'DWDLQ
'DWDLQ
("1($'5
Figure 30. SPI input and output timing parameters
WU'2
9&&
'2
ORZWRKLJK
9&&
WI'2
9&&
'2
KLJKWRORZ
9&&
WILQ
WULQ
',
&/.
&61
9&&
9&&
("1($'5
56/69
DocID025319 Rev 3
L99LD01
SPI electrical characteristics
Figure 31. SPI maximum clock frequency
W6&.ULVH
W6&.ILOW
W6&.49
6&.
0LFUR&RQWUROOHU
0DVWHU
6ODYH
0,62
WVHWXS
("1($'5
The maximum SPI clock frequency can be calculated as follows (see Figure 31):
tCLKQV(total) = tCLKrise(uC) + tCLKfilt(PCB) + tCLKQV(slave) + tsetup(uC)
fCLK(max) < ½ x tCLKQV(total)
Example:
tCLKQV = 25 ns + 100 ns + 250 ns + 25 ns = 400 ns
fCLK(max) < 1.25 MHz
Figure 32. NRES pin open drain structure
15(6
("1($'5
DocID025319 Rev 3
57/69
68
SPI electrical characteristics
L99LD01
Figure 33. Handshake procedure at start up with microcontroller on board
9&&
9&&B7+
15(6
PV
6WDUWXS$FNQRZOHGJPHQWZLWKLQ RU PV
15(6
PV
15(6
6WDUWXSDFNQRZOHGJPHQWZLWKLQRWKHU RU PV
PV
,IQRDFNQRZOHGJPHQWZLWKLQ RU PVÎ GHYLFHHQWHUVLQ/LPS+RPHPRGH
,IQRDFNQRZOHGJPHQWDIWHUFRQVHFXWLYHUHVHWSXOVHVGHYLFHHQWHUVLQ/LPS+RPH
0RGHDQG5HJXODWRU9&&LVVZLWFKHG2))
("1($'5
58/69
DocID025319 Rev 3
L99LD01
Application circuits
7
Application circuits
Typical application circuits are shown on the following Figure 34, Figure 35 and Figure 36.
Figure 37 shows the case of standalone application. Figure 38 shows an example for the
boost converter topology which uses an external Mosfet M3, for provide reverse battery
protection, maintaining at same time a very low drop voltage in the normal functioning, but
achieving low dissipation and high efficiency, in case of high power applications (LED
headlamps).
Figure 34. Boost application circuit
9%&0
'
&
&
'
&
&
.
.
0LFUR
.
.
15(6
3:0B/
6',
6'2
6&.
/+0
.
,63
,VHQVH
,VHQVH
*
/02'(
&61
56+817
Q)
0
(;7B9&&
(1$%/(
5
0
*
,61
0287
3:0
,13B29
5
96
9&&
&
56(16(
9&&
&
6&
5
Q)
&
5
5
5&FRPS
5
*QG
*QG
*QG
&
&9
5
56)
5
&
&3%
9/('
17&
9
5
5
&
5
6XSSO\YROWDJHSURYLGHGE\WKHERG\FRQWUROPRGXOH
517&
&KDVWREHXVHGLQFDVHWKHGHIDXOWPVUHVHWWLPHKDVWREHLQFUHDVHG
,QFDVHRI/LPS+RPHHYHQW
/+0 JQGÎ 'HYLFHDOZD\V2II
/+0 2SHQRU+LJKÎ 'HYLFHDOZD\V21
(;7B9&& &RQQHFWWKLVSLQWRJQGLIWKHX3LVVXSSOLHGE\9&& SLQ,IWKHX3LVH[WHUQDOO\VXSSOLHGE\DQH[WHUQDO9VXSSO\
FRQQHFWWKLVSLQWRWKHX3H[WHUQDOVXSSO\
5&FRPSRQHQWVKDYHWREHFKRVHQLQRUGHUWRGRQ¶WUHVHWWKHGHYLFHGXULQJ3:0RSHUDWHGE\WKH%&09ROWDJH
2SWLRQDOFRPSRQHQWVIRUQRLV\ILOWHULQJ
("1($'5
DocID025319 Rev 3
59/69
68
Application circuits
L99LD01
Figure 35. Fly back application circuit
9%&0
'
&
'
&
&
&
&
5
Q)
15(6
3:0B/
6',
6'2
6&.
.
.
0LFUR
.
.
,VHQVH
,VHQVH
*
/02'(
0287
3:0
,13B29
/+0
56(16(
0
.
56+817
Q)
0
(;7B9&&
(1$%/(
5
*
,63
5
,61
&61
5
96
&
9&&
9&&
&
&9
5
&
5
6&
5
5&FRPS
&
56)
5
*QG
*QG
*QG
5
&
&3%
9/('
17&
9
5
5
&
5
6XSSO\YROWDJHSURYLGHGE\WKHERG\FRQWUROPRGXOH
&KDVWREHXVHGLQFDVHWKHGHIDXOWPV UHVHWWLPHKDVWREHLQFUHDVHG
,QFDVHRI/LPS+RPHHYHQW
/+0 JQG Î 'HYLFHDOZD\V2II
/+0 2SHQRU+LJKÎ 'HYLFHDOZD\V21
(;7B9&& &RQQHFWWKLVSLQWRJQG LIWKHX3 LVVXSSOLHGE\9&& SLQ,IWKHX3 LVH[WHUQDOO\VXSSOLHGE\DQH[WHUQDO9VXSSO\
FRQQHFWWKLVSLQWRWKHX3 H[WHUQDOVXSSO\
5&FRPSRQHQWVKDYHWREHFKRVHQLQRUGHUWRGRQ¶WUHVHWWKHGHYLFHGXULQJ3:0RSHUDWHGE\WKH%&09ROWDJH
2SWLRQDOFRPSRQHQWVIRUQRLV\ILOWHULQJ
517&
("1($'5
60/69
DocID025319 Rev 3
L99LD01
Application circuits
Figure 36. Buck-boost application circuit
9%&0
'
&
&
'
&
&
&
5
15(6
3:0B/
6',
6'2
6&.
.
.
.
.
5
517&
56+817
Q)
Q)
56(16(
5
(;7B9&&
(1$%/(
/+0
,63
0
.
,VHQVH
,VHQVH
*
/02'(
0287
3:0
,13B29
5
*
,61
&61
5
96
9&&
9&&
&
0LFUR
5
&
6&
5
5&FRPS
5
&9
&
56)
5
*QG
*QG
*QG
5
&
&3%
9/('
17&
0
&
5
9
6XSSO\YROWDJHSURYLGHGE\WKHERG\FRQWUROPRGXOH
&KDVWREHXVHGLQFDVHWKHGHIDXOWPVUHVHWWLPHKDVWREHLQFUHDVHG
,QFDVHRI/LPS+RPHHYHQW
/+0 JQGÎ 'HYLFHDOZD\V2II
/+0 2SHQRU+LJKÎ 'HYLFHDOZD\V21
(;7B9&& &RQQHFWWKLVSLQWRJQGLIWKHX3LVVXSSOLHGE\9&& SLQ,IWKHX3LVH[WHUQDOO\VXSSOLHGE\DQH[WHUQDO9VXSSO\
FRQQHFWWKLVSLQWRWKHX3H[WHUQDOVXSSO\
5&FRPSRQHQWVKDYHWREHFKRVHQLQRUGHUWRGRQ¶WUHVHWWKHGHYLFHGXULQJ3:0RSHUDWHGE\WKH%&09ROWDJH
2SWLRQDOFRPSRQHQWVIRUQRLV\ILOWHULQJ
("1($'5
DocID025319 Rev 3
61/69
68
Application circuits
L99LD01
Figure 37. Stand alone application example for boost topology
9%&0
'
&
&
'
5
.
5
&
&
5
&
15(6
3:0B/
6',
6'2
6&.
5
5
0287
3:0
,13B29
(;7B9&&
(1$%/(
/+0
96
,VHQVH
,VHQVH
*
/02'(
*QG
*QG
*QG
5
0
*
,63
.
,61
&61
5
9&&
6&
5&FRPS
&9
9&&
56(16(
5
56)
Q)
&
&
&3%
9/('
17&
56+817
Q)
0
&
9
&
5
5
5
6XSSO\YROWDJHSURYLGHGE\WKHERG\FRQWUROPRGXOH
7KHLQWHUQDOFLUFXLWU\UHFRJQL]HVWKHVWDQGDORQHRSHUDWLRQVKRUWLQJ15(6WR96
&RQQHFWWKLVSLQWR9IRUHQDEOLQJ'LWKHU(IIHFW
(;7B9&& ,QVWDQGDORQHLVVXJJHVWHGWRFRQQHFWWKLVSLQWR&9
5&FRPSRQHQWVKDYHWREHFKRVHQLQRUGHUWRGRQ¶WUHVHWWKHGHYLFHGXULQJ3:0RSHUDWHGE\WKH%&09ROWDJH
2SWLRQDOFRPSRQHQWVIRUQRLV\ILOWHULQJ
517&
("1($'5
62/69
DocID025319 Rev 3
L99LD01
Application circuits
Figure 38. Reverse battery protection: an example for boost topology
9%$77
0
&
&
5
&
&
.
.
0LFUR
.
.
96
*
,63
,VHQVH
,VHQVH
*
/02'(
&61
/+0
56+817
(QDEOH&RQWURO
Q)
0
(;7B9&&
(1$%/(
5
0
.
,61
0287
3:0
,13B29
5
9&&
6&
5&FRPS
15(6
3:0B/
6',
6'2
6&.
&9
&
9&&
56(16(
5
&
56)
5
Q)
&
5
5
*QG
*QG
*QG
&RQWURO
&
&3%
9/('
17&
5
9
5
&
5
&KDVWREHXVHGLQFDVHWKHGHIDXOWPVUHVHWWLPHKDVWREHLQFUHDVHG
517&
,QFDVHRI/LPS+RPHHYHQW
/+0 JQGÎ 'HYLFHDOZD\V2II
/+0 2SHQRU+LJKÎ 'HYLFHDOZD\V21
(;7B9&& &RQQHFWWKLVSLQWRJQGLIWKHX3LVVXSSOLHGE\9&& SLQ,IWKHX3LVH[WHUQDOO\VXSSOLHGE\DQH[WHUQDO9VXSSO\
FRQQHFWWKLVSLQWRWKHX3H[WHUQDOVXSSO\
2SWLRQDOFRPSRQHQWVIRUQRLV\ILOWHULQJ
("1($'5
If the DRL module is supplied by a high side driver (HSD) of the body control module (BCM),
a minimum current consumption is requested during the off phase of the PWM dimming, so
that the HSD of the BCM do not detect a wrong open load condition. This is in charge of the
µP which has to draw this “minimum current consumption”, from the supply line (see
Figure 39).
DocID025319 Rev 3
63/69
68
Application circuits
L99LD01
Figure 39. External MOS required during PWM dimming
9ROWDJHPRGXODWLRQZLWKKLJKGXW\F\FOH+]
SURYLGHGE\WKH+6'RIWKH%RG\&RQWURO0RGXOH
9%&0
'
&
3:0B/GLPPLQJHJGXW\F\FOH
6DPHRUPXOWLSOHIUHTXHQF\RI
9%&0 PRGXODWLRQ
7R3:0B/SLQRI/('GULYHU
0LFUR
0
0LVWXUQHGRQGXULQJWKHRIISKDVHRIWKH3:0B/GLPPLQJVLJQDO
'!0'#&4
64/69
DocID025319 Rev 3
L99LD01
Package information
8
Package information
8.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
8.2
LQFP32™ package information
Figure 40. LQFP32™ package dimensions
("1($'5
DocID025319 Rev 3
65/69
68
Package information
L99LD01
Table 35. LQFP32™ mechanical data
Millimeters
Symbol
Min.
Typ.
A
1.6
A1
0.05
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
D
8.80
9.00
9.20
D1
6.80
7.00
7.20
D3
0.15
0.20
5.60
E
8.80
9.00
9.20
E1
6.80
7.00
7.20
E3
L
5.60
0.45
L1
K
0.60
0.75
1.00
0°
3.5°
ccc
66/69
Max.
7°
0.10
DocID025319 Rev 3
L99LD01
9
Order codes
Order codes
Table 36. Device summary
Order code
Package
Tube
LQFP32
L99LD01
DocID025319 Rev 3
67/69
68
Revision history
10
L99LD01
Revision history
Table 37. Document revision history
68/69
Date
Revision
Changes
19-Jun-2014
1
Initial release.
15-Jun-2015
2
Updated Description
Table 15: Absolute maximum ratings:
– VG1, VG2, VCPB, VISENSE-: updated values
Table 16: Thermal data:
– RThj-case: updated values
Table 17: VS and VCC1 pin characteristics:
– tVSM, tV1F, tV1OT: updated values
– VCC1_DROP: updated description
– tLMODERR, tOC, tLEDOV, tWD1, tWD2: added parameters
Table 19: NRES and LMODE pin characteristics:
– tRR, tFS, tRD: updated values
Table 21: G2 pin characteristics (driver2):
– VG2_H: updated values
Table 22: Converter oscillator and RSF pin characteristics:
– FO: updated values
– FO_S: updated test conditions and values
– Renamed “Duty cycle” symbol in “Duty cycle max”: updated test
conditions and values
– Renamed “TON_MIN” symbol in “Duty cycle min”: updated test
conditions and values
Table 24: ISENSE+, ISENSE- pin, and O.T.A. characteristics:
– VISENSE+IR, VISENSE-IR: removed parameters
– VISENSE+, VISENSE-, (VISENSE+ - VISENSE-)_TH , VSENSE_MAX_1,
VLREF_16: updated values
Table 25: SC pin characteristics:
– VSC_low, VSC_HIGH: updated test conditions and values
Table 26: VLED pin characteristics:
– OV_TH1_VS, OV_TH2_VS: updated test conditions and values
Updated Chapter 8: Package information
25-Jun-2015
3
Table 32: SPI DC characteristics:
– ICLK in, IDI in: updated maximum value
DocID025319 Rev 3
L99LD01
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
DocID025319 Rev 3
69/69
69
工商网监
湘ICP备2023018690号
