L99LD20Q6TR

L99LD20 High power LED driver for automotive applications Datasheet - production data Applications • Low Beam • High beam 4)1/[ *$'*36 • Daytime running light • Turn indicator • Position light Features • Side marker • AEC-Q100 qualified • General – ST SPI communication v4.1 – 5.5 to 24 V Operating battery voltage range – Load dump protected – QFN40L 6x6 (wettable flanks) with exposed pad – Timeout watchdog and limp home function – Low standby current • Buck section – Integrated switching mosfets – Lossless current sensing without need of external components – Very accurate LED current setting programming inductor's peak current and peak-to-peak current ripple – Adjustable peak current by SPI – Adjustable current ripple by SPI – Integrated PWM generation unit with 10-bit resolution and phase shift – Peak current control – Constant VLED x TOFF architecture • Fog light Description The L99LD20 is a flexible LED driver, which is specifically designed for the control of two independent high brightness LED strings for automotive front lighting applications. It consists of a high efficiency monolithic dual buck converter. The buck converters integrate n-channel MOSFET which is driven by a bootstrap circuit. When more than two LED channels are required on one module, then more devices L99LD20 can be combined; also with L99LD21 device – incorporating Boost Controller - from which L99LD20 derivate. • Protection and diagnostic – Battery under voltage – Temperature warning (2 thresholds) – Overtemperature shutdown – LED voltage digital feedback through SPI – Buck outputs short circuit and open load protection July 2018 This is information on a product in full production. DS11366 Rev 3 1/61 www.st.com Contents L99LD20 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 2 3 Buck converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3 Peak and average current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.4 Buck converter’s blank time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 Buck converter’s start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 3.2 3.3 4 2/61 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.2 Pre-standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.4 Limp home . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.5 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Programmable functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 Activation of the buck output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 PWM dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Temperature warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Overtemperature shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.3 VS under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.4 Buck TON minimum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.5 Buck output’s short circuit to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.6 Buck TON maximum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.7 Buck Open Load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DS11366 Rev 3 L99LD20 5 6 Contents 4.3 Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.2 Status Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4.3 Customer test and trimming registers description . . . . . . . . . . . . . . . . . 36 4.4.4 Customer test and trimming procedure description . . . . . . . . . . . . . . . . 37 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.2 Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.4.4 Direct input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.5 PWM dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.6 Digital timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 QFN-40L 6x6 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.1 8 Control Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 7 4.4.1 QFN-40L 6x6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Appendix A Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DS11366 Rev 3 3/61 3 List of tables L99LD20 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. 4/61 Pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DIN pin Map for Buck1 and Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operation code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Global Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Global Status Byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ROM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CR#1: Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CR#2: Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CR#3: Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CR#4: Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Constant VLED x TOFF selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DIN map table for Buck Cell X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Buck input voltage window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SR#1: Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SR#2: Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SR#3: Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Watchdog status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CT: Ctm Trimming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Writing test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Testing procedure description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Default peak current selection for Buck Cell 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Default VLEDxTOFF Selection for Buck Cell 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 QFN40L 6x6 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Buck converter power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Inductor peak current selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 VLEDxTOFF constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Direct Input pin limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PWMCLK and Fall back PWM description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Digital timings description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 QFN-40L 6x6 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DS11366 Rev 3 L99LD20 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Peak current control principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Inductor and mosfet current waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Testing flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IL_PEAK vs DAC code - Low Rdson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IL_PEAK vs DAC code - High Rdson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 VLED x TOFF vs DAC code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PWM clock failure and reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 QFN-40L 6x6 on four-layers PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 QFN-40L 6x6 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DS11366 Rev 3 5/61 5 Introduction 1 L99LD20 Introduction The L99LD20 is a monolithic driver IC, which controls the current of two independent high power LED strings, whose forward current and voltage can reach up to 1.5 A (average) and up to 50 V respectively. This device has been designed with dedicated functions, in order to fulfill the stringent requirements of automotive front lighting applications. The device offers a high level of flexibility, without any change of the external components, thanks to its programmability through the ST SPI interface. This feature support generic platform approaches, which require a software configurability of several parameters. This robust interface, offers a detailed diagnostic of the device itself, as well as of the controlled LED strings. As the device potentially controls safety critical functions such as low beams and turn indicators, built-in features are integrated in order to support a high level of functional safety. The L99LD20 features a timeout watchdog, a monitoring of the watchdog counter, a limp home function and a direct input. The ST SPI protocol takes into account FMEA case. The device consists of two independent integrated buck converters, whose input voltage is compatible with VBUCKIN. The integrated buck converters are based on constant off-time architecture (for a given LED output voltage) and control the peak current and the peak-topeak current ripple of their respective inductors. Operating in continuous conduction mode, the average of each LED string’s current, which is connected to the output of each buck converter, is tightly controlled. This architecture, which consists of two independent buck stages, allows the control of a wide range of LED strings, whose forward voltage is independent from the battery voltage. With the aim of ensuring a wide operating inductor current range, the Buck mosfets can be set in low or high RDS_ON modes, so that two different inductor peak current (ILx_PEAK) ranges [0.179 A ÷ 0.849 A] or [0.362 A ÷ 1.695 A] can be selected. The average LED current is controlled by setting the inductor's peak current and peak-topeak current ripple. Sensing of the peak current is integrated, not requiring any external shunt resistance, which saves cost and reduces the power dissipation. Buck n-channel mosfet RDS_ON value depends on the operative conditions as junction temperature, Input voltage and LED string current. For example, at VBuckin = 45 V, Iled = 700 mA, Tj = 25 °C the maximum RDS_ON is 400 mΩ (low RDS_ON mode). 6/61 DS11366 Rev 3 L99LD20 1.1 Introduction Typical application Figure 1. Functional block diagram 96 95(* 9 89/2 963, &61 6&. 6', 6'2 63, UHJLVWHUV 'LJLWDO %RRVW)6: 3URWHFWLRQV 99 %RRVW3JRRG '$& '$& &%227 %675$3 %8&.,1 *$7( '5,9(5 /;) 6WDWH 0DFKLQH &RQVWDQW 7RII[9/(' &/$03 &XUUHQW6HQVLQJ '$& ELW'$& &XUUHQW 5HIHUHQFH /;6 $'& %8&. 3URWHFWLRQV &%227 'LDJQRVWLF 273'HIDXOW 3HDNFXUUHQW ',1 3:0&/. 9/(' %8&.,1 %8&. :DWFKGRJ /;) /LPS+RPH /;6 6WDQGE\ 3:0'LP ELW ',* '$& $'& 3*1' 9/(' 6*1' *$'*06 DS11366 Rev 3 7/61 60 Introduction L99LD20 Figure 2. Typical application schematic [//' %2267B287387 96 %2267 &21752//(5 5VK [//' %2267 &21),* %8&. &219(57(5 %2267 %8&. &21752//(5 &219(57(5 9%8&.,1B 5VF /2*,& 5VK %8&. %8&. &219(57(5 &219(57(5 9%8&.,1B /2*,& %8&.&21),* ',$* /2*,& %8&.&21),* ',$* 96 63, 0LFURFRQWUROOHU 3K\V /D\HU 5VF %8&. 63, %8&. &219(57(5 &219(57(5 63, %8&.&21),* ',$* 3ZU0QJPW %2267 &21),* 5HYHUVH %DWWHU\ 9%8&.,1B %8&. &219(57(5 9%8&.,1B %8&. &219(57(5 63,%86 *$'*06 Figure 3. Application diagram 5HYHUVH %DWWHU\ )LOWHU &B96 96 3RZHU 0DQDJHPHQW 7(67 6*1' &B9B5(* 99 0LFURFRQWUROOHU 6XSSO\ 7(67 9VXSSO\ &B963, 963, 9/(' &61 )URQW/('GULYHU 6&/. 6', //' 5B9/('B &%227 %8&.,1 /('B&+$,1B &B%6753B /B%&.B /;) 'B%&.B /;6 6'2 &,1B%&.B &287B%&.B 0LFURFRQWUROOHU 6 tSTDBY (EN,GOSTBY) = (0,1) Characteristics – V3V3 < VPOR; – VS and VSPI low consumption; – SPI inactive – V3V3 > VPOR – Bucks disabled – SPI active – By default, when device leaves Standby mode – Under following condition, when device is in Active mode: – All registers reset to VSPI Under voltage default values Automatic transition after Reset mode WD failure; 400 ns – V3V3>VPOR One SPI frame setting (EN,GOSTBY) = (0,0) – SPI inactive Two consecutive SPI frames setting: UNLOCK = 1 (EN,GOSTBY) = (1,1) DS11366 Rev 3 17/61 60 Functional description L99LD20 Table 2. Operating modes (continued) Operating mode Entering conditions Leaving condition – SPI sequence to enter Active mode: – DIN access enabled: UNLOCK = 1 Buck1 is according to (EN,GOSTBY) = (1,0) DIN; – SPI sequence to enter Buck2 is OFF Standby mode: – SPI active UNLOCK = 1 (EN,GOSTBY) = (0,1) Limp Home 400 ns after Reset mode Active mode Characteristics – VSPI undervoltage – WD failure – Buck converters are – SPI sequence to enter active Standby mode: – SPI is active UNLOCK = 1 (EN,GOSTBY) = (0,1) SPI sequence: – UNLOCK = 1 – EN = 1 and GOSTBY = 0 3.2 Programmable functions 3.2.1 Activation of the buck output In Active mode, the activation of the Buck converters is performed according to the configuration of control register CR#3 for Buck1 and CR#3 for Buck2, as showed in the following table. See Table 15: CR#3: Control Register 3. Table 3. DIN pin Map for Buck1 and Buck2 3.2.2 CR#3 or CR#3 CR#3 or CR#3 Buck1 and Buck2 status 0 0 Buckx always OFF (default for Buck2) 0 1 Buckx attached to internal PWM generator 1 0 Buckx always ON 1 1 Buckx controlled by DIN Input (default for Buck1) PWM dimming The device allows modifying the brightness of the LEDs string simply managing the average current. The PWM dimming could be achieved in two different ways: • Through direct input, DIN • With integrated PWM generator Dimming with direct input The signal applies to buck1, buck2 or both, depending on DIN mapping bit configuration (see bits and bits on Table 15: CR#3: Control Register 3). If the control 18/61 DS11366 Rev 3 L99LD20 Functional description registers are configured accordingly, one (or both) buck converter(s) are activated and directly controlled by DIN pin. The default configuration is set in order to allow direct driving only for buck1, whilst buck2 is turned off. In case of limp home function, the default conditions are applied. PWM control through DIN has to take into account the DIN filter time (tDIN_FT, 32 µs typical) on rising edge to properly set the desired duty cycle. Dimming with integrated PWM generator This function allows modifying the average current on the LEDs by means of a dedicated control register (see bits and bits on Table 13: CR#1: Control Register 1). This function must be activated setting the right mapping bits configuration inside the control register 3, and in particular, CR#3 for Buck1 and CR#3 for Buck2. To set duty cycle, a 10-bit number must be written in the corresponding register, resulting in a 1024 steps of resolution. The duty cycle is determined through the following equation: N DC % = ------------- ⋅ 100 1024 Where N is the 10-bit number. The PWM frequency is depending on the PWM_CLK input signal with the following equation: PWM_CLK PWM_LF = ----------------------------1024 Where PWM_LF is the LEDs dimming frequency. If PWM signal fails, an error bit is reported in the STATUS register where PWMCLK fail is located. An internal fallback oscillator is enabled in order to provide a fixed PWM frequency clock signal (FFALLBACK_CLK), whilst no changes is applied on the duty cycle. Once the external PWM is available again and after a read & clear operation on Status Register 2, the internal clock is disabled and PWM operation continues with the external clock (see Figure 12). 3.3 Protections 3.3.1 Temperature warning The device integrates a temperature warning with two thresholds TW1 and TW2 in each buck’s mosfet. If the Tj of the buck mosfet1 or buck mosfet2 rises above TW1 or TW2, the status bit TWxy is set (x = 1 or x = 2, it stands for the buck1 or buck2, y = 1 or y = 2, it stands for the TW1 or TW2) . TWXY bit is set on the status registers: SR#1 for Buck1 and SR#2 for Buck2. Thermal warning is also reported in the Global Status Byte register, and in particular, bit 25 (GW) is set. If the Tj drops below the temperature warning reset threshold 1 (TW1-TW1_HYS), respectively TW2 – TW2_HYS, the corresponding status bit is automatically reset. As long as the Tj does not exceed the over temperature shutdown, the device does not latches off the buck mosfets, even if a temperature warning is detected. DS11366 Rev 3 19/61 60 Functional description 3.3.2 L99LD20 Overtemperature shutdown If the junction temperature of one of the buck mosfets rises above the shutdown temperature TTSD, an overtemperature event (OVT) is detected. The channel is switched off and the corresponding bit (OVT1 or OVT2) is set in the status register SR#1 for Buck1 and SR#2 for Buck2. Overtemperature events are also reported in the Global Status Byte register and in particular bit 27 FE1 is set. In normal mode the corresponding buck converter is latched off, until the following conditions are fulfilled: 1. TJX drops below the thermal shutdown reset threshold TTSD-TTSD_HYS. 2. Subsequently the microcontroller sends a read and clear command, in order to reset OVT1 or OVT2 bit located in the Status register SR#1 or SR#2. In fail safe mode (Limp Home), the device applies an auto restart of the fault buck converter with a period equal to tAUTORESTART, provided that the TJX falls below TSD reset threshold (TTSD-TTSD_HYS). 3.3.3 VS under voltage lockout If the VS supply falls below VS_UV (VS under voltage threshold), the buck converters will be deactivated, regardless of the SPI control registers or DIN. This feature is implemented, in order to avoid any operation outside the allowed VS operating range. 3.3.4 Buck TON minimum operation Buck minimum on time operation is detected when the corresponding failure counter counts N_Ton_min_fail switching cycles (also nonconsecutive), during which ILx_PEAK is reached between TBLANK_BUCK and TON_MIN_BUCK. In normal mode (Active mode), once minimum TON operation is validated, flag TON_MIN_OPx is set and the corresponding Buckx converter is latched off, until the microcontroller sends a frame and clears the corresponding status bit (SR#1 and SR#1). In fail safe mode (Limp Home), once a minimum TON violation is validated, the corresponding buck converter is latched off until automatically cleared by an auto-restart procedure, with a period equal to tAUTORESTART. The failure counter is not incremented during the startup phase (TSTARTUP). The failure counter is reset if Nton_min_fail_reset consecutive pulses are detected with TON longer than TON_MIN_BUCK. 3.3.5 Buck output’s short circuit to GND A shorted buck output to GND is detected when LED string voltage (VLED) is lower than a specified threshold (VLED_SHT) and the corresponding failure counter counts Nton_min_fail switching cycles (also nonconsecutive), during which ILx_PEAK is reached between TBLANK_BUCK and TON_MIN_BUCK. In normal mode (Active mode), once a short circuit is validated, flag SHTx is set and the corresponding Buckx converter is latched off, until the microcontroller sends a frame and clears the corresponding status bit (SR#1 and SR#1). 20/61 DS11366 Rev 3 L99LD20 Functional description In fail safe mode (Limp Home), once a short circuit is validated, the corresponding buck converter is latched off until automatically cleared by an auto-restart procedure, with a period equal to tAUTORESTART. The failure counter is not incremented during the startup phase. The failure counter is reset if Nton_min_fail_reset consecutive pulses are detected with TON longer than TON_MIN_BUCK. 3.3.6 Buck TON maximum operation Buck maximum on time operation is detected when switching on time is equal to tON_MAX_BUCK for two consecutive cycles. Once maximum Ton operation is validated, flag TON_MAX_OPx is set and the corresponding Buckx converter is temporarily switched off for a Ttonmax_off. Then, Buckx is enabled to switch on again while TON_MAX_OPx bit will be latched until a R&C command clears corresponding status bit (SR#2 or SR#2). In fail safe mode (Limp Home), once a maximum TON violation is validated, the corresponding buck converter is latched off until automatically cleared by an auto-restart procedure, with a period equal to tAUTORESTART. 3.3.7 Buck Open Load detection If one of the LED strings is disconnected, the converter will charge the output capacitor of the buck converter by regulating the peak current of the switch, until VLED is equal to the buck input voltage. From this point, since the output capacitor is charged at the maximum possible value, it cannot absorb any current despite the activation of the switch, and the target ILx_PEAK cannot be reached. Upon these conditions, Buckx starts switching at maximum Ton: maximum Ton operation detection (described in Section 3.3.6) guarantees Open Load failure protection as well. DS11366 Rev 3 21/61 60 SPI functional description L99LD20 4 SPI functional description 4.1 SPI protocol ST-SPI is a standard used in ST automotive ASSP devices. SPI protocol standardization here described defines a common structure of the communication frames and defines specific addresses for product and status information. The ST-SPI will allow usage of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular product. In addition to that, fail safe mechanisms are implemented to protect the communication from external influence and wrong or unwanted usage. 4.2 SPI communication At the beginning of each communication the master can read the content of the register (ROM address 10h) of the slave device. This 8 bit register indicates the SPI frame length (32 bit) and the availability of additional features. Each communication frame consists of a command byte which is followed by 3 data bytes. The data returned on SDO within the same frame always starts with the . It provides general status information about the device. It is followed by 3 data bytes (i.e. “in-frame-response”). For write cycles the is followed by the previous content of the addressed register. Table 4. Command byte (8 bit) Operating code Address Bit 31 30 29 28 27 26 25 24 Name OC1 OC0 A5 A4 A3 A2 A1 A0 Table 5. Data byte 2 Data byte 2 Bit 23 22 21 20 19 18 17 16 Name D23 D22 D21 D20 D19 D18 D17 D16 Table 6. Data byte 1 Data byte 1 22/61 Bit 15 14 13 12 11 10 9 8 Name D15 D14 D13 D12 D11 D10 D9 D8 DS11366 Rev 3 L99LD20 SPI functional description Table 7. Data byte 0 Data byte 0 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Where: OCx: Operation Code Ax : Address Dx: Data bit Command Byte Each communication frame starts with a command byte. It consists of an operating code which specifies the type of operation (, , , ) and a 6 bit address. Table 8. Operation code definition OC1 OC0 Meaning 0 0 0 1 1 0 1 1 The and operations allow access to the RAM of the device. A operation is used to read a status register and subsequently clears its content. The allows access to the ROM area which contains device related information. Global Status Byte According to the ST SPI 4.1 standard, the first byte on the SDO pad during each command reports the global status of the chip: Table 9. Global Status Byte Global Status Byte Bit 31 30 29 28 27 26 25 24 Name GSBN RSTB SPIE FE2 FE1 DE GW FS DS11366 Rev 3 23/61 60 SPI functional description L99LD20 Table 10. Global Status Byte description Bit Name 31 GSBN Global Status Bit Not This bit is a NOR combination of the remaining bits of this register: RSTB nor SPIE nor FE2 nor FE1 nor DE nor GW nor FS 30 RSTB Reset Bit The RSTB indicates a device reset. In case this bit is set, all internal Control Registers are set to default and kept in that state until the bit is automatically cleared by any valid SPI communication. 29 SPIE SPI Error The SPIE is a logical OR combination of errors related to a wrong SPI communication (SDI stuck, wrong number of clock, parity check error) FE2 Functional Error 2 (logic OR combination of errors which does not cause parts of the device to be disabled) TOFF1_MAX or TOFF2_MAX or TOFF1_MIN or TOFF2_MIN or TON_MAX_OP1 or TON_MAX_OP2 27 FE1 Functional Error 1 (logic OR combination of critical errors which cause parts of the device to be disabled) VS_UV or OL1 or OL2 or OVT1 or OVT2 or SHT1 or SHT2 ot TON_MIN_OP1 or TON_MIN_OP2. 26 DE Device error PWMCLK_FAIL. 25 GW Global warning TW11 or TW12 or TW21 or TW22 24 FS Fail safe If this bit is set, the device is in limp home mode 28 4.3 Description Address mapping Table 11. RAM memory map Address 24/61 Name Access Content 01h Control Register 1 R/W CR#1: 1st Control Register 02h Control Register 2 R/W CR#2: 2nd Control Register 03h Control Register 3 R/W CR#3: 3rd Control Register 04h Control Register 4 R/W CR#4: 4th Control Register 05h Status Register 1 R/C SR#1: 1st Status Register 06h Status Register 2 R/C SR#2: 2nd Status Register 07h Status Register 3 R/C SR#3: 3rd Status Register DS11366 Rev 3 L99LD20 SPI functional description Table 11. RAM memory map (continued) Address Name Access R/W (W only when EOT bit = 0) 3Eh Customer Trimming Register 3Fh Advanced Operation Code Clear Content CT: Customer Trimming Register A R&C operation to this address causes all status registers to be cleared Table 12. ROM memory map Address Name Access Content Comments 00h Company Code R 00h STMicroelectronics 01h Device family R 02h LED product family 02h Device number 1 R 55h ‘U’ in ASCII 03h Device number 2 R 41h ‘A’ in ASCII 04h Device number 3 R 52h ‘R’ in ASCII 05h Device number 4 R 07h ‘7’ in hex 0Ah Silicon version R 04h Fifth version 31h Bit7 = 0, burst read is disabled SPI data length = 32 bits Bit6, DL2 = 0 Bit5, DL1 = 1 Bit4, DL0 = 1 Bit3, SPI8 = 0: 8 bit frame option not available Bit2 =0 Parity check is used Bit1, S1=0 Bit0, S0=1 4Ah A WD is implemented Bit7, WD1 =0 Bit6, WD0 =1 WD period 50 ms = 10 * 5 ms -> WT[5:0] = 0xA Bit5, WT5 = 0 Bit4, WT4 = 0 Bit3, WT3 = 1 Bit2, WT2 = 0 Bit1, WT1 = 1 Bit0, WT0 = 0 44h Bit7, WB1 = 0 Bit6, WB2 = 1 WBA[5-0], Bit[5-0] = address of the configuration register, where the WD bit is located = 04d = 000100b 10h 11h 13h SPI Mode WD Type 1 WD bit pos. 1 R R R DS11366 Rev 3 25/61 60 SPI functional description L99LD20 Table 12. ROM memory map (continued) Address Name Access Content Comments 14h WD bit pos. 2 R D7h Bit7, WB1 = 1 Bit6, WB0 = 1 Bit position of the WD bit within the corresponding configuration register = 23d = 010111b 20h SPI CPHA Test R 55h Predefined by ST - SPI , it is used to verify that the SCK Phase of the SPI master is set correctly 3Eh GSB Options R 00h All bits of GSB are used 00h Access to this address provokes a SW reset (all control registers are set to their default values; in addition, all status registers are cleared too). 3Fh Advanced Operation Code R Data field should not be all ones, otherwise an SDI stuck occurs 4.4 Registers description 4.4.1 Control Register description 20 19 18 17 16 15 14 13 12 11 10 DUTY1 Address: 0x01h Type: R/W 9 8 7 6 DUTY2 5 4 3 2 1 0 Parity bit 21 UNLOCK 22 HLEDCUR2 23 HLEDCUR1 CR#1: Control Register 1 Table 13. CR#1: Control Register 1 Bit Default Name Description 23÷14 1000000000 DUTY1 10 bit PWM duty cycle selection for Buck1 (from 0 to hex 3FF) Default 50% 13÷4 1000000000 DUTY2 10 bit PWM duty cycle selection for Buck2 (from 0 to hex 3FF) Default 50% 3 Set by OTP (DEF_HLEDCUR) 2 26/61 [1]: High LED current configuration selected for Buck1 (Low RON, both half power stages enabled) HLEDCUR1 [0]: Low LED current configuration selected for Buck1 (High RON, only one half power stage enabled) [1]: High LED current configuration selected for Buck2 (Low RON, both half power stages enabled) HLEDCUR2 [0]: Low LED current configuration selected for Buck2 (High RON, only one half power stage enabled) DS11366 Rev 3 L99LD20 SPI functional description Table 13. CR#1: Control Register 1 (continued) Bit Default 1 0 0 Name Description UNLOCK [0]: bits GOSTBY, EN and BST_DIS cannot be set to 1 [1]: bits GOSTBY, EN and BST_DIS can be set to 1 with the next SPI frame If UNLOCK = 1, then it is always automatically reset with the next valid SPI frame Parity bit ODD parity bit check 21 20 19 18 17 16 IL1_PEAK 15 14 IL2_PEAK Address: 0x02h Type: R/W 13 12 11 10 9 8 VLED_TOFF1 7 6 5 VLED_TOFF2 4 3 2 1 EN 0 Parity bit 22 Reserved 23 GOSTBY CR#2: Control Register 2 Table 14. CR#2: Control Register 2 Bit Default Name 23÷18 Set by OTP (see Table 27) IL1_PEAK Inductor Peak Current selection bits for Buck1 17÷12 100000 IL2_PEAK Inductor Peak Current selection bits for Buck2 11÷8 Set by OTP (see Table 28) VLED_TOFF1 Constant VLEDxTOFF Selection bits for Buck1: 0000: 10 V*µs; 1111: 72 V*µs; see Table 17 7÷4 1111 VLED_TOFF2 Constant VLEDxTOFF Selection bits for Buck2: 0000: 10 V*µs; 1111: 72 V*µs; see Table 17 3 0 GOSTBY Description Standby Mode Bit: 0: Device waked up 1: Standby (if EN = 0) GOSTBY can be set to 1 only if UNLOCK = 1; in other words, trying to set this bit to 1 when UNLOCK = 0 will have no effects and it will maintain its previous value. GOSTBY can be reset to 0 also when UNLOCK = 0. To set Standby mode it is necessary to send two consecutive SPI frames, as follows: 1st SPI write operation to set UNLOCK bit to 1 (CR#1, bit1) 2nd SPI write operation to set GOSTBY bit to 1 and EN bit to 0 DS11366 Rev 3 27/61 60 SPI functional description L99LD20 Table 14. CR#2: Control Register 2 (continued) Bit Default Name Description Active mode Enable Bit: 0: Device stays in Limp Home (if GOSTBY = 0). This status is assumed immediately after a wake up (CSN low or DIN High for a time > tWAKE_UP) 1: Device Enabled for Active mode operation (if GOSTBY = 0). EN can be set to 1 only if UNLOCK = 1; in other words, trying to set this bit to 1 when UNLOCK = 0 will have no effects and it will maintain its previous value. EN can be reset to 0 also when UNLOCK = 0. To set Active mode it is necessary to send two consecutive SPI frames as follows: 1st SPI write operation to set UNLOCK bit to 1 (CR#1, bit1) 2nd SPI write operation to set GOSTBY bit to 0 and EN bit to 1 2 0 EN 1 0 Reserved This bit must be set to 1 Parity bit ODD parity bit check 0 19 18 PH1 17 16 15 PH2 Address: 0x03h Type: R/W 14 13 12 11 10 9 8 Reserved 7 6 5 4 B_IN_W1 3 2 B_IN_W2 1 0 Parity bit 20 PWM_SYNC 21 DIN_MAP2 22 DIN_MAP1 23 Reserved CR#3: Control Register 3 Table 15. CR#3: Control Register 3 Bit Default Name 23÷20 0000 PH1 4 bit phase selection for Buck1: Phase shift = PH1 * 360 / 16 19÷16 0000 PH2 4 bit phase selection for Buck2: Phase shift = PH1 * 360 / 16 15÷14 11 DIN_MAP1 Buck1 DIN map (see Table 18) 13÷12 00 DIN_MAP2 Buck2 DIN map (see Table 18) 11÷7 11011 Reserved 6 0 5÷4 00 28/61 Description PWMSYNC: 0: PWM Counter not reset; PWM_SYNC 1: PWM Counter Reset (note that this bit is automatically reset after counter reset) B_IN_W1 Buck Input Voltage Window for Buck1 (see Table 19) DS11366 Rev 3 L99LD20 SPI functional description Table 15. CR#3: Control Register 3 (continued) Bit Default Name 3÷2 00 B_IN_W2 Buck Input Voltage Window for Buck2 (see Table 19) 1 1 Reserved This bit must be set to 1 Parity bit ODD parity bit check 0 Description 22 21 Reserved 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Parity bit 23 WD_TRIG CR#4: Control Register 4 Unused Address: 0x04h Type: R/W Table 16. CR#4: Control Register 4 Bit Default Name Description 23 0 WD_TRIG In order to keep device in Active mode, this bit must be cyclically toggled within a period equal to tWD to refresh the watchdog. 22÷21 00 Reserved Note: when writing on this register, bit 21 and 22 must be set to 00 20÷1 Unused 0 Parity bit ODD parity bit check Table 17. Constant VLED x TOFF selection VLED_TOFF Constant VLED x TOFF [V x µs] 0000 10 0001 12 0010 14 0011 16 0100 18 0101 20 0110 22 0111 24 1000 28 1001 32 1010 36 1011 40 1100 48 DS11366 Rev 3 29/61 60 SPI functional description L99LD20 Table 17. Constant VLED x TOFF selection (continued) VLED_TOFF Constant VLED x TOFF [V x µs] 1101 56 1110 64 1111 72 Table 18. DIN map table for Buck Cell X DIN_MAP X Status of Buck Cell X 00 Always OFF 01 PWM dimming 10 Always ON 11 Controlled by DIN Table 19. Buck input voltage window 30/61 B_IN_W Buck In voltage range [V] 00 10÷25 01 25÷40 10 40÷50 11 50÷60 DS11366 Rev 3 L99LD20 SPI functional description 4.4.2 Status Register description 16 15 14 VLED1,ON 13 12 11 10 9 8 VLED2,ON R/C Address: 0x05h Type: R, R/C 7 6 5 4 3 2 R 1 0 Parity bit 17 TON_MIN_OP2 18 TON_MIN_OP1 19 TW11 20 TW12 21 OVT1 22 SHT2 23 SHT1 SR#1: Status Register 1 R/C Table 20. SR#1: Status Register 1 Bit 23÷16 15÷8 7 6 Default 00000000 00000000 0 0 Name Description Access VLED1,ON ADC conversion related to VLED1 (ranging from 0 V to 52.5 V), sampled during on time of Buck1. Note that in case of Buck1 controlled by DIN pin or by SPI, the ADC is continuously refreshed during on-state, while, if controlled by internal PWM dimming generator, ADC refresh occurs only once per period just before the end of each PWM on-cycle. R/C VLED2,ON ADC conversion related to VLED2 (ranging from 0 V to 52.5V), sampled during on time of Buck2. Note that in case of Buck2 controlled by DIN pin or by SPI, the ADC is continuously refreshed during on-state, while, if controlled by internal PWM dimming generator, ADC refresh occurs only once per period just before the end of each PWM on-cycle. R/C SHT1 VLED1 short circuit detection. This bit is set when TON_MIN_OP1 is set too but only if, at the same instant, average VLED1 voltage is lower than 1.5V. When SHT1 = 1, Buck1 is disabled until a read and clear command of this bit has been acknowledged. In LHM, an auto restart procedure cyclically clears this bit with a period equal to tAUTORESTART R/C SHT2 VLED2 short circuit detection. This bit is set when TON_MIN_OP2 is set too but only if, at the same instant, average VLED2 voltage is lower than 1.5V. When SHT2 = 1, Buck2 is disabled until a read and clear command of this bit has been acknowledged. R/C DS11366 Rev 3 31/61 60 SPI functional description L99LD20 Table 20. SR#1: Status Register 1 (continued) Bit 5 4 3 2 1 0 32/61 Default 0 0 0 Name Description Access OVT1 Overtemperature for Buck1 (set when Tj ≥ TTSD for more than tOVT); If this bit is set: – in Active mode: Buck1 is latched OFF; reset is performed by a R&C command, which will be successful only if Tj < TTSD TTSD_HYS (typ 140 °C). Then Buck1 is allowed to turn on again. – in LHM, after setting an OVT1, an auto restart procedure is implemented: every tAUTORESTART OVT1 bit is automatically cleared and, if Tj < TTSD - TTSD_HYS, then Buck1 is allowed to turn on again, otherwise OVT1 bit is set again. R/C TW12 Thermal warning 2 for Buck1. This bit is set if Tj ≥ TW2. This is a read only and real time bit. When Buck1 temperature decreases under a second threshold (Tj < TW2 - TW2_HYS), this bit is cleared. R TW11 Thermal warning 1 for Buck1. This bit is set if Tj ≥ TW1 This is a read only and real time bit. When Buck1 temperature decreases under a second threshold (TW1 - TW1_HYS), this bit is cleared. R 0 Operation at minimum on-time for Buck1. This bit is set when Buck1 runs at an on-time shorter than tON_MIN_BUCK for more than 32 (even not consecutive) cycles. TON_MIN_OP1 When TON_MIN_OP1 = 1, Buck1 is disabled until a read and clear command of this bit has been acknowledged. In LHM, an auto restart procedure cyclically clears this bit with a period equal to tAUTORESTART. R/C 0 Operation at minimum on-time for Buck2. This bit is set when Buck2 runs at an on-time shorter than TON_MIN_OP2 tON_MIN_BUCK for more than 32 (even not consecutive) cycles. When TON_MIN_OP2 = 1, Buck2 is disabled until a read and clear command of this bit has been acknowledged. R/C Parity Bit ODD parity bit check DS11366 Rev 3 L99LD20 SPI functional description TON_MAX_OP1 TON_MAX_OP2 PWMCLK_FAIL VSPI_FAIL R/C R Address: 0x06h Type: R, R/C 14 13 12 11 10 9 R/C 8 7 6 5 Reserved — R R 4 3 2 1 0 Parity bit TW21 R 15 DIN_ST TW22 R/C 16 TOFF_MAX2 17 TOFF_MAX1 18 TOFF_MIN2 19 TOFF_MIN1 20 VS_UV 21 WD_FAIL 22 WD_STATUS 23 OVT2 SR#2: Status Register 2 Unused Table 21. SR#2: Status Register 2 Bit 23 22 21 20 19 Default 0 0 0 Name Description Access OVT2 Overtemperature for Buck2 (set when Tj ≥ TTSD for more than tOVT ); if this bit is set Buck2 is latched OFF; reset is performed by a R&C command, which will be successful only if Tj < TTSD - TTSD_HYS. Then Buck2 is allowed to turn on again. R/C TW22 Thermal warning 2 for Buck2. This bit is set if Tj ≥ TW2. This is a read only and real time bit. When Buck2 temperature decreases under a second threshold (Tj < TW2 - TW2_HYS), this bit is cleared. R TW21 Thermal warning 1 for Buck2. This bit is set if Tj ≥ TW1. This is a read only and real time bit. When Buck2 temperature decreases under a second threshold (TW1 - TW1_HYS), this bit is cleared. R 0 Operation at maximum on-time for Buck1. This bit is set when Buck1 runs at an on-time equal to tON_MAX_BUCK for two consecutive cycles. Every time this event occurs, Buck1 is temporarily switched off TON_MAX_OP1 for a tTON_MAX_OFF time, then is enabled to switch on again. Instead, TON_MAX_OP1 bit will be latched until a R&C. In LHM, an auto restart procedure cyclically clears this bit with a period equal to tAUTORESTART. R/C 0 Operation at maximum on-time for Buck2. This bit is set when Buck2 runs at an on-time equal to t for two consecutive cycles. TON_MAX_OP2 ON_MAX_BUCK Every time this event occurs, Buck2 is temporarily switched off for a tTON_MAX_OFF time, then is enabled to switch on again. Instead, TON_MAX_OP2 bit will be latched until a R&C. R/C DS11366 Rev 3 33/61 60 SPI functional description L99LD20 Table 21. SR#2: Status Register 2 (continued) Bit 18 Default 0 Name Description Access PWMCLK_FAIL When this bit is set, a PWM Clock Fail is detected. This occurs FPWMCLK ≤ FPWMCLK_FAIL. In this case PWMCLK signal is bypassed by an internal fall back PWM frequency clock (having a frequency equal to FFALLBACK_CLK). PWMCLK normal operation will be restored after a R&C operation, when PWMCLK frequency FPWMCLK > FPWMCLK_FAIL. R/C VSPI failure bit 0: VSPI (external SPI Supply) present 1: VSPI not present (VSPI voltage lower than VSPI_UV): device goes to Limp Home Mode R Watchdog status bit: see Table 23 R 17 0 VSPI_FAIL 16÷15 00 WD_STATUS 14 0 WD_FAIL 13 0 VS_UV 12 0 Watchdog failure bit: 0: watchdog OK; 1: watchdog failure in Active mode When this bit is set, the device goes in Limp Home Mode R/C VS undervoltage bit 0: VS > VS_UV; 1: VS ≤ VS_UV R TOFF_MIN1 Minimum off-time operation for Buck1 0: Off-time ≥ tOFF_MIN_BUCK 1: Off-time < tOFF_MIN_BUCK R R 11 0 TOFF_MIN2 Minimum off-time operation for Buck2 0: Off-time ≥ tOFF_MIN_BUCK 1: Off-time < tOFF_MIN_BUCK 10 0 TOFF_MAX1 Maximum off-time operation for Buck1: 0: Off-time < tOFF_MAX_BUCK 1: Off-time ≥ tOFF_MAX_BUCK R 9 0 TOFF_MAX2 Maximum off-time operation for Buck2: 0: Off-time < tOFF_MAX_BUCK 1: Off-time ≥ tOFF_MAX_BUCK R 8÷6 000 Reserved 5 0 DIN_ST Direct input status bit. Filtered replica of logical level at DIN pin. Filtering time is equal to tDIN_ST. R 4÷1 0000 Unused 0 34/61 Parity Bit ODD Parity Bit Check DS11366 Rev 3 L99LD20 SPI functional description SR#3: Status Register 3 22 21 20 19 18 17 16 15 14 VLED1,OFF 13 12 11 10 9 8 7 VLED2,OFF 6 5 4 3 2 1 0 Parity bit 23 Unused R/C Address: 0x07h Type: R/C Table 22. SR#3: Status Register 3 Bit 23÷16 Default 00000000 Name Description Access VLED1,OFF ADC conversion related to VLED1 (rangin g from 0 V to 52.5 V), sampled during off-time of Buck1. Note that in case of Buck1 controlled by DIN pin or by SPI, the ADC is continuously refreshed during off-state, while, if controlled by internal PWM dimming generator, ADC refresh occurs only once per period just before the end of each PWM off-cycle. R/C ADC conversion related to VLED2 (ranging from 0 V to 52.5 V), sampled during off-time of Buck2. Note that in case of Buck1 controlled by DIN pin or by SPI, the ADC is continuously refreshed during off-state, while, if controlled by internal PWM dimming generator, ADC refresh occurs only once per period just before the end of each PWM off-cycle. R/C 15÷8 00000000 VLED2,OFF 7÷1 0000000 Unused 0 Parity Bit ODD Parity Bit Check Table 23. Watchdog status WD_STATUS WD timer status 00 [0…24%] 01 [24% … 50%] 10 [50% … 74%] 11 [74% … 100%] DS11366 Rev 3 35/61 60 SPI functional description 4.4.3 L99LD20 Customer test and trimming registers description CT: Customer Trimming Register DEF_DAC1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Reserved Address: 0x3Eh Type: R/W Write operation allowed only when CTM_TRIM_COD = 100 and EOT = 0 Table 24. CT: Ctm Trimming Register Bit Default Name 23÷21 000 CTM_TRIM_COD 20÷19 00 DEF_HLEDCUR 18÷17 00 DEF_DAC1 16÷15 00 DEF_VLEDTOFF1 14 0 13 1 12 0 EOT 11÷1 00000000000 — Comment Operation Code for Trimming Operation: 011: Execute blank check read 100: Execute selected bit burning 010: Execute margin mode read 011: Execute blank check read 111: Execute end of trimming 001: Execute standard read Reserved 0 36/61 Parity Bit End of Ctm Trimming Reserved ODD Parity Bit Check DS11366 Rev 3 2 1 0 Parity bit 18 EOT 19 Reserved 20 DEF_VLEDTOFF1 21 DEF_HLEDCUR 22 CTM_TRIM_COD 23 L99LD20 4.4.4 SPI functional description Customer test and trimming procedure description General description The writing procedure is performed connecting the two terminals of the anti-fuse capacitor at 15 V and ground respectively. This is achieved by providing 15V on VS battery pin. After this phase, the capacitor is burnt and behaves like a resistance; its value (the residual resistance) strictly depends on the effectiveness of the burning procedure. During physical reading operation, the residual resistance is compared with a fixed threshold. If the residual resistance is greater than threshold a bit 0 is given, and the OTP cell is considered unwritten, otherwise a bit 1 is given and the OTP cell is considered written. Blank check reading is executed to verify that all anti-fuses are unwritten after fabrication, while margin mode, usually performed immediately after the burning process, is used to verify if burned cells are properly written. Executing a blank-check reading after all writing operations have been completed allows verifying that unwritten cells haven’t been degraded by burning processes. Recommended test flow In Figure 8 and in Table 26 the recommended testing procedure is shown and described. Testing procedure starts with a blank check read, to verify that all anti-fuse rows are unwritten. After this operation, it is possible to select the bits to be written and to start programming. Writing operation should be performed up to 3 times. At the end of programming, a reading procedure should be performed in Margin Mode. At the end of the test, it is strongly recommended executing a blank-check read in order to verify that unwritten cells haven’t been degraded. Table 25 summarizes the writing test conditions. Table 25. Writing test conditions Symbol Note: Parameter Conditions VS 15 V supply IHV HV current during programming — Temperature — External capacitance Min Typ Max 15 Unit V 28 mA -40 27 150 °C 2 5 10 nF An external capacitance must be applied between VS and GROUND pins. DS11366 Rev 3 37/61 60 SPI functional description L99LD20 Figure 8. Testing flow chart WHVWVWDUW %ODQNFKHFNUHDG 12 5HDG 2." 7 V % Figure 11. VLED x TOFF vs DAC code  9/('[72))>9[—V@                         '$&FRGH *$'*36 50/61 DS11366 Rev 3 L99LD20 Electrical specifications 5.4.3 SPI Table 37. SPI signal description Symbol CSN Parameter Test conditions Min Typ Max High State 0.7 * V3V3 — V3V3 — 0.3 * V3V3 — V3V3 — 0.3 * V3V3 — V3V3 — 0.3 * V3V3 Chip Select Not V Low State High State SCK 0.7 * V3V3 Serial Clock V Low State High State SDI 0.7 * V3V3 Serial data Input V Low State Serial data Output - High State IOUT = -1 mA VSPI-0.5 VSPI-0.2 — Serial data Output - Low State IOUT = 1 mA — 0.2 0.5 — -1 — 1 SDO ILK Output leakage current Note: Unit V µA See also Chapter 4: SPI functional description. Table 38. SPI timings Symbol Tsck Parameter Test conditions Min Typ Max Unit Serial clock (SCK) period 250 ns THsck SCK high time 100 ns TLsck SCK low time 100 ns Trise_in CSN, SCK, SDI rise time Fsck = 4 MHz 25 ns Tfall_in CSN, SCK, SDI fall time Fsck = 4 MHz 25 ns THcsn CSN high time TScsn 6 µs CSN setup time, CSN low before SCK rising 100 ns TSsck SCK setup time, SCK low before CSN rising 100 ns TSsdi SDI setup time before SCK rising 25 ns SDI hold time 25 ns Thold_sdi Tcsn_v CSN falling until SDO valid Cout = 50 pF; Iout = ±1 mA 100 ns Tcsn_v CSN rising until SDO tristate Cout = 50 pF; Iout = ±4 mA 100 ns Tsck_v SCK falling until SDO valid Cout = 50 pF 60 ns TRsdo SDO rise time Cout = 50 pF; Iout = -1 mA 100 ns DS11366 Rev 3 50 51/61 60 Electrical specifications L99LD20 Table 38. SPI timings (continued) Symbol TFsdo Tcsn_low_t 5.4.4 Parameter SDO fall time Test conditions Min Typ Max Unit 50 100 ns 35 50 ms Cout = 50 pF; Iout = 1 mA CSN low timeout 20 Direct input Table 39. Direct Input pin limits Symbol Parameter VDIN_L DIN Low threshold VDIN_H DIN High threshold 52/61 Test conditions Min 0.7 * V3V3 DS11366 Rev 3 Typ Max Unit — 0.3 * V3V3 V — V3V3 V L99LD20 5.4.5 Electrical specifications PWM dimming .. Table 40. PWMCLK and Fall back PWM description Symbol Parameter Test conditions Min Typ Max Unit 0.3 * V3V3 V VPWMCLK_L PWMCLK low threshold VPWMCLK_H PWMCLK high threshold 0.7 * V3V3 V3V3 V FPWMCLK PWMCLK input frequency range 102400 409600 Hz 0 26500 Hz 210 KHz FPWMCLK_FAIL PWMCLK frequency fail detection range FFALLBACK_CLK Fall back PWM frequency clock 190 200 Figure 12. PWM clock failure and reset sequence  3:0&ORFNIURP—& aN+]  5HDGDQG&OHDU RI3:0&/.)DLO 'HWHFWLRQRI 3:0&/.)DLO //'B 3:0B&/. &RUUHFW3:0&/.  VLJQDOLVGHWHFWHG  5HDGDQG&OHDU RI3:0&/.)DLO ([WHUQDO3:0&ORFNVLJQDOORVWĺ WKHGHYLFHXVHVWKHLQWHUQDO IDOOEDFNFORFNaN+] 3:0&ORFNIURP—& aN+] //'B 3:0B&/. 3:0FORFNFRXQWHU //'B //'B 3:0B&/. 3:0FORFNFRXQWHU //'B 3:0FORFNFRXQWHU //'B 6\QFKURQL]HGRU XQV\QFKURQL]HG3:0 GLPPLQJFORFNFRXQWHUV 3:0FORFNFRXQWHUIHG E\LQWHUQDON+]IDOO EDFNFORFN 7KH3:0FORFNFRXQWHULV IHGE\WKHH[WHUQDO 3:0&/.VLJQDO 3:0FORFNFRXQWHUVIUR]HQ GXHWRPLVVLQJFORFNVLJQDO 3:0&/.)DLOELW   $3:0&/.)DLOFRXQWHULVLPSOHPHQWHG ,WLVLQFUHPHQWHGLIQRULVLQJHGJHRQ3:0&/.SLQLV GHWHFWHGZLWKLQ—V 7KH3:0&/.)DLOFRXQWHULVGHFUHPHQWHGZKHQULVLQJ HGJHVRQ3:0&/.SLQDUHGHWHFWHGZLWKLQ—V  (YHQLIWKH3:0&/.)DLOFRXQWHULVUHVHWWKH3:0&/. )DLOELWLVVWLOOVHWDQGWKH3:0FORFNFRXQWHUIRUWKHORZ IUHTXHQF\3:0GLPPLQJLVVWLOOIHGE\WKHLQWHUQDO3:0 &ORFNaN+] $3:0&/.)DLOLVUHSRUWHGLIWKHFRXQWHUUHDFKHV 7KH3:0FORFNFRXQWHUIRUWKHORZIUHTXHQF\3:0 GLPPLQJLVIHGE\WKHLQWHUQDO3:0&ORFNaN+] 7KH3:0&/.)DLOELWLVVHW   $63,5HDGDQG&OHDU&RPPDQGRIWKH 3:0&/.)DLOELWLVGHWHFWHG +RZHYHUWKH3:0&/.)DLOFRXQWHULVQRW UHVHWWKHUHIRUHWKLVFRPPDQGKDVQRHIIHFW $3:0&/.)DLOFRXQWHUUHVHWGHFUHPHQWHGGRZQWR ]HURVLQFHDYDOLG3:0&/.VLJQDOLVGHWHFWHG IUHTXHQF\!N+]ULVLQJHGJHVZLWKLQ—V $UHDGDQGFOHDUFRPPDQGRIWKH3:0&/.)DLOELWLV GHWHFWHGZKLOHWKH3:0&/.)DLOFRXQWHULVUHVHW 7KH3:0&/.FRXQWHUVDUHUHVHWDQGDUHIHGE\WKH VLJQDORQWKHLU3:0&/.SLQ *$'*06 DS11366 Rev 3 53/61 60 Electrical specifications 5.4.6 L99LD20 Digital timings Table 41. Digital timings description Symbol Min Typ Max Unit Watchdog timeout period 45 50 55 ms tCSN_TIMEOUT CSN timeout 90 115 140 ms tAUTORESTART Autorestart time in limp home mode 45 50 55 ms tWD tVS,UV tDIN_FT(1) Parameter VS undervoltage filter time 32 µs DIN Filter time 32 µs 12.8 µs tDIN_ST DIN status information time tSKEW Timing skew for DIN tVSPI_FT VSPI Filtering Time tWAKE_UP Time for a complete wake up (V3V3 > VPOR_L) tSTDBY tOVT Test conditions 2.5 32 µs 190 µs DIN low Time needed for a Cap on V3V3 = 4.7 µF transition to standby mode (V3V3 < VPOR_L) V3V3 < 2.5 V 1.6 ms Filtering time for overtemperature (OVT bit will be set if Tj > TTSD for more than tOVT) 1.2 µs CSN low or DIN high for t > tWAKEUP Cap on V3V3 = 4.7 µF V3V3 > 3 V guaranteed by frequency oscillator (20 MHz typical) and scan 1. Digital timings guaranteed by scan. WD and autorestart timings limits added to give indication on application cases. 54/61 µs DS11366 Rev 3 L99LD20 Package and PCB thermal data 6 Package and PCB thermal data 6.1 QFN-40L 6x6 thermal data Figure 13. QFN-40L 6x6 on four-layers PCB Table 42. PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 129 mm x 60 mm Board Material FR4 Copper thickness (outer layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm DS11366 Rev 3 55/61 60 Package information 7 L99LD20 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 QFN-40L 6x6 package information Figure 14. QFN-40L 6x6 package dimensions ("1($'5 56/61 DS11366 Rev 3 L99LD20 Package information Table 43. QFN-40L 6x6 mechanical data Symbol Min Typ Max A 0.85 0.95 1.05 A1 0 A3 0.05 0.20 b 0.20 0.25 0.30 D 5.85 6.00 6.15 E 5.85 6.00 6.15 D2 3.95 4.10 4.25 E2 3.95 4.10 4.25 e 0.50 J 0.45 L 0.40 0.50 L1 0.20 L2 0.05 L3 0.20 L4 0.075 P 0.31 P1 0.18 P2 0.18 ddd 0.08 DS11366 Rev 3 0.60 57/61 60 Order codes 8 L99LD20 Order codes Table 44. Device summary Order code Package QFN-40L 6x6 58/61 Tube Tape and reel L99LD20Q6 L99LD20Q6TR DS11366 Rev 3 L99LD20 Glossary Appendix A Glossary Table 45. Glossary Acronym µC Description Microcontroller ADC Analog / Digital converter ASSP Application Specific Standard Product CPHA Clock Phase CPOL Clock Polarity CSN Chip select not (normal low) (SPI) CTRL Control register FE Functional Error FS Fail Safe GE Device Error GSB GSBN Global Status Byte Global Status Bit Not GW Global Warning I/O Input /Output pins DIN Direct input LH Limp Home LSB Least Significant Bit MCU Mirocontroller SDI SPI Data Input (slave) SDO SPI Data Onput (slave) MSB Most Significant Bit DS11366 Rev 3 59/61 60 Revision history L99LD20 Revision history Table 46. Document revision history 60/61 Date Revision Changes 04-Nov-2015 1 Initial release. 15-Mar-2018 2 Datasheet status promoted from preliminary data to production data. Updated the following sections: – Description in Cover page – Chapter 1: Introduction and ILx_PEAK current ranges – Added Figure 3: Application diagram – Section 2.3: Peak and average current setting – Section 3.1.1: Standby mode – Section 3.1.2: Pre-standby mode – Table 2: Operating modes – Section 3.2.2: PWM dimming – Table 12: ROM memory map – Section 4.4: Registers description: Section 4.4.1: Control Register description, Section 4.4.2: Status Register description, Section 4.4.2: Status Register description, Section 4.4.3: Customer test and trimming registers description – Chapter 5: Electrical specifications: Section 5.2: ESD protection Section 5.3: Thermal characteristics, Section 5.4: Electrical characteristics) 25-Jul-2018 3 Updated Figure 7: Device state diagram. Minor text changes to improve readability. DS11366 Rev 3 L99LD20 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11366 Rev 3 61/61 61