LNBH24
Dual LNB supply and control IC with step-up and I²C interface
Features
■
Complete interface between LNBS and I²C bus
■
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93%@0.5 A)
■
Selectable output current limit through external
resistor
■
Compliant with main satellite receivers output
voltage specification
■
New accurate built-in 22 kHz tone generator
meets widely accepted standards (patent
pending)
■
Fast oscillator start-up facilitates DiSEqC™
encoding
PowerSSO-36 (ePad)
designed to provide the 13/18 V power supply and
the 22 kHz tone signalling for two independent
LNB down-converters in the antenna dishes
and/or multi-switch box. In this application field, it
offers a dual tuner STBs with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
■
Built-in 22 kHz tone detector supports bidirectional DiSEqC™ 2.0
■
Very low-drop post regulator and high
efficiency step-up PWM with integrated power
N-MOS allow low power losses
■
Two output pins suitable for bypassing the
output R-L filter and avoiding tone distortion (RL filter as per DiSEqC™ 2.0 specs, see typ.
application circuits)
■
Overload and over-temperature internal
protections with I²C diagnostic bits
■
Output voltage and output current level
diagnostic feedback by I²C bits
■
LNB short circuit dynamic protection
■
+/- 4 kV ESD tolerant on output power pins
Description
Intended for analog and digital dual satellite
receivers/sat-TV, sat-PC cards, the LNBH24 is a
monolithic voltage regulator and interface IC,
assembled in PowerSSO-36 ePad, specifically
Table 1.
April 2009
Device summary
Order code
Package
Packaging
LNBH24PPR
PowerSSO-36 (Exposed pad)
Tape and reel
Rev 3
1/30
www.st.com
30
Contents
LNBH24
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5
Data encoding through external tone generator (EXTM) . . . . . . . . . . . . . . 6
2.6
I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.9
Output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10
22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.11
Minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.12
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.13
Over-current and short-circuit protection and diagnostic . . . . . . . . . . . . . . 8
2.14
Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
6.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
2/30
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LNBH24
Contents
7.2
System register (SR, 1 Byte for each section A and B) . . . . . . . . . . . . . . 16
7.3
Transmitted data (I²C bus write mode) for each section A/B . . . . . . . . . . 16
7.4
Diagnostic received data (I²C read mode) for both sections A/B . . . . . . . 17
7.5
Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6
Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7
DiSEqC™ implementation for each section A/B . . . . . . . . . . . . . . . . . . . 18
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
Block diagram
LNBH24
Block diagram
Figure 1.
Block diagram
TTX-A
-
ISEL --A
ADDR --A
SDA SCL
ADDR -B
-
LX -A
Byp
VCC --L
ISEL --B TTX-B
-
LX -B
Preregulator
+U.V.lockout
+P.ON reset
EN--A
VSEL--A
TTX--A
ITEST-A
VUP -A
ISEL--A
VOUT-A Control
Linear Post --reg
+Protections
+Diagnostics
VoRX -A
VCTRL -A
TEN--B
EN--B
TEN--A
EN--A
VSEL--A
I²C
² interface
PWM
Controller
Rsense
P-GND-A
VCC
EN--B
PWM
Controller
1
Rsense
VSEL--B
P-GNDB
VSEL--B
TTX-B
ITEST--B
VOUT--B Control
VUP --B
ISEL--B
Linear Post --reg
+Protections
+Diagnostics
I²C
² Diagnostics
VoRX -B
VCTRL -B
VoTX -A
VoTX -B
22KHz
Oscill.
TTX--A
Oscill.
TTX--B
EXTM --A
DETIN --A
DSQOUT -A
TEN--B
TEN--A
DSQIN -A
22KHz Tone
Amp. Diagn.
22KHz Tone
Freq. Det.
22KHz Tone
Freq. Det.
A-GND
-
4/30
DSQIN -B
22KHz Tone
Amp. Diagn.
LNBH24
EXTM -B
DETIN -B
DSQOUT -B
LNBH24
2
Introduction
Introduction
The LNBH24 includes two completely independent sections. Except for the VCC and I²C
inputs, each circuit can be separately controlled and have independent external
components. The specification that follow should be considered equally for both sections
(A/B).
2.1
Application information
This IC has a built-in DC-DC step-up converter which, from a single 8 V to 15 V source,
generates the voltages (VUP) that allow the linear post-regulator to work at a minimum
dissipated power of 0.375 W Typ. @ 500 mA load (the linear post-regulator drop voltage is
internally held at VUP-VOUT=0.75 V typ.). An under voltage lockout circuit will disable the
entire circuit when the supplied VCC drops below a fixed threshold (6.7 V typically).
Note:
In this document the VOUT is intended as the voltage present at the linear post-regulator
output (VoRX pin).
2.2
DiSEqC™ data encoding and decoding
The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance
with the standards, and can be selected through I²C interface TTX bit (or TTX pin) and
activated by a dedicated pin (DSQIN) which allows immediate DiSEqC™ data encoding, or
through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In
standby condition (EN bit LOW). The TTX function must be disabled setting TTX to LOW.
2.3
DiSEqC™ 2.0 implementation
The built-in 22 kHz Tone detector completes the fully bi-directional DiSEqC™ 2.0 (see
Note:) interfacing. Its input pin (DETIN) must be AC coupled to the DiSEqC™ bus, and
extracted PWK data are available on the DSQOUT pin. To comply with the bi-directional
DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH24 is
provided with two output pins for each section, one for the DC voltage output (VoRX) and one
for the 22 kHz tone transmission (VoTX). The VoTX must be activated only during the tone
transmission while the VoRX provides the 13/18 V output voltage. This allows the 22 kHz
Tone to pass without any losses due to the R-L filter impedance (see Figure 4). During the
22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by the TEN
bit, the VoTX pin must be preventively set ON by the TTX function. This can be controlled
both through the TTX pin and the I²C bit. As soon as the tone transmission is expired, the
VoTX must be disabled by setting the TTX to LOW to set the device in the 22 kHz receiving
mode. The 13/18 V power supply is always provided to the LNB from the VoRX pin through
the R-L filter.
2.4
DiSEqC™ 1.X implementation
When the LNBH24 is used in DiSEqC™ 1.x applications the R-L filter is always needed for
the proper operation of the 22 kHz tone generator (patent pending. See Figure 4). Also in
this case, the TTX function must be preventively enabled before to start the 22 kHz data
transmission and disabled as soon as the data transmission has been expired. The tone can
5/30
Introduction
LNBH24
be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates
the 22 kHz tone on the VoTX output with 0.5 cycle ± 25 µs delay from the TTL signal
presence on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal is
expired.
2.5
Data encoding through external tone generator (EXTM)
In order to improve design flexibility an external tone input pin is available (EXTM). The
EXTM is a Logic input pin which activates the 22 kHz tone output, on the VoTX pin, by using
the LNBH24 integrated tone generator (similar to the DSQIN pin function). In fact, the output
tone waveform characteristics will always be internally controlled by the LNBH24 tone
generator and the EXTM signal will be used as a timing control for DiSEqC tone data
encoding on the VoTX output. A TTL-compatible 22 kHz signal is required for the proper
control of the EXTM pin function. Before sending the TTL signal on the EXTM pin, the VoTX
tone generator must be previously enabled through the TTX function (TTX pin or TTX bit set
HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates
the 22 kHz tone on the VoTX output with 1.5 cycles ± 25 µs delay from the TTL signal
presence on the EXTM pin, and it stops with 2 cycles ± 25 µs delay after the TTL signal is
expired (see Figure 2).
Figure 2.
EXTM timings
2.6
I²C interface
The main functions of the IC are controlled via I²C BUS by writing 8 bits on the system
register (SR 8 bits in write mode). On the same register there are 8 bits that can be read
back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the
diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF),
while three will report the last output voltage register status (EN, VSEL, LLC) received by
the IC (see the diagnostic functions section). Each section (A/B) has two selectable I²C
addresses selectable, respectively, through the ADDR-A and ADDR-B pins (see address
pins characteristics Table 10).
2.7
Output voltage selection
When the IC sections are in standby mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC
LNBs. Additionally, the LNBH24 is provided with the LLC I²C bit which increase the selected
voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.
6/30
LNBH24
Introduction
The LNBH24 is also compliant with the USA LNB power supply standards. In order to allow
fast transition of the output voltage from 18 V to 13 V and vice-versa, the LNBH24 is
provided with the VCTRL TTL pin which keeps the output at 13 V when it is set LOW and at
18 V when it is set HIGH or floating. VSEL and, if required, LLC bits must be set HIGH
before using the VCTRL pin to switch the output voltage level. If VCTRL = 1 or floating, then
VOUT = 18.5 V (or 19.5 V if LLC=1). With VCTRL=0 VOUT=13.4 V (LLC= either 0 or 1).
Should be noted that the VCTRL pin controls only the linear regulator VOUT stage while the
step-up VUP voltage is controlled only through the VSEL and LLC I²C bits. That is, even if
VCTRL = 0 (keeping VOUT = 13.4 V) you will have VUP = 19.25 V typ when VSEL = 1 and
20.25 V with VSEL = LLC = 1. This means that VCTRL = 0 must be used only for short
period to avoid the higher power dissipation. In standby condition (EN bit LOW) all the I²C
bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but
the TTX bit must be set LOW during the standby condition).
2.8
Diagnostic and protection functions
The LNBH24 has 5 diagnostic internal functions provided via I²C BUS by reading 5 bits on
the system register (SR bits in read mode). All the diagnostic bits are, in normal operation
(no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature
and over-load protection status (OTF and OLF), while the remaining 3 bits are dedicated to
the output voltage level (VMON), 22 kHz Tone (TMON) and to the Minimum Load Current
diagnostic function (IMON).
2.9
Output voltage diagnostic
When VSEL = 0 or 1 and LLC = 0, the output voltage pin (VoRX) is internally monitored and,
as long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to
"1". The output voltage diagnostic is valid only with LLC = 0 and AUX = 0. Any VMON
information with LLC = 1 and/or AUX = 1 must be disregarded by the MCU.
2.10
22 kHz tone diagnostic
The 22 kHz tone can be internally detected and monitored If the DETIN pin is connected to
the LNB output bus (see typical application circuits) through a decoupling capacitor. The
Tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude
and/or the Tone frequency is out of the guaranteed limits (see TMON limits in the electrical
characteristics in Table 13), the TMON I²C Bit is set to "1".
2.11
Minimum output current diagnostic
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH24 is provided with a minimum output current flag by the
IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA
typically with ITEST=1, and 6 mA with ITEST=0. The minimum current diagnostic function
(IMON) is always active. In order for it to function even in a multi-IRD configuration (multiswitch), where the supply current could be sunk only from the higher supply voltage
connected to the multi-switch box, the LNBH24 is provided with the AUX I²C bit. To force the
LNBH24 output voltage as the highest voltage on the bus (22 V typ.) during the minimum
current diagnostic phase, the AUX I²C bit can be set HIGH before reading the IMON I²C bit
status. When the AUX bit is set to HIGH, the VOUT is set to 22 V (typ.) and the VUP is set to
7/30
Introduction
LNBH24
22.75 V (VUP = VOUT + 0.75 V typ.) independent of the VSEL/LLC bits status. If the AUX
function is used to force the VOUT to 22 V, it is recommended to set the AUX bit to LOW as
soon as the minimum current test phase is expired, so that the VOUT voltage will be
controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the
IMON function must be used only with the 22 kHz tone transmission deactivated (TEN = 0
and DSQIN = LOW), otherwise the IMON bit could be set to 0 even if the output current is
below the minimum current thresholds (6 mA or 12 mA).
2.12
Output current limit selection
The linear regulator current limit threshold can be set through an external resistor connected
to ISEL pin. The resistor value defines the output current limit by the equation:
IMAX(A) = 10000/RSEL
where RSEL is the resistor connected between ISEL and GND. The highest selectable
current limit threshold is 1.0 A typ with RSEL=10 kΩ. The above equation defines the typical
threshold value for each output. However, it is suggested not to exceed for an extended
period a total of current of 1 A from both sections (IOUT_A + IOUT_B < 1 A) in order to avoid
triggering the over-temperature protection.
2.13
Over-current and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically through the
PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output
is shut down for a time TOFF, typically 900 ms. Simultaneously the diagnostic OLF I²C bit of
the system register is set to "1". After this time has elapsed, the output is resumed for a time
TON = (1/10) TOFF = 90 ms (typ.). At the end of TON, if the overload is still detected, the
protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no
overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to
LOW. Typical TON+TOFF time is 990 ms and an internal timer determines it. This dynamic
operation can greatly reduce the power dissipation in short-circuit condition, still ensuring
excellent power-on start-up in most conditions. However, there could be some cases in
which a highly capacitive load on the output may cause a difficult start-up when the dynamic
protection is chosen. This can be solved by initiating any power start-up in static mode
(PCL=1) and then switching to the dynamic mode (PCL = 0) after a chosen amount of time
depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to
"1" when the current clamp limit is reached and returns LOW when the overload condition is
cleared.
2.14
Thermal protection and diagnostic
The LNBH24 is also protected against overheating. When the junction temperature exceeds
150 °C (typ.), the step-up converter and the liner regulator are shut off, and the diagnostic
OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when
the junction is cooled down to 135 °C (typ.).
Note:
8/30
External components are needed to comply to bi-directional DiSEqC™ bus hardware
requirements. Full compliance of the whole application with DiSEqC™ specifications is not
implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.
LNBH24
Pin configuration
3
Pin configuration
Figure 3.
Pin connections
Table 2.
A-GND
1
36
EXTM-B
TTX-B
2
35
VCTRL-B
DETIN-B
3
34
ISEL-B
DSQIN-B
4
33
VUP-B
DSQOUT-B
5
32
VOTX-B
ADDR-B
6
31
VORX-B
NC
7
30
A-GND
LX-B
8
29
VCC
P-GND-B
9
28
VCC-L
P-GND-A
10
27
BYP
LX-A
11
26
VORX-A
SDA
12
25
VOTX-A
SCL
13
24
NC
ADDR-A
14
23
NC
DSQOUT-A
15
22
VUP-A
DSQIN-A
16
21
ISEL-A
DETIN-A
17
20
VCTRL-A
TTX-A
18
19
EXTM-A
Pin description
Pin n°
(sec. A/B)
Symbol
Name
29
VCC
Supply input
8 to 15 V IC DC-DC power supply.
28
VCC–L
Supply input
8 to 15 V analog power supply.
11
LX-A
N-MOS Drain
Integrated N-Channel power MOSFETs drain.
8
LX-B
22
VUP-A
33
VUP-B
26
VoRX-A
Function
Step-Up voltage
Input of the linear post-regulators. The voltage on these pins is
monitored by the internal step-up controllers to keep a
minimum dropout across the linear pass transistors.
LDO output port
Outputs of the linear post-regulators. See Table 6 for voltage
selections and description.
31
VoRX-B
25
VoTX-A
32
VoTX-B
12
SDA
Serial data
Bi-directional data from / to I²C BUS.
13
SCL
Serial clock
Clock from I²C BUS.
16
DSQIN-A
4
DSQIN-B
Output port during
TX Outputs to the LNB. See Table 6 for selection.
22 kHz Tone TX
DiSEqC inputs
These pins will accept the DiSEqC code from the main
microcontroller. The LNBH24 will uses this code to modulate
the internally-generated 22 kHz carrier. Set to ground if not
used.
9/30
Pin configuration
Table 2.
LNBH24
Pin description (continued)
Pin n°
(sec. A/B)
Symbol
18
TTX-A
Name
TTX enable
2
TTX-B
17
DETIN-A
3
DETIN-B
15
DSQOUT- A
22 kHz tone decoders inputs must be AC coupled to the
DiSEqC 2.0 BUS. Set to GND if not used.
DiSEqC outputs
Open drain outputs of the tone detectors to the main
µController for DiSEqC 2.0 data decoding. They are LOW
when tone is detected on DETIN pins. Set to GND if not used.
External
modulation
External modulation logic input pins which activate the 22 kHz
tone output on the VoTX pins. Set to ground if not used.
DSQOUT- B
19
EXTM-A
36
EXTM-B
10
P-GND-A
9
P-GND-B
ePad
ePad
Exposed Pad
1, 30
A-GND
Analog grounds
Power grounds
BYP
14
ADDR-A
6
ADDR-B
21
ISEL-A
The TTX pins can be used as well as the TTX I²C bits of the
system register, to control the TTX function enable.
Set floating or to GND if not used.
Tone decoders
inputs
5
27
Function
DC-DC converters power grounds.
To be connected with power grounds and to the ground layer
through vias to dissipate the heat.
Analog circuits grounds.
By-pass capacitor
Needed for internal pre-regulator filtering. The BYP pin is
intended only to connect an external ceramic capacitor. Any
connection of this pin to external current or voltage sources
may cause permanent damage to the device.
Address setting
Two I²C addresses available for each section by setting the
Address pins voltage level. See Table 10
Current selection
The resistors “RSEL” connected between ISEL and GND
define the linear regulators current limit protection threshold
by the equation: IMAX(typ)=10000/ RSEL.
34
ISEL-B
20
VCTRL-A
35
VCTRL-B
Output voltage
control
13 V-18 V linear regulators VoRX switch control. To be used
only with VSEL=1. If VCTRL=1 or floating VoRX=18.5 V (or
19.5V if LLC=1). If VCTRL=0 than VoRX=13.4 V (LLC=either 0
or 1). Leave floating if not used. DO NOT connect to GND if
not used.
7, 23, 24
N.C.
Not connected
Not internally connected pins.
10/30
LNBH24
Maximum ratings
4
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
VCC-L, VCC DC power supply input voltage pins
DC input voltage
VUP
IO
Output current
Value
Unit
-0.3 to 16
V
-0.3 to 24
V
Internally limited
VoRX
DC output pin voltage
-0.3 to 25
V
VoTX
Tone output pin voltage
-0.3 to 25
V
VI
Logic input voltage (TTX, SDA, SCL, DSQIN, EXTM, VCTRL, Address)
-0.3 to 7
V
LX
LX input voltage
-0.3 to 24
V
2
VPP
VDETIN
Detector input signal amplitude
VOH
Logic high output voltage (DSQOUT)
-0.3 to 7
V
VBYP
Internal reference pin voltage (Note 1)
-0.3 to 4.6
V
ISEL
Current selection pin voltage
-0.3 to 4.6
V
TSTG
Storage temperature range
-50 to 150
°C
Operating junction temperature range
-25 to 125
°C
TJ
ESD
ESD rating with human body model (HBM) for all pins unless 8, 11, 25,
26, 31, 32
2
ESD rating with human body model (HBM) for pins 25, 26, 31, 32
4
ESD rating with human body model (HBM) for pins 8, 11
Note:
Note:
kV
0.6
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal.
1
Table 4.
Symbol
The BYP pin is intended only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent damage to the device.
Thermal data
Parameter
Value
Unit
RthJC
Thermal resistance junction-case
2
°C/W
RthJA
Thermal resistance junction-ambient (PSSO-36) with device
soldered on 2s2p PC Board
30
°C/W
11/30
Application circuit
LNBH24
5
Application circuit
Figure 4.
Typical application circuit
D3a
1N4007
C4a
470nF
C3a
100µF
L2a
C5b
100µF
C6b
470nF
22
Ferrite
Bead
19
20
36
35
EXTM-A
VCTRL-A
EXTM-B
VCTRL-B
VUP-A
C9a 10µF
VoTX-A
25
D4a
1N5818
D1a
STPS130A
L3a
11
VoRX-A
L1a
22µH
Rsel-A
Rsel-B
11KΩ
11KΩ
21
ISEL-A
34
ISEL-B
C1
100µF
C2
100nF
17
DSQIN-A
TTX-B
16
15
18
4
5
2
LX-B
DETIN-B
3
SCL
VoRX-B
31
VCC
28
VCC-L
R1
100Ω
C8
220nF
DSQOUT-A
TTX-A
DSQIN-B
DSQOUT-B
L1b
22µH
8
15 Ω
R4a
R3a 10KΩ
C12a
10nF
R3b 10KΩ
C12b
10nF
L3b
D1b
STPS130A
13
12
I 2C
SDA
C3b
100µF
L2b
Ferrite
Bead
C5b
100µF
C10b
220nF
33
VoTX-B
VUP-B
9
P-GND-A
10
A-GND
1-30
32
BYP
ADDR-A
ADDR-B
27
14
6
C11
470nF
D3b
1N4007
12/30
15Ω
R4b
C6b
470nF
P-GND-B
LNBOUT_B
220µH
D2b
BAT43
C4b
470nF
C13a 10nF
D2a
BAT43
L
N
B
H
2
4
DETIN-A
29
220µH
26
C10a
220nF
VIN
+12V
C7
100nF
LNBOUT_A
LX-A
C9b 10µF
D4b
1N5818
C13b 10nF
LNBH24
Table 5.
Application circuit
Bill of material (valid for A and B sections except for C1, C2, C7, C8 and R1)
Component
Notes
R1, R4
1/4 W resistors. Refer to the typical application circuit for the relative values
R3, RSEL
1/8 W resistors. Refer to the typical application circuit for the relative values
C1
25 V electrolytic capacitor, 100 µF or higher is suitable.
C9
10µF, > 35 V electrolytic capacitor
C3, C5
C2, C4, C6, C7, C8, C10,
C11, C12, C13
100µF, > 25 V electrolytic capacitor, ESR in the 150 mΩ to 350 mΩ range
>25 V ceramic capacitors. Refer to the typ. appl. circuit for the relative values
D1
STPS130A or any similar schottky diode with VRRM > 25 V and IF(AV) higher than:
IF(AV) > IOUT_MAX x (VUP_MAX/VIN_MIN)
D2
BAT43, 1N5818, or any schottky diode with IF(AV)>0.2A, VRRM > 25 V, VFIPEAK, where IPEAK is the boost converter peak current:
L1
L2
Ferrite bead, Panasonic-EXCELS A35, Murata-BL01RN1-A62, Taiyo-YudenBKP1608HS600 or equivalent with similar or higher impedance and current rating
higher than 2A
L3
220 µH-270 µH inductor with current rating higher than rated output current
13/30
I²C bus interface
6
LNBH24
I²C bus interface
Data transmission from main MCU to the LNBH24 and vice-versa takes place through the 2
wires I²C bus Interface, consisting of the 2 SDA and SCL lines (pull-up resistors to positive
supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 5 the data on the SDA line must be stable during the high semi-period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
6.2
Start and stop condition
As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4
Acknowledge
The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7). The peripheral (LNBH24) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH24 will not generate acknowledge if the
VCC supply is below the under-voltage lockout threshold (6.7 V typ.).
6.5
Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH24, the MCU can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data. This approach of course is less protected from malfunctions and decreases
the noise immunity.
14/30
LNBH24
I²C bus interface
Figure 5.
Data validity on the I²C bus
Figure 6.
Timing diagram of I²C bus
Figure 7.
Acknowledge on the I²C bus
15/30
LNBH24 software description
7
LNBH24
LNBH24 software description
The LNBH24 I²C interface controls both the IC sections A and B depending on the address
sent before the DATA byte. The description below is valid for both sections.
7.1
Interface protocol
The interface protocol comprises:
●
A start condition (S)
●
A chip address byte (the LSB bit determines read (=1)/write (=0) transmission)
●
A sequence of data (1 byte + acknowledge)
●
A stop condition (P)
Section address (A or B)
Data
MSB
S
0
LSB
0
0
1
0
X
X
MSB
LSB
R/W ACK
ACK
P
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, two addresses for each section selectable by ADDR-A/B pins (see Table 10)
7.2
System register (SR, 1 Byte for each section A and B)
Mode
MSB
LSB
Write
PCL
TTX
TEN
LLC
VSEL
EN
ITEST
AUX
Read
IMON
VMON
TMON
LLC
VSEL
EN
OTF
OLF
Write = control bits functions in write mode
Read = diagnostic bits in read mode.
All bits reset to 0 at power on
7.3
Transmitted data (I²C bus write mode) for each section A/B
When the R/W bit in the section address is set to 0, the main MCU can write on the system
register (SR) of the relative section (A or B, depending on the 7 bit address value) via I²C
BUS. All and 8 bits are available and can be written by the MCU to control the device
functions as per the below Table 6.
16/30
LNBH24
Table 6.
PCL
LNBH24 software description
Truth table
TTX
TEN
LLC
VSEL
EN
ITEST
0
0
0
1
0
VoRX= 13.4 V, VUP=14.15 V, (VUP-VoRX=0.75 V)
0
0
1
1
0
VoRX= 18.5 V, VUP=19.25 V, (VUP-VoRX=0.75 V)
0
1
0
1
0
VoRX= 14.4 V, VUP=15.15 V, (VUP-VoRX=0.75 V)
0
1
1
1
0
VoRX= 19.5 V, VUP=20.25 V, (VUP-VoRX=0.75 V)
X
X
1
1
VoRX= 22 V, VUP=22.75 V, (VUP-VoRX=0.75 V)
X
AUX
Function
0
1
22 KHz controlled by DSQIN pin (only if TTX=1)
1
1
22 KHz tone output is always activated
0
1
VoRX output is ON, VoTX Tone generator output is OFF
1
1
VoRX output is ON, VoTX Tone generator output is ON
0
1
Pulsed (dynamic) current limiting is selected
1
1
Static current limiting is selected
1
X
X
X
X
X
1
0
Minimum output current diagnostic threshold = 6mA typ.
X
X
1
1
Minimum output current diagnostic threshold = 12mA typ.
X
X
0
X
X
Power block disabled
X = don't care
All values are typical unless otherwise specified
Valid with TTX pin floating or connected GND
7.4
Diagnostic received data (I²C read mode) for both sections
A/B
The LNBH24 can provide to the master a copy of the diagnostic system register information
via I²C bus in read mode. The read mode is master activated by sending the chip address
with R/W bit set to 1. At the following master generated clock bits, the LNBH24 issues a byte
on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can:
●
Acknowledge the reception, thus starting the transmission of another byte from the
LNBH24
●
No acknowledge, stopping the read mode communication
Three bits of the register are read back as a copy of the corresponding write output voltage
register status (LLC, VSEL, EN), while the other five bits convey diagnostic information
about the over-temperature (OTF), output voltage level (VMON), output overload (OLF),
minimum output current presence (IMON) and 22 kHz tone (TMON). In normal operation the
diagnostic bits are set to zero, while if a failure is occurring, the corresponding bit is set to
one. At start-up all the bits are reset to zero.
17/30
LNBH24 software description
Table 7.
IMON
LNBH24
Register
VMON
TMON
LLC
VSEL
EN
These bits are read
exactly the same as
they were left after
last write operation
0/1
0/1
OTF
OLF
Function
0
TJ < 135°C, normal operation
1
TJ > 150°C, power blocks disabled
0
IO < IOMAX, normal operation
1
IO > IOMAX, Overload Protection triggered
0/1
Note:
Values are typical unless otherwise specified.
7.5
Power-on I²C interface reset
These bits are set to 1 if the relative parameter
is out of the specification limits.
The I²C interface built in the LNBH24 is automatically reset at power-ON. As long as the VCC
stays below the undervoltage lockout (UVL) threshold (6.7 V), the interface will not respond
to any I²C command and the system registers (SR) are initialized to all zeroes, thus keeping
the power blocks disabled. Once the VCC rises above 7.3 V typ. The I²C interface becomes
operative and the SRs can be configured by the main MCU. This is due to 500 mV
hysteresis provided in the UVL threshold to avoid false re-triggering of the power-ON reset
circuit.
7.6
Address pin
For each section of the LNBH24 it is possible to select two I²C interface addresses by
means of the relevant ADDR pin. The ADDR pins are TTL-compatible and can be set as per
address pins characteristics Table 10.
7.7
DiSEqC™ implementation for each section A/B
LNBH24 helps system designer to implement the bi-directional DiSEqC 2.0 protocol by
allowing easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH24
and the main MCU the PWK data is exchanged using logic levels that are compatible with
both 3.3 V and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN
and DSQOUT, in order to maintain the timing relationships between the PWK data and the
PWK modulation as accurate as possible. These two pins should be directly connected to
two I/O pins of the MCU, thus leaving to the firmware the task of encoding and decoding the
PWK data in accordance with the DiSEqC protocol. Full compliance of the system to the
specification is thus not implied by the bare use of the LNBH24. The system designer should
also take in consideration the bus hardware requirements, which can be simply
accomplished by the R-L termination connected on the VOUT pins of the LNBH24, as shown
in the typical application circuits in Figure 4. To avoid any losses due to the R-L impedance
during the tone transmission, LNBH24 has dedicated Tone output (VoTX) that is connected
after the filter and must be enabled by setting the TTX function to HIGH only during the tone
transmission (see DiSEqC 2.0 implementation in sections 2.2 and 2.3). Also unidirectional
DiSEqC 1.x and non-DiSEqC system need this termination connected through a bypass
capacitor and after an R-L filter with 15 Ω in parallel with a 220 µH-270 µH inductor.
However, there is no need for tone decoding, so the DETIN and DSQOUT pins can be left
connected to GND.
18/30
LNBH24
8
Electrical characteristics
Electrical characteristics
Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ, DSQIN=LOW, VI = 12 V, IOUT =
50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VOUT=VoRX pin
voltage. See software description section for I²C access to the system register.
Table 8.
Symbol
VIN
IIN
VOUT
Electrical characteristics of sections A/B
Parameter
Supply voltage
Supply current
Output voltage
Test conditions
Min.
Typ.
Max.
Unit
8
12
15
V
Both sections A and B enabled,
IOUT=0
20
30
Both sections A and B enabled,
EN=TEN=TTX=1, IOUT=0
50
70
EN=0
6
AUX=1; IOUT=50mA
22
IOUT=750mA, VSEL=LLC=1
VSEL=1, IOUT=750mA
VSEL=0, IOUT=750mA
LLC=0
17.8
18.5
19.2
LLC=1
18.8
19.5
20.2
LLC=0
12.8
13.4
14
LLC=1
13.8
14.4
15
VSEL=0
5
40
VSEL=1
5
60
VOUT
Line regulation
VOUT
Load regulation
VSEL=0 or 1, IOUT from 50 to750mA
13/18V Rise and Fall
transition time by VCTRL pin
VSEL=LLC=1, VCTRL from LOW to
HIGH and vice versa, IOUT from 6 to
450mA, CO from 10 to 330nF
13/18
TR - T F
IMAX
Output current limiting
VIN=8 to 15V
mA
V
mV
200
575
mV
µs
RSEL=11KΩ
750
1000
RSEL= 22KΩ
300
600
mA
Output short circuit current
VSEL=0/1, AUX=0/1
1000
TOFF
Dynamic overload protection
OFF time
PCL=0, Output shorted
900
TON
Dynamic overload protection
ON time
PCL=0, Output shorted
FTONE
Tone frequency
DSQIN=HIGH or TEN=1, TTX=1
20
22
24
kHz
ATONE
Tone amplitude
DSQIN=HIGH or TEN=1, TTX=1
IOUT from 0 to750mA
COUT from 0 to 750nF
0.4
0.65
0.9
VPP
DTONE
Tone duty cycle
DSQIN=HIGH or TEN=1, TTX=1
43
50
57
%
Tone rise or fall time
DSQIN=HIGH or TEN=1, TTX=1
5
8
15
µs
20
22
24
kHz
ISC
mA
ms
tr, tf
FEXTM
EffDC-DC
EXTM frequency
VEXTM-H =3.3V, VEXTM-L =0V,
DC-DC converter efficiency
IOUT=750mA
TOFF/10
(1)
93
%
19/30
Electrical characteristics
Table 8.
Symbol
FSW
LNBH24
Electrical characteristics of sections A/B (continued)
Parameter
Test conditions
Min.
DC-DC converter switching
frequency
Tone detector frequency
capture range
VDETIN
Tone detector input amplitude Sine wave signal, 22 kHz
ZDETIN
Tone detector input
impedance
DSQOUT pin logic LOW
IOZ
Max.
220
FDETIN
VOL
Typ.
0.4VPP sine wave(2)
19
22
0.3
kHz
25
kHz
1.5
VPP
150
V
DSQOUT pin leakage current DETIN Tone absent, VOH=6V
10
µA
VIL
DSQIN,TTX,13/18, EXTM pin
logic Low
0.8
V
VIH
DSQIN,TTX,13/18, EXTM pin
logic High
IIH
DSQIN,TTX,13/18, EXTM pin
VIH=5V
input current
15
Output backward current
-6
TSHDN
ΔTSHDN
0.3
kΩ
0.5
IOBK
DETIN Tone present, IOL=2mA
Unit
2
EN=0, VOBK=21V
V
µA
-15
mA
Thermal shut-down threshold
150
°C
Thermal shut-down
hysteresis
15
°C
1. External signal frequency range in which the EXTM function is guaranteed.
2. Frequency range in which the DETIN function is guaranteed. The VPP level is intended on the LNBOUT (before the C12A/B
capacitor. See typical application circuit in Figure 4).
TJ from 0 to 85 °C, VI = 12 V.
Table 9.
Symbol
I²C electrical characteristics
Parameter
Test conditions
VIL
LOW Level input voltage
SDA, SCL
VIH
HIGH Level input voltage
SDA, SCL
IIN
Input current
SDA, SCL, VI = 0.4 to 4.5 V
Low level output voltage
SDA (open drain), IOL = 6 mA
Maximum clock frequency
SCL
VOL
FMAX
20/30
Min.
Typ.
Max.
Unit
0.8
V
2
-10
400
V
10
µA
0.6
V
kHz
LNBH24
Electrical characteristics
TJ from 0 to 85 °C, VI = 12 V.
Table 10.
Symbol
Address pins characteristics
Parameter
Test condition
Min.
Typ.
Max.
Unit
Section “A” address selection
VADDR-A1
"0001000(R/W)" Address pin R/W bit determines the transmission
voltage range for section A
mode: read (R/W=1) write (R/W=0)
0
0.8
V
VADDR-A2
"0001001(RW)" Address pin
voltage range for section A
2
5
V
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
Section “B” address selection
VADDR-B1
"0001010(R/W)" Address pin R/W bit determines the transmission
voltage range for section B
mode: read (R/W=1) write (R/W=0)
0
0.8
V
VADDR-B2
"0001011(RW)" Address pin
voltage range for section B
2
5
V
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
Refer to the typical application circuit in Figure 4, TJ from 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ, DSQIN=LOW, VI=12 V, IO = 50
mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO=VoRX pin voltage.
See software description section for I²C access to the system register.
Table 11.
Symbol
Output voltage diagnostic (VMON bit) characteristics of sections A/B
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTH-L
Diagnostic low threshold at
VO=13.4V typ.
EN=1, VSEL=0
LLC=0
85
90
95
%
VTH-L
Diagnostic low threshold at
VO=18.5V typ.
EN=VSEL=1
LLC=0
84
90
96
%
NB: if the output voltage is lower than the min. value the VMON I²C bit is set to 1.
When VSEL=0: If VMON=0 then VO>85% of VO typ.; If VMON=1 then VO84% of VO typ.; If VMON=1 then VO
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