LNBH26LSPQR

LNBH26LS Dual LNBS supply and control IC with step-up and I²C interface Datasheet - production data   LNB short-circuit dynamic protection +/- 4 kV ESD tolerant on output power pins Applications    STB satellite receivers TV satellite receivers PC card satellite receivers Description Features         Complete interface between then LNB and I²C bus Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A) Selectable output current limit by external resistor Compliant with main satellite receiver output voltage specification (8 programmable levels) Accurate built-in 22 kHz tone generator suits widely accepted standards 22 kHz tone waveform integrity guaranteed also at no load condition Low drop post regulator and high efficiency step-up PWM with integrated power NMOS allowing low power losses Overload and overtemperature internal protection with I²C diagnostic bits April 2015 Intended for analog and digital dual satellite receiver/Sat-TV, Sat-PC cards, the LNBH26LS is a monolithic voltage regulator and IC interface, assembled in QFN24 (4x4 mm) specifically designed to provide the 13/18 V power supply and the 22 kHz tone signaling to the LNB downconverter in the antenna dishes or to the multiswitch box. In this application field, it offers a complete solution for dual tuner satellite receivers with extremely low component count, low power dissipation together with simple design and I²C standard interfacing. Table 1: Device summary Order code Package Packing LNBH26LSPQR QFN24 (4x4 mm) Tape and reel DocID025504 Rev 2 This is information on a product in full production. 1/35 www.st.com Contents LNBH26LS Contents 1 Block diagram.................................................................................. 6 2 Application information (valid for each section A/B) .................... 7 2.1 DISEQC™ data encoding (DSQIN pin) ............................................. 7 2.2 Data encoding by external 22 kHz tone TTL signal ........................... 7 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin ...................................................................................................... 8 2.4 Output current limit selection ............................................................. 8 2.5 Output voltage selection .................................................................... 8 2.6 Diagnostic and protection functions .................................................. 8 2.7 Surge protection and TVS diodes ..................................................... 9 2.8 Power-on I²C interface reset and undervoltage lockout .................... 9 2.9 PNG: input voltage minimum detection ............................................. 9 2.10 COMP: boost capacitors and inductor ............................................... 9 2.11 OLF: overcurrent and short-circuit protection and diagnostic .......... 10 2.12 OTF: thermal protection and diagnostic .......................................... 10 3 4 Pin configuration ........................................................................... 11 Maximum ratings ........................................................................... 14 5 Typical application circuits........................................................... 15 6 I²C bus interface ............................................................................ 17 7 8 6.1 Data validity..................................................................................... 17 6.2 Start and stop condition .................................................................. 17 6.3 Byte format ...................................................................................... 17 6.4 Acknowledge ................................................................................... 17 6.5 Transmission without acknowledge ................................................. 17 I²C interface protocol .................................................................... 19 7.1 Write mode transmission ................................................................. 19 7.2 Read mode transmission ................................................................ 20 7.3 Data registers .................................................................................. 21 7.4 Status registers ............................................................................... 23 Electrical characteristics .............................................................. 25 8.1 9 2/35 Output voltage selection .................................................................. 27 Package information ..................................................................... 29 DocID025504 Rev 2 LNBH26LS 10 Contents 9.1 QFN24L (4x4 mm) package information ......................................... 30 9.2 QFN24L (4x4 mm) packing information .......................................... 32 Revision history ............................................................................ 34 DocID025504 Rev 2 3/35 List of tables LNBH26LS List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description ............................................................................................................................ 12 Table 3: Absolute maximum ratings ......................................................................................................... 14 Table 4: Thermal data ............................................................................................................................... 14 Table 5: LNBH26LS DiSEqC 1.x bill of material ....................................................................................... 16 Table 6: DATA 1 (read/write register. Register address = 0X2) ............................................................... 21 Table 7: DATA 2 (read/write register. Register address = 0X3) ............................................................... 21 Table 8: DATA 3 (read/write register. Register address = 0X4) ............................................................... 22 Table 9: DATA 4 (read/write register. Register address = 0X5) ............................................................... 23 Table 10: STATUS 1 (read register. Register address = 0X0) ................................................................. 23 Table 11: STATUS 2 (read register. Register address = 0X1) ................................................................. 24 Table 12: Electrical characteristics of section A/B .................................................................................... 25 Table 13: Output voltage selection table (data1 register, write mode) ..................................................... 27 Table 14: I²C electrical characteristics ...................................................................................................... 27 Table 15: Address pin characteristics ....................................................................................................... 28 Table 16: QFN24L (4x4 mm) package mechanical data .......................................................................... 31 Table 17: QFN24L (4x4 mm) tape mechanical data ................................................................................. 32 Table 18: QFN24L (4x4 mm) reel mechanical data .................................................................................. 33 Table 19: Document revision history ........................................................................................................ 34 4/35 DocID025504 Rev 2 LNBH26LS List of figures List of figures Figure 1: Block diagram .............................................................................................................................. 6 Figure 2: Tone enable and disable timing (using an external waveform) ................................................... 7 Figure 3: Tone enable and disable timing (using envelope signal) ............................................................ 8 Figure 4: Surge protection circuit ................................................................................................................ 9 Figure 5: Pin connections (top view) ......................................................................................................... 11 Figure 6: LNBH26LS DiSEqC 1.X typical application circuit .................................................................... 15 Figure 7: Data validity on the I²C bus ....................................................................................................... 18 Figure 8: Timing diagram of I²C bus ......................................................................................................... 18 Figure 9: Acknowledge on the I²C bus...................................................................................................... 18 Figure 10: Example of writing procedure starting with first data address 0x2 .......................................... 19 Figure 11: Example of reading procedure starting with first status address 0X0 ..................................... 20 Figure 12: QFN24L (4x4 mm) package outline ........................................................................................ 30 Figure 13: QFN24L (4x4 mm) recommended footprint ............................................................................. 31 Figure 14: QFN24L (4x4 mm) tape outline ............................................................................................... 32 Figure 15: QFN24L (4x4 mm) reel outline ................................................................................................ 33 DocID025504 Rev 2 5/35 Block diagram 1 LNBH26LS Block diagram Figure 1: Block diagram 6/35 DocID025504 Rev 2 LNBH26LS 2 Application information (valid for each section A/B) Application information (valid for each section A/B) This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (VUP) that let the integrated LDO post-regulator (generating the 13 V/18 V LNB output voltages plus the 22 kHz DiSEqC tone) work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at VUP VOUT = 1 V typ.). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V typically). The step-up converter soft-start function reduces the in-rush current during startup. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. to switch from 0 to 18 V. 2.1 DISEQC™ data encoding (DSQIN pin) The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC™ standards, and can be activated in 3 different ways: 1) By an external 22 kHz source DiSEqC™ data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1. 2) By an external DiSEqC™ data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. 3) Through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled high and the EXTM bit set to “0”. 2.2 Data encoding by external 22 kHz tone TTL signal In order to improve design flexibility, an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”. The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the LNBH26LS integrated tone generator. The output tone waveforms are internally controlled by the LNBH26LS tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26LS activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired. Refer to Figure 2: "Tone enable and disable timing (using an external waveform)". Figure 2: Tone enable and disable timing (using an external waveform) DocID025504 Rev 2 7/35 Application information (valid for each section A/B) 2.3 LNBH26LS Data encoding by external DiSEqC envelope control through the DSQIN pin If an external DiSEqC™ envelope source is available, the internal 22 kHz generator can be activated during the tone transmission by connecting the DiSEqC™ envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. In this manner, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept high the internal control circuit activates the 22 kHz tone output. The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired, refer to Figure 3: "Tone enable and disable timing (using envelope signal)"). Figure 3: Tone enable and disable timing (using envelope signal) 2.4 Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit as per below equation: Equation 1: with ISET = 0, where RSEL is the resistor connected between ISEL and GND expressed in kW and ILIM(typ.) is the typical current limit threshold expressed in mA. ILIM can be set up to 750 mA for each channel. However, do not exceed, for a long period of time, a total amount of current of 1 A from both sections (IOUT-A + IOUT-B < 1 A) in order to avoid the overtemperature protection triggering and to thoroughly validate the PCB layout thermal management in real application environment conditions. 2.5 Output voltage selection Each linear regulator channel output voltage level can be easily programmed to accomplish application specific requirements, using 4 + 4 bits of an internal DATA1 register, see Section 7.3: "Data registers" and Table 13: "Output voltage selection table (data1 register, write mode)" for exact programmable values. Register writing is accessible via the I²C bus. 2.6 Diagnostic and protection functions The LNBH26LS has 4 diagnostic internal functions provided via the I²C bus, by reading 4 bits on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that is, no failure detected), set to low. One diagnostic bit is dedicated to the 8/35 DocID025504 Rev 2 LNBH26LS Application information (valid for each section A/B) overtemperature (OTF), and two bits (one per section) are dedicated to overcurrent (OLFA, OLF-B). One bit is dedicated to the input voltage power not good function (PNG). Once the OTF bit (or OLF-A, OLF-B or PNG) has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is performed. 2.7 Surge protection and TVS diodes Each LNBH26LS device section is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect each section of STB output circuits where the LNBH26LS and other devices are electrically connected to the antenna cable. Figure 4: Surge protection circuit GIPD1311131146LM For this purpose the use of LNBTVSxx surge protection diodes specifically designed by ST is recommended. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details). 2.8 Power-on I²C interface reset and undervoltage lockout The I²C interface built into the LNBH26LS is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all data register bits are initialized to zero, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor. 2.9 PNG: input voltage minimum detection When the input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1”. Refer to the Table 14: "I²C electrical characteristics" for threshold details. 2.10 COMP: boost capacitors and inductor The DC-DC converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacitors (VUP pin). For this purpose, one I²C bit in the DATA 4 register (see COMP not found) can be set to “1” or “0” as follows: COMP = 0 for electrolytic capacitors COMP = 1 for ceramic capacitors DocID025504 Rev 2 9/35 Application information (valid for each section LNBH26LS A/B) For recommended DC-DC capacitor and inductor values refer to Section 5: "Typical application circuits" and to the BOM in Table 5: "LNBH26LS DiSEqC 1.x bill of material" . 2.11 OLF: overcurrent and short-circuit protection and diagnostic In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. The shortcircuit current protection can be set either statically (simple current clamp) or dynamically through the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set to low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T ON time 90 ms and after that, the output is set as shutdown for a T OFF time of typically 900 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1”. After this time has elapsed, the involved output is resumed for a time T ON. At the end of TON, if the overload is still detected, the protection circuit cycles again through T OFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to low after the register reading. Typical T ON+ TOFF time is 990 ms and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, ensuring an excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL =1) and, then, switching to the dynamic mode (PCL = 0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is performed. After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register. If OLR=1, all VSEL bits, corresponding to the involved section, are reset to “0” and the LNB section output (VOUT pin) is disabled. To re-enable the output stage, the VSEL bits must be set again by the microprocessor and the OLF bit is reset to “0” after a register reading operation. If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation. 2.12 OTF: thermal protection and diagnostic The LNBH26LS is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and both linear regulators are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register. If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (VOUT pins) are disabled. To re-enable the output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation. If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation. 10/35 DocID025504 Rev 2 LNBH26LS 3 Pin configuration Pin configuration Figure 5: Pin connections (top view) DocID025504 Rev 2 11/35 Pin configuration LNBH26LS Table 2: Pin description Pin n° Symbol Name 3 LX-A NMOS drain Channel A, integrated N-channel power MOSFET drain. 4 P-GND Power ground DC-DC converter power ground. To be connected directly to the exposed pad. 5 LX-B NMOS drain Channel B, integrated N-channel power MOSFET drain. 6 ADDR Address setting 7 SCL Serial clock Clock from I²C bus. 8 SDA Serial data Bi-directional data from/to I²C bus. Two I²C bus addresses available by setting the ADDRESS pin level voltage. See Table 15: "Address pin characteristics". The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold. Refer to Section 2: "Application information (valid for each section A/B)". The RSEL resistor defines the same current limit for both channels (A and B). 9 ISEL Current selection for channel A and B 1, 2, 13, 14, 15, 18, 19, 23 GND Analog ground Analog circuit ground. To be connected directly to the exposed pad. 10 NC Not internally connected Not internally connected pin. Set floating if not used. VUP-B Channel B step-up voltage Input of channel B linear post-regulator. The voltage on this pin is monitored by the internal channel B step-up controller to keep a minimum dropout across the linear pass transistor. VOUT-B Channel B, LNB output port Output of channel B integrated very low drop linear regulator. Refer to Table 13: "Output voltage selection table (data1 register, write mode)" for voltage selection and description. Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to an external current or voltage sources may cause permanent damage to the device. 11 12 16 BYP Bypass capacitor 17 VCC Supply input VOUT-A Channel A, LNB output port Output of channel A integrated very low drop linear regulator. Refer to Table 13: "Output voltage selection table (data1 register, write mode)" for voltage selection and description. VUP-A Channel A step-up voltage Input of channel A linear post-regulator. The voltage on this pin is monitored by the internal channel A step-up controller to keep a minimum dropout across the linear pass transistor. 20 21 12/35 Pin function 8 to 16 V IC DC-DC power supply. DocID025504 Rev 2 LNBH26LS Pin configuration Pin n° 22 Symbol DSQIN-A Name Pin function DSQIN for DiSEqC envelope input or external 22 KHz TTL input It is intended for channel A 22 kHz tone control. It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-A I²C bit setting as follows: If EXTM-A=0, TEN-A=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH26LS uses this code to modulate the internally generated 22 kHz carrier. If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which activate the 22 kHz tone output, refer to Section 2.2: "Data encoding by external 22 kHz tone TTL signal". Pull up high if the tone output is activated only by the TEN-A I²C bit. It is intended for channel B 22 kHz tone control. It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-B I²C bit setting as follows: If EXTM-B=0, TEN-B=1: it accepts the DiSEqC envelope code from the main microcontroller. The LNBH26LS uses this code to modulate the internally generated 22 kHz carrier. If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals which activate the 22 kHz tone output, refer to Section 2.2: "Data encoding by external 22 kHz tone TTL signal". Pull up high if the tone output is activated by TEN-B I²C bit only. 24 DSQIN-B DSQIN for DiSEqC envelope input or external 22 KHz TTL input Epad Epad Exposed pad To be connected with power grounds and to the ground layer through vias to dissipate the heat. DocID025504 Rev 2 13/35 Maximum ratings 4 LNBH26LS Maximum ratings Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC power supply input voltage pins -0.3 to 20 V VUP DC input voltage -0.3 to 40 V IOUT Output current Internally limited mA VOUT DC output pin voltage -0.3 to 40 V VI Logic input pin voltage (SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V LX LX input voltage -0.3 to 30 V VBYP Internal reference pin voltage -0.3 to 4.6 V ISEL Current selection pin voltage -0.3 to 3.5 V TSTG Storage temperature range -50 to 150 °C Operating junction temperature range -25 to 125 °C TJ ESD ESD rating with human body model (HBM) all pins, unless power output pins 2 ESD rating with human body model (HBM) for power output pins 4 kV Table 4: Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junction-case 2 °C/W RthJA Thermal resistance junction-ambient with device soldered on 2s2p 4-layer PCB provided with thermal vias below the exposed pad 40 °C/W Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. 14/35 DocID025504 Rev 2 LNBH26LS 5 Typical application circuits Typical application circuits Figure 6: LNBH26LS DiSEqC 1.X typical application circuit D2-A LNBOUT- A 21 D1- A L1-A VOUT- A 20 VUP-A LNBH26LS C2-A C3-A 3 LX-A 9 ISEL 16 Byp C5-A D3-A R1 (RSEL) C7 Vin 12 V 17 DSQIN -A DSQIN -B ADDR Vcc C4 C1 L1-B I 2C Bus{ 7 SDA SCL 5 LX-B 11 VUP- B 8 DiSEqC 22KHz 22 Tone enable control or 24 DiSEqC Envelope 6 TTL TTL D1-B VOUT-B 12 A- GND P-GND C2-B C3-B 4 LNBOUT-B 15 C5-B D3-B D2-B GIPG201517041137LM DocID025504 Rev 2 15/35 Typical application circuits LNBH26LS Table 5: LNBH26LS DiSEqC 1.x bill of material Component R1 (RSEL) SMD resistor. Refer to Table 12: "Electrical characteristics of section A/B" and ISEL pin description in Table 2: "Pin description" . C1 > 25 V electrolytic capacitor, 100 µF or higher is suitable or > 25 V ceramic capacitor, 10 µF or higher is suitable. C2 With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable or with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is suitable. C3 From 470 nF to 2.2 µF ceramic capacitor placed as closer as possible to VUP pins. Higher values allow lower DC-DC noise. C5 From 100 nF to 220 nF ceramic capacitor placed as closer as possible to VOUT pins. Higher values allow lower DC-DC noise. C4, C7 16/35 Notes 220 nF ceramic capacitors. To be placed as closer as possible to VOUT pin. D1 STPS130A or similar Schottky diode. D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier. D3 BAT54, BAT43, 1N5818, or any low power Schottky diode with I F (AV) > 0.2 A, VRRM > 25 V, VF < 0.5 V. To be placed as closer as possible to VOUT pin. L1 With COMP=0, use 10 µH inductor with ISAT > IPEAK where IPEAK is the boost converter peak current, or with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with ISAT > IPEAK where IPEAK is the boost converter peak current. DocID025504 Rev 2 LNBH26LS 6 I²C bus interface I²C bus interface Data transmission from the main microprocessor to the LNBH26LS, and vice versa, takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 6.1 Data validity As shown in Figure 7: "Data validity on the I²C bus", the data on the SDA line must be stable during the high semi-period of the clock. The high and low state of the data line can only change when the clock signal on the SCL line is low. 6.2 Start and stop condition As shown in Figure 8: "Timing diagram of I²C bus", a start condition is a transition from high to low of the SDA line while SCL is high. The stop condition is a transition from low to high of the SDA line while SCL is high. A stop condition must be sent before than each start condition. 6.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is the first to be transferred. 6.4 Acknowledge The master (microprocessor) puts a resistive high level on the SDA line during the acknowledge clock pulse, see Figure 9: "Acknowledge on the I²C bus". The peripheral (LNBH26LS), which acknowledges, must pull down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The peripheral, which has been addressed, must generate acknowledge after the reception of each byte, otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The LNBH26LS doesn’t generate acknowledge if the VCC supply is below the undervoltage lockout threshold (4.7 V typ.). 6.5 Transmission without acknowledge If the detection of LNBH26LS acknowledge is not necessary, the microprocessor can use a simpler transmission; it simply waits for one clock without checking the slave acknowledging, and sends the new data. This approach has less protection in case of misworking and decreases noise immunity. DocID025504 Rev 2 17/35 I²C bus interface LNBH26LS Figure 7: Data validity on the I²C bus Figure 8: Timing diagram of I²C bus Figure 9: Acknowledge on the I²C bus 18/35 DocID025504 Rev 2 LNBH26LS I²C interface protocol 7 I²C interface protocol 7.1 Write mode transmission The LNBH26LS interface protocol is made up of:        A start condition (S) A chip address byte with the LSB bit R/W = 0 A register address (internal address of the first register to be accessed) A sequence of data (byte to write to the addressed internal register + acknowledge) The following bytes, if any, to be written to successive internal x A stop condition (P), the transfer lasts until a stop bit is encountered The LNBH26LS, as slave, acknowledges every byte transfer Figure 10: Example of writing procedure starting with first data address 0x2 ACK = acknowledge S = start P = stop R/W = 1/0, read/write bit X = 0/1, set the values to select the chip address, see Table 13: "Output voltage selection table (data1 register, write mode)" for pin selection and to select the register address, see Table 6: "DATA 1 (read/write register. Register address = 0X2)" and Table 10: "STATUS 1 (read register. Register address = 0X0)". The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped by the master by sending a stop condition after any acknowledge bit. DocID025504 Rev 2 19/35 I²C interface protocol 7.2 LNBH26LS Read mode transmission In read mode the byte sequence must be as follows:        A start condition (S) A chip address byte with the LSB bit R/W=0 The register address byte of the internal first register to be accessed A stop condition (P) A new master transmission with the chip address byte and the LSB bit R/W=1 After the acknowledge, the LNBH26LS starts sending the addressed register content. As long as the master keeps the acknowledge low, the LNBH26LS transmits the next address register byte content The transmission is terminated when the master sets the acknowledge high with a following stop bit Figure 11: Example of reading procedure starting with first status address 0X0 ACK = acknowledge S = start P = stop R/W = 1/0, read/write bit X = 0/1, set the values to select the chip address, see Table 15: "Address pin characteristics" for pin selection and to select the register address, see Table 6: "DATA 1 (read/write register. Register address = 0X2)". The reading procedure can start from any register address (STATUS 1, 2 or DATA 1..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped by the master by sending a stop condition after any acknowledge bit. 20/35 DocID025504 Rev 2 LNBH26LS 7.3 I²C interface protocol Data registers The DATA 1..4 registers can be addressed both to write and read mode. In read mode they return the last writing byte status received in the previous write transmission. The following tables provide the register address values of DATA 1..4 and a function description of each bit. Table 6: DATA 1 (read/write register. Register address = 0X2) Bit Name CH Bit 0 (LSb) VSEL1-A 0/1 Bit 1 VSEL2-A 0/1 Bit 2 VSEL3-A Bit 3 VSEL4-A 0/1 Bit 4 VSEL1-B 0/1 Bit 5 VSEL2-B 0/1 Bit 6 VSEL3-B Bit 7 (MSb) VSEL4-B A B Value Description Channel A output voltage selection bits refer to Table 13: "Output voltage selection table (data1 register, write mode)" 0/1 Channel B output voltage selection bits refer to Table 13: "Output voltage selection table (data1 register, write mode)" 0/1 0/1 N/A = reserved bit. All bits reset to “0” at power-on. Table 7: DATA 2 (read/write register. Register address = 0X3) Bit Bit 0 (LSb) Bit 1 Name CH TEN A N/A A Bit 2 N/A Bit 4 TEN-B N/A B Bit 6 Bit 7 (MSb) 22 kHz tone enabled. Tone output controlled by the DSQIN pin 0 22 kHz tone output disabled 0 Reserved. Keep to “0” 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal 0 Reserved. Keep to “0” 1 22 kHz tone enabled. Tone output controlled by the DSQIN pin 0 22 kHz tone output disabled 0 Reserved. Keep to “0” 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal 0 Reserved. Keep to “0” EXTM-B N/A Description 1 EXTM-A Bit 3 Bit 5 Value N/A = reserved bit. All bits reset to “0” at power-on. DocID025504 Rev 2 21/35 I²C interface protocol LNBH26LS Table 8: DATA 3 (read/write register. Register address = 0X4) Bit Name CH Bit 0 (LSb) N/A 0 Reserved. Keep to “0” Bit 1 N/A 0 Reserved. Keep to “0” Bit 2 PCL-A 1 Pulsed (dynamic) LNB output current limiting is deactivated 0 Pulsed (dynamic) LNB output current limiting is active A Value Description Bit 3 N/A 0 Reserved. Keep to “0” Bit 4 N/A 0 Reserved. Keep to “0” Bit 5 N/A 0 Reserved. Keep to “0” Bit 6 PCL-B 1 Pulsed (dynamic) LNB output current limiting is deactivated 0 Pulsed (dynamic) LNB output current limiting is deactivated 0 Reserved. Keep to “0” B Bit 7 (MSb) N/A N/A = reserved bit. All bits reset to “0” at power-on. 22/35 DocID025504 Rev 2 LNBH26LS I²C interface protocol Table 9: DATA 4 (read/write register. Register address = 0X5) Bit Name CH Value Bit 0 (LSb) N/A - 0 Reserved. Keep to 0 Bit 1 N/A - 0 Reserved. Keep to 0 Bit 2 N/A - 0 Reserved. Keep to 0 1 In case of overload protection activation (OLF=1), all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0) 0 In case of overload protection activation (OLF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overload condition is removed (OLF=0) with the previous VSEL bit setting Bit 3 A/B Bit 4 N/A - 0 Reserved. Keep to 0 Bit 5 N/A - 0 Reserved. Keep to 0 1 If thermal protection is active (OTF=1), all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=0) 0 In case of thermal protection activation (OTF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=0) with the previous VSEL bit setting - 1 DC-DC converter compensation: set to use very low E.S.R. capacitors or ceramic caps on VUP pin - 0 DC-DC converter compensation: set to use standard electrolytic capacitors on VUP pin Bit 6 Bit 7 (MSB) 7.4 OLR Description THERM A/B COMP Status registers The STATUS 1, 2 registers can only be addressed to read mode and provide the diagnostic functions described in the following tables. Table 10: STATUS 1 (read register. Register address = 0X0) Bit Bit 0 (LSb) Bit 1 Name OLF-A OLF-B CH Value Description 1 VOUT pin overload protection has been triggered (IOUT > I LIM). Refer to Table 8: "DATA 3 (read/write register. Register address = 0X4)" for the overload operation and PCL settings 0 No overload protection has been triggered to the VOUT pin (IOUT < ILIM) 1 VOUT pin overload protection has been triggered (IOUT > I LIM). Refer to Table 8: "DATA 3 (read/write register. Register address = 0X4)" for the overload operation and PCL settings 0 No overload protection has been triggered to VOUT pin (IOUT < I LIM) A B DocID025504 Rev 2 23/35 I²C interface protocol LNBH26LS Bit Name CH Value Bit 2 N/A - - Reserved Bit 3 N/A - - Reserved Bit 4 N/A - - Reserved Bit 5 N/A - - Reserved 1 Junction overtemperature is detected, TJ > 150 °C (typ.). See also THERM bit setting in Table 9: "DATA 4 (read/write register. Register address = 0X5)". 0 Junction overtemperature not detected, TJ < 135 °C (typ.). TJ is below thermal protection threshold 1 Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 12: "Electrical characteristics of section A/B" 0 Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 12: "Electrical characteristics of section A/B" Bit 6 OTF Bit 7 (MSb) A/B PNG A/B Description N/A = reserved bit. All bits reset to “0” at power-on. Table 11: STATUS 2 (read register. Register address = 0X1) Bit Name CH Value Description Bit 0 (LSb) N/A - - Reserved Bit 1 N/A - - Reserved Bit 2 N/A - - Reserved Bit 3 N/A - - Reserved Bit 4 N/A - - Reserved Bit 5 N/A - - Reserved Bit 6 N/A - - Reserved Bit 7 (MSb) N/A - - Reserved N/A = reserved bit. All bits reset to “0” at power-on. 24/35 DocID025504 Rev 2 LNBH26LS 8 Electrical characteristics Electrical characteristics Refer to Section 5: "Typical application circuits" , TJ from 0 to 85 °C, all DATA 1..4 register bits set to 0 unless VSEL1 = 1, RSEL = 11 kΩ, DSQIN = low, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical values are referred to T J = 25 °C. VOUT = VOUT pin voltage. See software description section for Section 6: "I²C bus interface" and Section 7: "I²C interface protocol" . Table 12: Electrical characteristics of section A/B Symbol VIN IIN Parameter Supply voltage Test conditions (1) Supply current Min. Typ. Max. Unit 8 12 16 V Both sections A and B enabled, IOUT = 0 mA 12 22 kHz tone enabled (TEN-A/B = 1, DSQINA/B = high), IOUT = 0 mA 19 Both sections A and B set in standby: VSEL1=VSEL2= VSEL3= VSEL4=0 2 VOUT Output voltage total accuracy Valid at any VOUT selected level VOUT Line regulation VIN = 8 to 16 V VOUT Load regulation IOUT from 50 to 500 mA mA -3.5 75 +3.5 % 40 mV 100 ILIM Output current limiting thresholds RSEL = 15 kΩ 500 750 RSEL = 20 kΩ 350 550 ISC Output short-circuit current RSEL = 15 kΩ SS Soft-start time SS mA 350 mA VOUT from 0 to 13 V 4 ms Soft-start time VOUT from 0 to 18 V 6 ms T13-18 Soft transition rise time VOUT from 13 to 18 V 1.5 ms T18-13 Soft transition fall time VOUT from 18 to 13 V 1.5 ms TOFF Dynamic overload protection OFF time PCL = 0, output shorted 900 ms TON Dynamic overload protection ON time PCL = 0, output shorted TOFF/10 Tone amplitude DSQIN = high, EXTM=0, TEN=1 IOUT from 0 to 500 mA CBUS from 0 to 750 nF ATONE DocID025504 Rev 2 0.55 0.675 0.8 VPP 25/35 Electrical characteristics Symbol LNBH26LS Parameter Test conditions DSQIN = high, EXTM=0, TEN=1 Min. Typ. Max. Unit 20 22 24 kHz FTONE Tone frequency DTONE Tone duty cycle 43 50 57 % tr, tf Tone rise or fall (2) time 5 8 15 µs EffDC/DC FSW UVLO VLP DC-DC converter efficiency IOUT = 500 mA 93 % 440 kHz UVLO threshold rising 4.8 V UVLO threshold falling 4.7 VLP threshold rising 7.2 VLP threshold falling 6.7 DC-DC converter switching frequency Undervoltage lockout thresholds Low power diagnostic (LPD) thresholds V VIL DSQIN, pin logic low VIH DSQIN, pin logic high IIH DSQIN, pin input current VIH = 5 V 15 IOBK Output backward current All VSELx = 0, VOBK = 30 V -3 ISINK Output low-side sink current VOUT forced at VOUT_nom + 0.1 V 70 mA Low-side sink current time-out VOUT forced at VOUT_nom + 0.1 V 10 ms Max. reverse current VOUT forced at VOUT_nom + 0.1 V, after ISINK_TIME-OUT is elapsed 2 mA ISINK_TIMEOUT IREV 0.8 2 V V µA -6 mA TSHDN Thermal shutdown threshold 150 °C DTSHDN Thermal shutdown hysteresis 15 °C Notes: (1) In applications where (VCC - VOUT) > 1.3 V, the increased power dissipation, inside the integrated LDO, must be taken into account in the application thermal management design. (2) 26/35 Guaranteed by design. DocID025504 Rev 2 LNBH26LS 8.1 Electrical characteristics Output voltage selection Each LNBH26LS channel is provided with 8 output voltage levels, (4 levels for 13 V range when VSEL4-A/B=0 and 4 levels for 18 V range when VSEL4-A/B=1) which can be selected through the register data1. The following table shows the output voltage values corresponding to VSELx bit combinations both for channel A and B. If all VSELx are at “0” the device is set in standby mode and the VOUT -A/B are disabled. Table 13: Output voltage selection table (data1 register, write mode) VOUT-A/B pin voltage VSEL 4-A/B VSEL 3-A/B VSEL 2-A/B VSEL 1-A/B 0 0 0 0 0 0 0 1 12.545 13.000 13.455 0 0 1 0 12.867 13.333 13.800 0 0 1 1 13.188 13.667 14.145 0 1 0 0 13.51 14.000 14.490 1 0 0 0 17.515 18.150 18.785 1 0 0 1 17.836 18.483 19.130 1 0 1 0 18.158 18.817 19.475 1 0 1 1 18.48 19.150 19.820 VOUT min. VOUT max. Function VOUT -A/B disabled. The LNBH26LS is set in standby mode 0 TJ from 0 to 85 °C, VI = 12 V. Table 14: I²C electrical characteristics Symbol Parameter Test conditions VIL Low level input voltage SDA, SCL VIH high level input voltage SDA, SCL IIN Input current SDA, SCL, VIN = 0.4 to 4.5 V VOL Low level output (1) voltage FMAX Maximum clock frequency Min. Typ. Max. Unit 0.8 V 2 -10 V 10 µA SDA (open drain), IOL = 6 mA 0.6 V SCL 400 kHz Notes: (1) Guaranteed by design. DocID025504 Rev 2 27/35 Electrical characteristics TJ from 0 to 85 °C, VI = 12 V. LNBH26LS Table 15: Address pin characteristics Symbol 28/35 Parameter Test conditions Min. Typ. Max. Unit VADDR-1 “0001000(R/W)” address pin voltage range R/W bit determines the transmission mode: read (R/W=1) write (R/W=0) 0 0.8 V VADDR-2 “0001001(R/W)” address pin voltage range R/W bit determines the transmission mode: read (R/W=1) write (R/W=0) 2 5 V DocID025504 Rev 2 LNBH26LS 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID025504 Rev 2 29/35 Package information 9.1 LNBH26LS QFN24L (4x4 mm) package information Figure 12: QFN24L (4x4 mm) package outline 30/35 DocID025504 Rev 2 LNBH26LS Package information Table 16: QFN24L (4x4 mm) package mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 3.90 4.00 4.10 D2 2.55 2.70 2.80 E 3.90 4.00 4.10 E2 2.55 2.70 2.80 e 0.45 0.50 0.55 L 0.25 0.35 0.40 Figure 13: QFN24L (4x4 mm) recommended footprint DocID025504 Rev 2 31/35 Package information 9.2 LNBH26LS QFN24L (4x4 mm) packing information Figure 14: QFN24L (4x4 mm) tape outline Table 17: QFN24L (4x4 mm) tape mechanical data 32/35 Dim. mm A0 4.35 B0 4.35 K0 1.1 DocID025504 Rev 2 LNBH26LS Package information Figure 15: QFN24L (4x4 mm) reel outline Table 18: QFN24L (4x4 mm) reel mechanical data Dim. R1 R2 R3 Reel 13” 13 330 60 DocID025504 Rev 2 33/35 Revision history 10 LNBH26LS Revision history Table 19: Document revision history Date Revision 04-Dec-2013 1 Initial release. 2 Updated section 2.11. Updated package information section. Changed figure 6. 20-Apr-2015 34/35 Changes DocID025504 Rev 2 LNBH26LS IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID025504 Rev 2 35/35