M48T251Y-70PM1

M48T251Y M48T251V 5.0 or 3.3V, 4096K TIMEKEEPER® SRAM with PHANTOM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ 5.0V OR 3.3V OPERATING VOLTAGE REAL TIME CLOCK KEEPS TRACK OF TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAYS, DATE OF THE MONTH, MONTHS, AND YEARS AUTOMATIC LEAP YEAR CORRECTION VALID UP TO THE YEAR 2100 AUTOMATIC SWITCH-OVER AND DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT VOLTAGES: (VPFD = Power-fail Deselect Voltage): – M48T251Y: 4.25V ≤ VPFD ≤ 4.50V – M48T251V: 2.80V ≤ VPFD ≤ 2.97V FULL 10% VCC OPERATING RANGE OVER 10 YEARS’ DATA RETENTION IN THE ABSENCE OF POWER WATCH FUNCTION IS TRANSPARENT TO RAM OPERATION 512K x 8 NV SRAM DIRECTLY REPLACES VOLATILE STATIC RAM OR EEPROM ) s ( ct Figure 1. 32-pin, DIP Package c u d 32 e t le 1 ) s t( o r P PMDIP32 (PM) o s b O - u d o r P e t e l o s b O February 2005 1/24 M48T251Y, M48T251V TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 32-pin, DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . Signal Names . . DIP Connections Block Diagram . . ................... ................... ................... ................... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....5 .....5 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Memory READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6. Memory WRITE Cycle 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. Memory WRITE Cycle 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Memory AC Characteristics, M48T251Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Memory AC Characteristics, M48T251V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 c u d e t le ) s t( o r P PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 o s b O - Figure 8. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. Phantom Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 11.Phantom Clock Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Phantom Clock AC Characteristics (M48T251Y). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Phantom Clock AC Characteristics (M48T251V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ) s ( ct u d o r P e t e l o s b O MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/24 M48T251Y, M48T251V Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 21 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 3/24 M48T251Y, M48T251V SUMMARY DESCRIPTION The M48T251Y/V TIMEKEEPER® RAM is a 512Kbit x 8 non-volatile static RAM and real time clock organized as 524,288 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solution. In the event of power instability or absence, a self-contained battery maintains the timekeeping operation and provides power for a CMOS static RAM. Control circuitry monitors VCC and invokes write protection to prevent data corruption in the memory and RTC. The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: – a 12-hour mode with an AM/PM indicator; or – a 24-hour mode The M48T251Y/V is a 32-pin (PM) DIP module that integrates the RTC, the battery, and SRAM in one package. The modules are shipped in plastic, anti-static tubes (see Table 14., page 22). Figure 2. Logic Diagram Table 1. Signal Names A0–A18 VCC A0-A18 DQ0-D7 CE M48T251Y M48T251V RST VSS t e l o s b O 4/24 ) s ( ct u d o r P e Reset Input CE Chip Enable OE Output Enable Input AI04237 o r P WE WRITE Enable Input so Data Inputs/Outputs DQ0–DQ7 OE c u d RST e t le WE Address Input b O - VCC Supply Voltage Input VSS Ground ) s t( M48T251Y, M48T251V Figure 3. DIP Connections A18/RST 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 A4 8 M48T251Y M48T251V 26 A9 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 c u d AI04239 Figure 4. Block Diagram e t le XO o s b O XI UPDATE READ CE TIMEKEEPER REGISTER WRITE OE CONTROL LOGIC WE ) s ( ct RST POWER FAIL ACCESS ENABLE SEQUENCE DETECTOR r P e O bs DQ0 I/O BUFFERS A0–A16 SRAM u d o t e l o o r P CLOCK/CALENDAR LOGIC 32.768 Hz CRYSTAL ) s t( DQ0–DQ7 COMPARISON REGISTER DATA INTERNAL VCC VCC POWER-FAIL DETECT LOGIC VBAT AI04238 5/24 M48T251Y, M48T251V OPERATION MODES Table 2. Operating Modes VCC Mode Deselect 4.5V to 5.5V or 3.0V to 3.6V WRITE READ READ CE OE WE DQ7-DQ0 Power VIH X X High-Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High-Z Active Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby Deselect ≤ VSO(1) X X X High-Z Battery Back-Up Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 12., page 20 for details. READ A READ cycle executes whenever WRITE Enable (WE) is high and Chip Enable (CE) is low (see Figure 5.). The distinct address defined by the 19 address inputs (A0-A18) specifies which of the 512K bytes of data is to be accessed. Valid data will be accessed by the eight data output drivers within the specified Access Time (tACC) after the last adFigure 5. Memory READ Cycle ) s t( dress input signal is stable, the CE and OE access times, and their respective parameters are satisfied. When CE tACC and OE tACC are not satisfied, then data access times must be measured from the more recent CE and OE signals, with the limiting parameter being tCO (for CE) or tOE (for OE) instead of address access. c u d e t le o s b O - o r P tRC ADDRESSES (s) tACC ct u d o CE OE r P e t e l o bs O DQ0 - DQ7 Note: WE is high for a READ cycle. 6/24 tOH tCO tOD tOE tCOE tODO tCOE DATA OUTPUT VALID AI04230 M48T251Y, M48T251V WRITE WRITE Mode (see Figure 6.) occurs whenever CE and WE signals are low (after address inputs are stable). The most recent falling edge of CE and WE will determine when the WRITE cycle begins (the earlier, rising edge of CE or WE determines cycle termination). All address inputs must be kept stable throughout the WRITE cycle. WE must be high (inactive) for a minimum recovery time (tWR) before a subsequent cycle is initiated. The OE control signal should be kept high (inactive) during the WRITE cycles to avoid bus contention. If CE and OE are low (active), WE will disable the outputs for Output Data WRITE Time (tODW) from its falling edge. Figure 6. Memory WRITE Cycle 1 tWC ADDRESSES tAW CE tWR c u d tWP WE o r P tOEW e t le tODW ) s t( HIGH IMPEDANCE so tDS DQ0–DQ7 (s) b O - tDH DATA IN STABLE AI04231 t c u Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain in a high impedance state during this period. 3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. d o r P e t e l o s b O 7/24 M48T251Y, M48T251V Figure 7. Memory WRITE Cycle 2 WE = VIH tWC VIH VIL VIH VIL ADDRESSES VIH VIL tAW tWP VIH CE VIL tWR VIL VIH tOEW WE VIL VIL tODW tCOE DQ0–DQ7 tDS VIH VIL tDH DATA IN STABLE e t le c u d VIH VIL o r P ) s t( AI04232 Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. ) s ( ct u d o r P e t e l o s b O 8/24 o s b O - M48T251Y, M48T251V Table 3. Memory AC Characteristics, M48T251Y M48T251Y–70 Parameter(1) Symbol Unit Min Max tAVAV tRC READ Cycle Time tAVQV tACC Access Time 70 ns tELQV tCO Chip Enable Low to Output Valid 70 ns tGLQV tOE Output Enable Low to Output Valid 35 ns tELQX tGLQX tCOE Chip Enable or Output Enable Low to Output Transition 5 ns tAXQX tOH Output Hold from Address Change 5 ns tEHQZ tGHQZ tOD(2) tWLQZ tODW(2) tAVAV tWC tWLWH tELEH 70 ns Chip Enable or Output Enable High to Output Hi-Z 25 ns Output Hi-Z from WE 25 ns WRITE Cycle Time 70 tWP(3) WE, CE Pulse Width 50 tAVEL tAVWL tAW Address Setup Time 0 tEHAX tWR1 WRITE Recovery Time tWHAX tWR2 Address Hold Time from WE tWHQX tOEW Output Active from WE tDVEH tDVWH tDS(4) Data Setup Time tWHDX tDH1(4) Data Hold Time from WE tEHDX tDH2(4) Data Hold Time from CE ) s ( ct b O - so ns uc d o r P e let ) s t( ns ns 15 ns 0 ns 5 ns 30 ns 0 ns 10 ns u d o Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH and tDS are measured from the earlier of CE or WE going high. r P e t e l o s b O 9/24 M48T251Y, M48T251V Table 4. Memory AC Characteristics, M48T251V M48T251V–85 Parameter(1) Symbol Unit Min Max tAVAV tRC READ Cycle Time tAVQV tACC Access Time 85 ns tELQV tCO Chip Enable Low to Output Valid 85 ns tGLQV tOE Output Enable Low to Output Valid 45 ns tELQX tGLQX tCOE Chip Enable or Output Enable Low to Output Transition 5 ns tAXQX tOH Output Hold from Address Change 5 ns tEHQZ tGHQZ tOD(2) tWLQZ tODW(2) tAVAV tWC tWLWH tWP1(3) tELEH 85 Chip Enable or Output Enable High to Output Hi-Z 35 ns Output Hi-Z from WE 30 ns WRITE Cycle Time 85 WRITE Enable Pulse Width 65 tWP2 Chip Enable Pulse Width 75 tAVEL tAVWL tAW Address Setup Time tEHAX tWR1(4) tWHAX tWR2 Address Hold Time from WE tWHQX tOEW Output Active from WE tDVEH tDVWH tDS(5) Data Setup Time tWHDX tDH1(5) Data Hold Time from WE tEHDX tDH2 Data Hold Time from CE uc Pr 0 e t le WRITE Recovery Time d o r P e Note: 1. 2. 3. ns (t s) b O - so ) s t( ns od uc ns ns ns 15 ns 5 ns 5 ns 35 ns 0 ns 15 ns Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). These parameters are sampled with a 5 pF load are not 100% tested. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high. t e l o s b O 10/24 M48T251Y, M48T251V Data Retention Mode Data can be read or written only when VCC is greater than VPFD. When VCC is below VPFD (the point at which write protection occurs), the clock registers and the SRAM are blocked from any access. When VCC falls below the Battery Switch Over threshold (VSO), the device is switched from VCC to battery backup (VBAT). RTC operation and SRAM data are maintained via battery backup until power is stable. All control, data, and address signals must be powered down when VCC is powered down. The lithium power source is designed to provide power for RTC activity as well as RTC and RAM data retention when VCC is absent or unstable. The capability of this source is sufficient to power the device continuously for the life of the equipment into which it has been installed. For specification purposes, life expectancy is ten (10) years at 25°C with the internal oscillator running without VCC. Each unit is shipped with its energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPFD, the energy source is enabled for battery backup operation. The actual life expectancy will be much longer if no battery energy is used (e.g., when VCC is present). PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 READ or WRITE cycles either extract or update data in the clock while disabling the memory. Data transfer to and from the timekeeping function is accomplished with a serial bit-stream under control of Chip Enable (CE), Output Enable (OE), and WRITE Enable (WE). Initially, a READ cycle using the CE and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see Figure 8., page 12). Next, 64 consecutive WRITE cycles are executed using the CE and WE control of the device. These 64 WRITE cycles are used only to gain access to the clock. Therefore, any address to the memory is acceptable. However, the WRITE cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set ) s ( ct u d o r P e t e l o aside just one address location in RAM as a Phantom Clock scratch pad. When the first WRITE cycle is executed, it is compared to Bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all of the bits in the comparison register have been matched. With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock. c u d e t le ) s t( o r P o s b O - s b O 11/24 M48T251Y, M48T251V Figure 8. Comparison Register Definition Hex Value 7 6 5 4 3 2 1 0 BYTE 0 1 1 0 0 0 1 0 1 C5 BYTE 1 0 0 1 1 1 0 1 0 3A BYTE 2 1 0 1 0 0 0 1 1 A3 BYTE 3 0 1 0 1 1 1 0 0 5C BYTE 4 1 1 0 0 0 1 0 1 C5 BYTE 5 0 0 1 1 1 0 1 BYTE 6 1 0 1 0 0 0 P e let 1 1 A3 BYTE 7 0 1 0 0 0 5C ) s ( ct o s b O 1 1 1 ro c u d 0 ) s t( 3A AI04262 Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB. u d o r P e t e l o s b O 12/24 M48T251Y, M48T251V Clock Register Information AM-PM/12/24 Mode Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in the clock register map (see Table 5.). Data contained in the clock registers is in Binary Coded Decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7. Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When it is high, the 12hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with the logic high being “PM.” In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours). Oscillator and Reset Bits Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the reset bit is set to logic '1,' the Reset Input pin is ignored. When the reset bit logic is set to '0,' a low input on the reset pin will cause the device to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the RTC/calendar begins to increment. Clock Accuracy The RTC is guaranteed to keep time accuracy to with ±1 minute per month at 25°C. The clock is factory-tuned with special calibration elements, and does not require additional calibration. Moderate temperature deviation will have a negligible effect in most applications. D7 0 D6 D5 0.1 Seconds D4 (t s) 1 0 10 Seconds 2 0 10 Minutes 3 12/24 0 4 0 0 5 0 0 0 0 6 t e l o 7 o r P e s b O c u d 10 / A/P OSC 10 Years Keys: A/P = AM/PM Bit 12/24 = 12 or 24-hour mode Bit OSC = Oscillator Bit o s b O D3 Hrs RST 10 date 0 Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable. e t le Table 5. Phantom Clock Register Map Register c u d Zero Bits 10M ) s t( 0 D2 o r P D1 D0 Function/Range BCD Format 0.01 Seconds Seconds 00-99 Seconds Seconds 00-59 Minutes Minutes 00-59 Hours (24 Hour Format) Hours 01-12/ 00-23 Day 01-7 Date: Day of the Month Date 01-31 Month Month 01-12 Year Year 00-99 Day of the Week RST = Reset Bit 0 = Must be set to '0' 13/24 M48T251Y, M48T251V Figure 9. Phantom Clock READ Cycle WE tRC tCW tRR tCO CE tOD tOW OE tODO tOE tOEE tCOE DATA OUTPUT VALID Q ) s t( AI04259 c u d Figure 10. Phantom Clock WRITE Cycle OE tWC tWP WE tCW ) s ( ct CE u d o r P e D o s b O - tWR tWR t DH tDH tDS DATA INPUT STABLE t e l o s b O e t le o r P AI04261 Figure 11. Phantom Clock Reset tRST RST AI04235 14/24 M48T251Y, M48T251V Table 6. Phantom Clock AC Characteristics (M48T251Y) Parameter(1) Symbol Min Typ Max Unit tAVAV tRC READ Cycle Time tELQV tCO CE Access Time 55 ns tGLQV tOE OE Access Time 55 ns tELQX tCOE CE to Output Low Z 5 ns tGLQX tOEE OE to Output Low Z 5 ns tEHQZ tOD(2) CE to Output High Z 25 ns tGHQZ tODO(2) OE to Output High Z 25 ns 65 ns tRR READ Recovery 10 ns tAVAV tWC WRITE Cycle Time 65 ns tWLWH tWP(3) WRITE Pulse Width 55 tEHAX tWR(4) WRITE Recovery 10 tDVEH tDS(5) Data Setup Time 30 ) s t( tWHDX tDH1(5) Data Hold Time from WE 0 tEHDX tDH2(5) Data Hold Time from CE 0 tELEH tCW CE Pulse Width 55 tRST RST Pulse Width 65 ns so P e let ro c u d ns ns ns ns ns ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load and are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high. ) s ( ct b O - u d o r P e t e l o s b O 15/24 M48T251Y, M48T251V Table 7. Phantom Clock AC Characteristics (M48T251V) Parameter(1) Symbol Min Typ Max Unit tAVAV tRC READ Cycle Time tELQV tCO CE Access Time 85 ns tGLQV tOE OE Access Time 85 ns tELQX tCOE CE to Output Low Z 5 ns tGLQX tOEE OE to Output Low Z 5 ns tEHQZ tOD(2) CE to Output High Z 30 ns tGHQZ tODO(2) OE to Output High Z 30 ns 85 ns tRR READ Recovery 20 ns tAVAV tWC WRITE Cycle Time 85 ns tWLWH tWP(3) WRITE Pulse Width 60 tEHAX tWR(4) WRITE Recovery 20 tDVEH tDS(5) Data Setup Time 35 ) s t( tWHDX tDH1(5) Data Hold Time from WE 0 tEHDX tDH2(5) Data Hold Time from CE 0 tELEH tCW CE Pulse Width 65 tRST RST Pulse Width 85 ns so P e let ro c u d ns ns ns ns ns ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load and are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE. 5. tDH and tDS are measured from the earlier of CE or WE going high. ) s ( ct u d o r P e t e l o s b O 16/24 b O - M48T251Y, M48T251V MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8. Absolute Maximum Ratings Symbol TA Parameter Operating Temperature Value Unit 0 to 70 °C TSTG Storage Temperature (VCC, Oscillator Off) –40 to 85 °C TSLD(1) Lead Solder Temperature for 10 seconds 260 °C M48T251Y –0.3 to +7.0 V M48T251V –0.3 to +4.6 ) s t( VCC Supply Voltage (on any pin relative to Ground) VIO Input or Output Voltages V –0.3 to VCC + 0.3 IO Output Current 20 PD Power Dissipation 1 r P e t le uc V mA od W Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). No preheat above 150°C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery. CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode. ) s ( ct o s b O - u d o r P e t e l o s b O 17/24 M48T251Y, M48T251V DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9. DC and AC Measurement Conditions Parameter M48T251Y M48T251V 4.5 to 5.5V 3.0 to 3.6V 0 to 70°C 0 to 70°C Load Capacitance (CL) 100pF 50pF Input Rise and Fall Times ≤ 5ns ≤ 5ns 0 to 3V 0 to 3V 1.5V 1.5V VCC Supply Voltage Ambient Operating Temperature Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output High Z is defined as the point where data is no longer driven (see Table 9., page 18). c u d Figure 12. AC Testing Load Circuit VCCI 1.1 KΩ DEVICE UNDER TEST ) s ( ct 680 Ω CL = 50 pF u d o r P e t e l o e t le ) s t( o r P o s b O - AI04240 Note: 50pF for M48T251V. Table 10. Capacitance s b O Symbol CIN CIO(3) Parameter(1,2) Min Max Unit Input Capacitance 10 pF Input / Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V. Sampled only; not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs were deselected. 18/24 M48T251Y, M48T251V Table 11. DC Characteristics Sym (1) Test Condition Parameter Min M48T251Y M48T251V –70 –85 Typ Max Typ Max 0V ≤ VIN ≤ VCC ±1 ±1 µA 0V ≤ VOUT ≤ VCC ±1 ±1 µA 85 50 mA ILI(2) Input Leakage Current ILO Output Leakage Current ICC1 Supply Current ICC2 Supply Current (TTL Standby) ICC3 VCC Power Supply Current VIL(3) Input Low Voltage –0.3 0.8 VIH(3) Input High Voltage 2.2 VCC + 0.3 VOL Output Low Voltage IOL = 2.0 mA VOH Output High Voltage IOH = –1.0 mA CE = VIH 5 10 5 7 mA CE = VCCI – 0.2 3 5 2 3 mA –0.3 0.6 V 2.2 VCC + 0.3 V 0.4 V VPFD(3) Power Fail Deselect 0.4 2.4 4.25 Battery Back-up Switchover VSO(3) Min Unit uc 2.4 4.37 4.50 2.80 r P e t le VBAT od ) s t( 2.97 2.5 V V V Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. RST (Pin 1) has an internal pull-up resistor. 3. All voltages are referenced to Ground. ) s ( ct o s b O - u d o r P e t e l o s b O 19/24 M48T251Y, M48T251V Figure 13. Power Down/Up Mode AC Waveforms VCC tF tR VPFD (max) VPFD (min) VSO tFB tREC tPD CE c u d tDR e t le Table 12. Power Down/Up Trip Points DC Characteristics Parameter(1) Symbol tREC VPFD (max) to CE low b O - Min Max Unit 1.5 2.5 ms µs VPFD (min) to VSO VCC Fall Time 10 µs VPFD (min) to VPFD (max) VCC Rise Time 0 µs 0 µs 10 Years VPFD (max) to VPFD (min) VCC Fall Time tFB tR uc CE High to Power-Fail tDR(2) AI04236 300 tF tPD so o r P ) s t( od (t s) Expected Data Retention Time r P e Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. At 25°C, VCC = 0V; the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running. t e l o s b O 20/24 M48T251Y, M48T251V PACKAGE MECHANICAL INFORMATION Figure 14. PMDIP32 – 32-pin Plastic Module DIP, Package Outline A A1 B S L C eA e1 e3 D N E 1 o r P PMDIP Note: Drawing is not to scale. e t le c u d ) s t( Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data Min so 9.27 mm Symb Typ Min Max 9.52 0.365 0.375 0.38 – 0.015 – 0.43 0.59 0.017 0.023 0.20 0.33 0.008 0.013 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 eA 14.99 16.00 0.590 0.630 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 A (s) A1 ct B C o r P e D t e l o s b O b O - du Max Typ inches 32 21/24 M48T251Y, M48T251V PART NUMBERING Table 14. Ordering Information Example Example: M48T 251Y –70 PM 1 TR Device Type M48T Supply Voltage and Write Protect Voltage 251Y = VCC = 4.5 to 5.5V; VPFD = 4.25 to 4.50V 251V = VCC = 3.0 to 3.6V; VPFD = 2.80 to 2.97V Speed –70 = 70ns (M48T251Y) c u d –85 = 85ns (M48T251V) Package PM = PMDIP32 e t le Temperature Range 1 = 0 to 70°C Shipping Method for SOIC ) s ( ct blank = Tubes TR = Tape & Reel r P e u d o ) s t( o r P o s b O - For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. t e l o s b O 22/24 M48T251Y, M48T251V REVISION HISTORY Table 15. Document Revision History Date Version Revision Details June 2001 1.0 First Issue 20-May-02 1.1 Add countries to disclaimer 28-Mar-03 2.0 v2.2 template applied; test condition updated (Table 12) 22-Feb-05 3.0 Reformatted; IR reflow update (Table 8) c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 23/24 M48T251Y, M48T251V c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 24/24