PSD835G2
Flash PSD, 5 V supply, for 8-bit MCUs
4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM
Features
■
Flash in-system programmable (ISP)
peripheral for 8-bit MCUs
■
Dual bank flash memories
– 4 Mbits of primary Flash memory
(8 uniform sectors, 64 Kbytes)
– 256 Kbits of secondary Flash memory with
4 sectors
– Concurrent operation: READ from one
memory while erasing and writing the other
■
64 Kbit of SRAM
■
52 reconfigurable I/O ports
■
Enhanced JTAG serial port
■
PLD with macrocells
– Over 3000 gates of PLD: CPLD and DPLD
– CPLD with 16 output macrocells (OMCs)
and 24 Rev 5 macrocells (IMCs)
– DPLD - user defined internal chip select
decoding
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52 individually configurable I/O port pins
They can be used for the following functions:
– MCU I/Os
– PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open-drain
outputs.
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In-system programming (ISP) with JTAG
– Built-in JTAG compliant serial port allows
full-chip in-system programmability
– Efficient manufacturing allow easy product
testing and programming
– Use low cost FlashLINK cable with PC
February 2009
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LQFP80 (U)
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Page register
– Internal page register that can be used to
expand the microcontroller address space
by a factor of 256
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Programmable power management
■
High endurance
– 100,000 Erase/WRITE cycles of Flash
memory
– 1,000 Erase/Write cycles of PLD
– 15 year data retention
■
5 V±10% single supply voltage
■
Standby current as low as 50 µA
■
Memory speed
– 70 ns Flash memory and SRAM access
time for VCC = 4.5 to 5.5 V
– 90 ns Flash memory and SRAM access
time for VCC = 4.5 to 5.5 V
■
ECOPACK® package
Rev 5
1/120
www.st.com
1
Contents
PSD835G2
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
1.2
1.3
2
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1
First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.2
Inventory build-up of preprogrammed devices . . . . . . . . . . . . . . . . . . . . 11
1.1.3
Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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1.2.1
Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 12
1.2.2
Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.3
Separate program and data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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PSDsoft™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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2.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6
JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.7
In-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.8
In-application reprogramming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9
Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
PSD register description and address offset . . . . . . . . . . . . . . . . . . . . 24
5
Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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6.1
Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2
Primary Flash memory and secondary Flash memory description . . . . . 33
6.3
Memory Block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4
Upper and lower block in main Flash sector . . . . . . . . . . . . . . . . . . . . . . . 33
PSD835G2
7
Contents
6.5
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6
Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3
Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.4
Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5
Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6
Read the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7
Data Polling flag (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.8
Toggle flag (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.9
Error flag (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.10
Erase Time-out flag (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.2
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.3
Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.4
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1
Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.2
Reset Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.3
Reset (RESET) signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12
Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.1
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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PSD835G2
12.2
Memory Select configuration for MCUs with separate program and data
spaces 48
12.3
Configuration modes for MCUs with separate program and data spaces 49
12.3.1
Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.3.2
Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14
Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
15
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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15.1
PSD Turbo bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
15.2
Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
15.3
Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15.4
Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15.5
Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.6
Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 60
15.7
The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.8
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
15.9
Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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15.10 External chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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PSD interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . 67
16.2
PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 67
16.3
MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.4
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.5
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16.6
80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
16.7
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.1
General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
17.2
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
17.3
MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PSD835G2
Contents
17.4
PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.5
Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
17.6
Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.7
Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.8
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.9
JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.10 Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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17.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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17.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.15 Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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17.16 Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
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17.17 Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
17.18 OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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17.19 Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
17.20 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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17.21 Ports A,B and C – functionality and structure . . . . . . . . . . . . . . . . . . . . . 83
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17.22 Port D – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
17.23 Port E – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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17.24 Port F – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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17.25 Port G – functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
18.1
Automatic Power-down (APD) unit and Power-down mode . . . . . . . . . . . 89
18.1.1
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
18.2
Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18.3
PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
18.4
PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
18.5
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
18.6
Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Reset timing and device status at Reset . . . . . . . . . . . . . . . . . . . . . . . . 93
19.1
Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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PSD835G2
19.2
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
19.3
I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 93
19.4
Reset of Flash memory erase and program cycles . . . . . . . . . . . . . . . . . 93
Programming in-circuit using the JTAG/ISP interface . . . . . . . . . . . . . 95
20.1
Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
20.2
JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
20.3
Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
22
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
23
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
24
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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PSD835G2
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLD I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
JTAG signals on port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Methods for programming different functional blocks of the PSD. . . . . . . . . . . . . . . . . . . . 21
Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
MCUs and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
80C251 configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interfacing the PSD with the 80C251, with one READ Input . . . . . . . . . . . . . . . . . . . . . . . 71
Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Port configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port Pin Direction Control, Output Enable P.T. not defined . . . . . . . . . . . . . . . . . . . . . . . . 81
Port Pin Direction Control, Output Enable P.T. Defined . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Port Direction Assignment example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Drive register Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Power-down mode effect on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PSD timing and standby current during Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . 90
APD counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Status during Power-Up Reset, Warm Reset and Power-down mode . . . . . . . . . . . . . . . . 94
JTAG port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Example of PSD typical power calculation at VCC = 5.0V (with Turbo mode On) . . . . . . . 99
Example of PSD Typical Power Calculation at VCC = 5.0V (with Turbo mode Off) . . . . . 100
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC signal letters for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC signal behavior symbols for PLD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
CPLD combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
CPLD macrocell synchronous clock mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
CPLD macrocell asynchronous clock mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Input macrocell timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Port F Peripheral Data mode Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Port F Peripheral Data mode Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Program, Write and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Reset (Reset) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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List of tables
Table 49.
Table 50.
Table 51.
PSD835G2
LQFP80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . . . . 116
PSD835G2 LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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PSD835G2
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
LQFP80 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PSDsoft development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Selecting the upper or lower block in a primary Flash memory sector . . . . . . . . . . . . . . . . 34
Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Priority level of memory and I/O components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8031 memory modules – separate space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8031 memory modules – combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PLD diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DPLD logic array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Macrocell and I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CPLD output macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
An example of a typical 8-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
An example of a typical 8-bit non-multiplexed bus interface. . . . . . . . . . . . . . . . . . . . . . . . 68
Interfacing the PSD with an 80C31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interfacing the PSD with the 80C251, with RD and PSEN inputs. . . . . . . . . . . . . . . . . . . . 72
Interfacing the PSD with the 80C51X, 8-bit data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interfacing the PSD with a 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
General I/O port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Port A, B and C structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Port D structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Port E, F, G structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
APD unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Enable power-down flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Power-Up and Warm Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PLD ICC /frequency consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Switching waveforms – key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Input to Output Disable / Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Combinatorial timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Synchronous clock mode timing – PLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Asynchronous Reset / Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Asynchronous clock mode timing (product term clock). . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
READ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Peripheral I/O Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Peripheral I/O Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
ISC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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List of figures
Figure 49.
PSD835G2
LQFP80 - 80 lead thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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PSD835G2
1
Description
Description
The PSD family of memory systems for microcontrollers (MCUs) brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and
flexible solution for embedded designs. PSD devices combine many of the peripheral
functions found in MCU based applications.
The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD
macrocell was created to address the unique requirements of embedded system designs. It
allows direct connection between the system address/data bus, and the internal PSD
registers, to simplify communication between the MCU and other supporting devices.
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The PSD family offers two methods to program the PSD Flash memory while the PSD is
soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application
Programming (IAP).
1.1
In-System Programming (ISP) via JTAG
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An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the
PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly
programmed while soldered to the circuit board. This requires no MCU participation, which
means the PSD can be programmed anytime, even when completely blank.
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The innovative JTAG interface to Flash memories is an industry first, solving key problems
faced by designers and manufacturing houses, such as:
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First time programming
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Inventory build-up of preprogrammed devices
●
Expensive sockets
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1.1.1
First time programming
How do I get firmware into the Flash memory the very first time? JTAG is the answer.
Program the blank PSD with no MCU involvement.
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Inventory build-up of preprogrammed devices
How do I maintain an accurate count of pre-programmed Flash memory and PLD devices
based on customer demand? How many and what version? JTAG is the answer. Build your
hardware with blank PSDs soldered directly to the board and then custom program just
before they are shipped to the customer. No more labels on chips, and no more wasted
inventory.
Expensive sockets
How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer.
Solder the PSD directly to the circuit board. Program first time and subsequent times with
JTAG. No need to handle devices and bend the fragile leads.
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Description
1.2
PSD835G2
In-application programming (IAP)
Two independent Flash memory arrays are included so that the MCU can execute code from
one while erasing and programming the other. Robust product firmware updates in the field
are possible over any communications channel (CAN, Ethernet, UART, J1850, etc.) using
this unique architecture. Designers are relieved of the following problems:
1.2.1
●
Simultaneous READ and WRITE to Flash memory
●
Complex memory mapping
●
Separate program and data space
Simultaneous READ and WRITE to Flash memory
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How can the MCU program the same memory from which it is executing code? It cannot.
The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading
code from one while erasing and programming the other during IAP.
1.2.2
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Complex memory mapping
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How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is
embedded in the PSD. The concurrent PSD memories can be mapped anywhere in MCU
address space, segment by segment with extremely high address resolution. As an option,
the secondary Flash memory can be swapped out of the system memory map when IAP is
complete. A built-in page register breaks the MCU address limit.
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1.2.3
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Separate program and data space
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How can I write to Flash memory while it resides in Program space during field firmware
updates? My 80C51 will not allow it. The PSD provides means to reclassify Flash memory
as Data space during IAP, then back to Program space when complete.
1.3
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PSDsoft™
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PSDsoft, a software development tool from ST, guides you through the design process stepby-step making it possible to complete an embedded MCU design capable of ISP/IAP in just
hours. Select your MCU and PSDsoft takes you through the remainder of the design with
point and click entry, covering PSD selection, pin definitions, programmable logic inputs and
outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging
your MCU firmware with the PSD design. When complete, two different device programmers
are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro.
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PSD835G2
Description
61 PB0
62 PB1
63 PB2
64 PB3
65 PB4
66 PB5
67 PB6
68 PB7
69 VCC
70 GND
71 PE0
72 PE1
73 PE2
74 PE3
75 PE4
76 PE5
77 PE6
78 PE7
79 PD0
LQFP80 connections
80 PD1
Figure 1.
PD2 1
60 CNTL1
PD3 2
59 CNTL0
AD0 3
58 PA7
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AD1 4
57 PA6
AD2 5
56 PA5
AD3 6
55 PA4
du
AD4 7
GND 8
VCC 9
AD5 10
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AD6 11
AD7 12
AD8 13
AD10 15
AD11 16
)-
AD12 17
AD13 18
49 GND
48 PC7
47 PC6
46 PC5
45 PC4
44 PC3
43 PC2
42 PC1
CNTL2 40
RESET 39
PF7 38
PF6 37
PF5 36
PF4 35
PF3 34
PF2 33
PF1 32
PF0 31
GND 30
VCC 29
PG7 28
PG6 27
41 PC0
PG5 26
PG4 25
PG3 24
PG2 23
PG1 22
PG0 21
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52 PA1
50 GND
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AD15 20
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51 PA0
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AD9 14
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Description
Table 1.
Pin
name
ADIO0-7
PSD835G2
Pin description
Pin
3-710-12
Type
Description
I/O
This is the lower Address/Data port. Connect your MCU address or address/data
bus according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed
with the lower address bits, connect AD0-AD7 to this port.
If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal
is active and one of the PSD functional blocks was selected. The addresses on
this port are passed to the PLDs.
)
s
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ct
u
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o
ADIO815
CNTL0
13-20
59
I/O
This is the upper Address/Data port. Connect your MCU address or address/data
bus according to the following rules:
If your MCU has a multiplexed address/data bus where the data is multiplexed
with the lower address bits, connect A8-A15 to this port.
If your MCU does not have a multiplexed address/data bus, connect A8-A15 to
this port.
If you are using an 80C251 in page mode, connect AD8-AD15 to this port.
If you are using an 80C51XA in burst mode, connect A12-A19 to this port.
ALE or AS latches the address. The PSD drives data out only if the READ signal
is active and one of the PSD functional blocks was selected. The addresses on
this port are passed to the PLDs.
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The following control signals can be connected to this port, based on your MCU:
WR – active low Write Strobe input.
R_W – active high READ/active low WRITE input.
This port is connected to the PLDs. Therefore, these signals can be used in
decode and other logic equations.
t
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d
o
r
I
The following control signals can be connected to this port, based on your MCU:
RD – active low Read Strobe input.
E – E clock input.
DS – active low Data Strobe input.
PSEN – connect PSEN to this port when it is being used as an active low READ
signal. For example, when the 80C251 outputs more than 16 address bits, PSEN
is actually the READ signal.
This port is connected to the PLDs. Therefore, these signals can be used in
decode and other logic equations.
P
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l
o
CNTL1
s
b
O
60
CNTL2
40
I
This port can be used to input the PSEN (Program Select Enable) signal from any
MCU that uses this signal for code exclusively. If your MCU does not output a
Program Select Enable signal, this port can be used as a generic input. This port
is connected to the PLDs as input.
Reset
39
I
Active low input. Resets I/O ports, PLD macrocells and some of the Configuration
registers and JTAG registers. Must be low at Power-up. Reset also aborts the
Flash programming/erase cycle that is in progress.
14/120
PSD835G2
Table 1.
Description
Pin description (continued)
Pin
name
Pin
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
58
57
56
55
54
53
52
51
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
68
67
66
65
64
63
62
61
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
48
47
46
45
44
43
42
41
s
b
O
PD2
79
Description
These pins make up port A. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
I/O CMOS
or Open CPLD macrocell (McellA0-7) outputs.
Drain
Inputs to the PLDs.
)
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ct
Latched, transparent or registered PLD input.
These pins make up port B. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
I/O CMOS
or Open CPLD macrocell (McellB0-7) output.
Drain
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r
P
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o
Inputs to the PLDs.
Latched, transparent or registered PLD input.
s
b
O
These pins make up port C. These port pins are configurable and can have the
following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open
Drain
External Chip Select (ECS0-7) output.
)
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r
P
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o
PD0
PD1
Type
Latched, transparent or registered PLD input.
PD0 pin of port D. This port pin can be configured to have the following functions:
I/O CMOS ALE/AS input latches addresses on ADIO0-ADIO15 pins.
or Open AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.
Drain
Input to the PLDs.
Transparent PLD input.
80
PD1 pin of port D. This port pin can be configured to have the following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open Input to the PLDs.
Drain
CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
1
PD2 pin of port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
I/O CMOS
or Open Input to the PLDs.
PSD Chip Select Input (CSI). When low, the MCU can access the PSD memory
Drain
and I/O. When high, the PSD memory blocks are disabled to conserve power. The
trailing edge of CSI can be used to get the PSD out of power-down mode.
15/120
Description
Table 1.
PSD835G2
Pin description (continued)
Pin
name
Pin
PD3
2
I/O CMOS PD3 pin of port D. This port pin can be configured to have the following functions:
or Open MCU I/O – write to or read from a standard output or input port.
Drain
Input to the PLDs.
71
PE0 pin of port E. This port pin can be configured to have the following functions:
I/O CMOS
MCU I/O – write to or read from a standard output or input port.
or Open
Latched address output.
Drain
TMS input for JTAG/ISP interface.
72
PE1 pin of port E. This port pin can be configured to have the following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open
Latched address output.
Drain
TCK input for JTAG/ISP interface (Schmidt Trigger).
73
PE2 pin of port E. This port pin can be configured to have the following functions:
I/O CMOS
MCU I/O – write to or read from a standard output or input port.
or Open
Latched address output.
Drain
TDI input for JTAG/ISP interface.
74
PE3 pin of port E. This port pin can be configured to have the following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open
Latched address output.
Drain
TDO input for JTAG/ISP interface.
75
PE4 pin of port E. This port pin can be configured to have the following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open Latched address output.
Drain
TSTAT input for the ISP interface.
Ready/Busy for in-circuit Parallel Programming.
PE0
PE1
PE2
PE3
PE4
PE5
PE7
PF0-PF7
16/120
Description
)
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)
(s
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o
r
PE5 pin of port E. This port pin can be configured to have the following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open
Latched address output.
Drain
TERR active low input for ISP interface.
P
e
t
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l
o
s
b
O
PE6
76
Type
77
I/O CMOS PE6 pin of port E. This port pin can be configured to have the following functions:
or Open MCU I/O – write to or read from a standard output or input port.
Drain
Latched address output.
78
I/O CMOS PE7 pin of port E. This port pin can be configured to have the following functions:
or Open MCU I/O – write to or read from a standard output or input port.
Drain
Latched address output.
31-38
PF0 through PF7 pins of port F. This port pins can be configured to have the
following functions:
I/O CMOS MCU I/O – write to or read from a standard output or input port.
or Open Input to the PLDs.
Drain
Latched address outputs.
As address A0-A3 inputs in 80C51XA mode.
As data bus port (D07) in non-multiplexed bus configuration.
PSD835G2
Table 1.
Pin
name
Description
Pin description (continued)
Pin
Type
Description
PG0 through PG7 pins of port G. This port pins can be configured to have the
8, 30, I/O CMOS following functions:
PG0-PG7 49, 50, or Open
MCU I/O – write to or read from a standard output or input port.
70
Drain
Latched address outputs.
VCC
9, 29,
69
Supply voltage
GND
8, 30,
49, 50,
70
Ground pins
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17/120
s
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18/120
CSIOP
FLASH ISP CPLD
(CPLD)
GLOBAL
CONFIG. &
SECURITY
CLKIN
64 KBIT SRAM
256 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
8 SECTORS
4 MBIT PRIMARY
FLASH MEMORY
PORT A & B
16 OUTPUT MACROCELLS
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
PORT A ,B & C
24 INPUT MACROCELLS
PORT F
8 EXT CS TO PORT C OR F
RUNTIME CONTROL
AND I/O REGISTERS
PERIP I/O MODE SELECTS
SRAM SELECT
SECTOR
SELECTS
MACROCELL FEEDBACK OR PORT INPUT
82
FLASH DECODE
PLD (DPLD)
r
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CLKIN
(PD1)
PORT G
PROG.
PORT
CLKIN
82
SECTOR
SELECTS
EMBEDDED
ALGORITHM
s
b
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PG0 – PG7
PORT F
PROG.
PORT
ADIO
PORT
PROG.
MCU BUS
INTRF.
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(s
PF0 –PF7
P
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r
AD0 – AD15
CNTL0,
CNTL1,
CNTL2
PAGE
REGISTER
PORT
E
PROG.
PORT
PORT
D
PROG.
PORT
PORT
C
PROG.
PORT
PORT
B
PROG.
PORT
PORT
A
PROG.
PORT
PE0 – PE7
PD0 – PD2
PC0 – PC7
PB0 – PB7
PA0 – PA7
Figure 2.
PLD
INPUT
BUS
ADDRESS/DATA/CONTROL BUS
Description
PSD835G2
PSD block diagram
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AI05793c
PSD835G2
2
PSD architectural overview
PSD architectural overview
PSD devices contain several major functional blocks. Figure 2: PSD block diagram shows
the architecture of the PSD device family. The functions of each block are described briefly
in the following sections. Many of the blocks perform multiple functions and are user
configurable.
2.1
Memory
Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed
discussion can be found in the section entitled Section 6.1: Memory blocks on page 32. The
4 Mbit (512K x 8) Flash memory is the primary memory of the PSD. It is divided into 8
equally-sized sectors that are individually selectable.
)
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u
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o
The 256 Kbit (32K x 8) secondary Flash memory is divided into 4 equally-sized sectors.
Each sector is individually selectable.
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The 64 Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the
MCU SRAM.
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o
Each sector of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
2.2
)
(s
Page register
s
b
O
The 8-bit Page register expands the address range of the MCU by up to 256 times. The
paged address can be used as part of the address space to access external memory and
peripherals, or internal memory and I/O. The Page register can also be used to change the
address mapping of sectors of the Flash memories into different memory spaces for IAP.
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2.3
d
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r
P
e
PLDs
s
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The device contains two PLDs, the Decode PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, each optimized for a different function. The functional partitioning of the
PLDs reduces power consumption, optimizes cost/performance, and eases design entry.
The DPLD is used to decode addresses and to generate Sector Select signals for the PSD
internal memory and registers. The CPLD can implement user-defined logic functions. The
DPLD has combinatorial outputs. The CPLD has 16 output macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 input macrocells (IMC) that can be configured
as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are
differentiated by their output destinations, number of product terms, and macrocells.
The PLDs consume minimal power by using power-management design techniques. The
speed and power consumption of the PLD is controlled by the Turbo bit in PMMR0 and other
bits in the PMMR2. These registers are set by the MCU at run-time. There is a slight penalty
to PLD propagation time when invoking the power management features.
19/120
PSD architectural overview
2.4
PSD835G2
I/O ports
The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each
I/O pin can be individually configured for different functions. ports can be configured as
standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed
address/data buses.
The JTAG pins can be enabled on port E for in-system programming (ISP). ports F and G
can also be configured as data ports for a non-multiplexed bus.
Ports A and B can also be configured as a data port for a non-multiplexed bus.
2.5
MCU bus interface
)
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PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed
address/data buses. The device is configured to respond to the MCU’s control signals,
which are also used as inputs to the PLDs. For examples, please see Section 16.3: MCU
bus interface examples on page 68.
Table 2.
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Name
o
s
b
82
Complex PLD (CPLD)
82
Port E pins
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PE0
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2.6
2.7
O
)
JTAG signals on port E
PE1
o
r
P
let
Inputs
Decode PLD (DPLD)
Table 3.
r
P
e
PLD I/O
Outputs
Product terms
17
43
24
150
JTAG signal
TMS
TCK
PE2
TDI
PE3
TDO
PE4
TSTAT
PE5
TERR
JTAG port
In-system programming (ISP) can be performed through the JTAG signals on port E. This
serial interface allows complete programming of the entire PSD device. A blank device can
be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can
be multiplexed with other functions on port E. Table 3: JTAG signals on port E indicates the
JTAG pin assignments.
In-system programming (ISP)
Using the JTAG signals on port E, the entire PSD device (memory, logic, configuration) can
be programmed or erased without the use of the MCU.
20/120
PSD835G2
2.8
PSD architectural overview
In-application reprogramming (IAP)
The primary Flash memory can also be programmed in-system by the MCU executing the
programming algorithms out of the secondary memory, or SRAM. Since this is a sizable
separate block, the application can also continue to operate. The secondary memory can be
programmed the same way by executing out of the primary Flash memory. The PLD or other
PSD Configuration blocks can be programmed through the JTAG port or a device
programmer. Table 4 indicates which programming methods can program different
functional blocks of the PSD.
2.9
Power management unit (PMU)
)
s
(
ct
The power management unit (PMU) gives the user control of the power consumption on
selected functional blocks based on system requirements. The PMU includes an Automatic
Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit
has a Power-down mode that helps reduce power consumption.
u
d
o
The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in PMMR0 can be reset to ’0’ and the CPLD latches
its outputs and goes to sleep until the next transition on its inputs.
r
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Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. Please see Section 18: Power management on page 88 for
more details.
Table 4.
s
b
O
Methods for programming different functional blocks of the PSD
Functional block
Primary Flash memory
s
(
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c
)-
JTAG/ISP
Device
programmer
IAP
Yes
Yes
Yes
Yes
Yes
Yes
PLD Array (DPLD and CPLD)
Yes
Yes
No
PSD configuration
Yes
Yes
No
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Secondary Flash memory
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21/120
Development system
3
PSD835G2
Development system
The PSD family is supported by PSDsoft, a Windows-based (95, 98, NT) software
development tool. A PSD design is quickly and easily produced in a point-and-click
environment. The designer does not need to enter Hardware Description Language (HDL)
equations, unless desired, to define PSD pin functions and memory map information. The
general design flow is shown in Figure 3. PSDsoft is available from our web site (the
address is given on the back page of this data sheet) or other distribution channels.
PSDsoft directly supports two low cost device programmers form ST: PSDpro and
FlashLINK (JTAG). Both of these programmers may be purchased through your local
distributor/representative, or directly from our web site using a credit card. The PSD is also
supported by third party device programmers. See our web site for the current list.
)
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s
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PSD835G2
Figure 3.
Development system
PSDsoft development tool
Choose MCU and PSD
Automatically Configures MCU
bus interface and other PSD
attributes.
Define PSD Pin and
Node Functions
)
s
(
ct
Point-and-click definition of PSD
pin functions, internal nodes and
MCU system memory map
u
d
o
r
P
e
Define General Purpose
Logic in CPLD
C Code Generation
Point-and-click definition of
combinatorial and registered
logic in CPLD. Access to HDL is
available if needed.
)-
Merge MCU Firmware
with PSD Configuration
s
(
t
c
A composite object file is created
containing MCU firmware and
PSD configuration
u
d
o
let
r
P
e
o
s
b
t
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l
o
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
s
b
O
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
ST PSD Programmer
PSDPro, or
FlashLINK (JTAG)
*.OBJ
FILE AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG/ISP)
AI04918b
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23/120
PSD register description and address offset
4
PSD835G2
PSD register description and address offset
Table 5 shows the offset addresses to the PSD registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD registers.Table 5 provides brief descriptions of the registers in CSIOP space.
The following section gives a more detailed description.
Table 5.
Register address offset
Register name
Port
A
Port
B
Port
C
Port
D
Port
E
Port
F
Port
G
Data In
00
01
10
11
30
40
41
Reads port pin as input, MCU
I/O input mode
Control
42
43
Stores data for output to port
pins, MCU I/O output mode
05
14
15
34
44
45
Direction
06
07
14
15
36
46
47
09
Input macrocell
0A
0B
Enable Out
0C
0D
Output
macrocells A
ete
Mask macrocells
B
38
t(s
1B
49
O
)
1A
1C
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P
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o
bs
48
u
d
o
Configures port pin as input or
output
Configures port pins as either
CMOS or Open Drain on some
pins, while selecting high slew
rate on other pins.
Reads input macrocells
Reads the status of the output
enable to the I/O port driver
4C
READ – reads output of
macrocells A
WRITE – loads macrocell flipflops
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P
ol
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O
19
c
u
d
20
Output
macrocells B
Mask macrocells
A
18
)
s
(
ct
32
04
08
Description
(1)
Selects mode between MCU
I/O or Address Out
Data Out
Drive Select
Other
READ – reads output of
macrocells B
WRITE – loads macrocell flipflops
21
Blocks writing to the output
macrocells A
22
Blocks writing to the output
macrocells B
23
Primary Flash
Protection
C0
Read only – Primary Flash
Sector Protection
Secondary Flash
Memory
Protection
C2
Read only – PSD Security and
secondary Flash memory
Sector Protection
JTAG Enable
C7
Enables JTAG port
PMMR0
B0
Power Management register 0
PMMR2
B4
Power Management register 2
24/120
PSD835G2
Table 5.
PSD register description and address offset
Register address offset (continued)
Port
A
Register name
Port
B
Port
C
Port
D
Port
E
Port
F
Port
G
Other
Description
(1)
Page
E0
Page register
VM
E2
Places PSD memory areas in
Program and/or Data space on
an individual basis.
Memory_ID0
F0
Read only – Primary Flash
memory and SRAM size
Memory_ID1
F1
Read only – secondary Flash
memory type and size
)
s
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ct
1. Other registers that are not part of the I/O ports.
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25/120
Register bit definition
5
PSD835G2
Register bit definition
All the registers of the PSD are included here, for reference. Detailed descriptions of these
registers can be found in the following sections.
Data-In registers – ports A, B, C, D, E, F, G
Read port pin status when port is in MCU I/O input mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
)
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ct
Read-only registers
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d
o
Data-Out registers – ports A, B, C, D, E, F, G
Latched data for output to port pin when pin is configured in MCU I/O output mode.
Bit 7
Bit 6
Bit 5
Bit 4
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Bit 3
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Port pin 3
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Bit 2
Bit 1
Bit 0
Port pin 2
Port pin 1
Port pin 0
Direction registers – ports A, B, C, D, E, F, G
Bit 7
Bit 6
Port pin 7
Port pin 6
)-
Bit 5
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c
Port pin 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
u
d
o
Port pin 0 = port pin is configured in Input mode (default).
1 = port pin is configured in Output mode.
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P
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Control registers – ports E, F, G
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s
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O
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin 0 = port pin is configured in MCU I/O mode (default).
1 = port pin is configured in Latched Address Out mode.
Drive registers – ports A, B, D, E, G
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin 0 = port pin is configured for CMOS Output driver (default).
1 = port pin is configured for Open Drain output driver.
26/120
PSD835G2
Register bit definition
Drive registers – ports C, F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Port pin 0
Port pin 0 = port pin is configured for CMOS Output driver (default).
1 = port pin is configured in Slew Rate mode.
Enable-Out registers – ports A, B, C, F
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Port pin 7
Port pin 6
Port pin 5
Port pin 4
Port pin 3
Port pin 2
Port pin 1
Read-only registers
Port pin 0 = port pin is in tri-state driver (default).
1 = port pin is enabled.
Bit 0
Port pin 0
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Input macrocells – ports A, B, C
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Read Input macrocell (IMC7-IMC0) status on ports A, B and C.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell 7
IMcell 6
IMcell 5
IMcell 4
IMcell 3
IMcell 2
IMcell 1
IMcell 0
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Read-only registers
Output macrocells A register
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Bit 7
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Mcella 7
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Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
Write register: Load MCellA7-MCellA0 with '0' or '1.'
Read register: Read MCellA7-MCellA0 output status.
Output macrocells B register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Mcellb 0
Write register: Load MCellB7-MCellB0 with '0' or '1.'
Read register: Read MCellB7-MCellB0 output status.
27/120
Register bit definition
PSD835G2
Mask macrocells A register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella 7
Mcella 6
Mcella 5
Mcella 4
Mcella 3
Mcella 2
Mcella 1
Mcella 0
McellA_Prot 0 = Allow MCellA flip-flop to be loaded by MCU (default).
1 = Prevent MCellA flip-flop from being loaded by MCU.
Mask macrocells B register
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Mcellb 7
Mcellb 6
Mcellb 5
Mcellb 4
Mcellb 3
Mcellb 2
Mcellb 1
Bit 0
Mcellb 0
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McellB_Prot 0 = Allow MCellB flip-flop to be loaded by MCU (default).
1 = Prevent MCellB flip-flop from being loaded by MCU.
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Flash Memory Protection register
Bit 7
Bit 6
Bit 5
Bit 4
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
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Bit 3
Bit 2
Bit 1
Bit 0
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Read-only registers
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Sec_Prot 1 = Primary Flash memory Sector is write protected.
0 = Primary Flash memory Sector is not write protected.
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Flash Boot Protection register
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Bit 7
Security_Bit
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Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
not used
Sec3_Prot
Sec2_Prot
Sec1_Prot
Sec0_Prot
Sec_Prot 1 = Secondary Flash memory Sector is write protected.
0 = Secondary Flash memory Sector is not write protected.
Security_Bit 0 = Security bit in device has not been set.
1 = Security bit in device has been set.
JTAG Enable register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
not used
not used
not used
not used
not used
JTAGEnable
JTAG_Enable 1 = JTAG port is enabled.
0 = JTAG port is disabled.
28/120
PSD835G2
Register bit definition
Page register
Configure Page input to PLD. Default is PGR7-PGR0=00.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
PMMR0 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
not used
(set to ’0’)
PLD
MCells CLK
PLD
Array CLK
PLD
Turbo
not used
(set to ’0’)
APD
Enable
not used
(set to ’0’)
)
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The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET)
pulses do not clear the registers.
PLD Turbo 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
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APD Enable 0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
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PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the
PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
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PLD MCells CLK Note: 0 = CLKIN to the PLD macrocells is connected.
1 = CLKIN to the PLD macrocells is disconnected, saving power.
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PMMR2 register
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Bit 7
not used
(set to ’0’)
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Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLD
Array WRH
PLD
Array ALE
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to ’0’)
PLD Array
Addr
PLD Array Addr 0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
Note: In XA mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7ADIO4
PLD Array 0 = CNTL2 input to the PLD AND array is connected.
CNTL2 1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array 0 = CNTL1 input to the PLD AND array is connected.
CNTL1 1 = CNTL1 input to the PLD AND array is disconnected, saving power.
29/120
Register bit definition
PSD835G2
PLD Array 0 = CNTL0 input to the PLD AND array is connected.
CNTL0 1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array ALE 0 = ALE input to the PLD AND array is connected.
1 = ALE input to the PLD AND array is disconnected, saving power.
PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected.
1 = WRH/DBE input to the PLD AND array is disconnected, saving power.
VM register
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Peripheral
mode
not used
(set to ’0’)
not used
(set to ’0’)
FL_data
Boot_data
FL_code
Boot_code
Bit 0
SR_code
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On reset, bit1-bit4 are loaded to configurations that are selected by the user in PSDsoft.Bit0
and bit7 are always cleared on reset.Bit0-bit4 are active only when the device is configured
for the 8031 and compatible MCU families.
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SR_code 0 = PSEN cannot access SRAM.
1 = PSEN can access SRAM.
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Boot_code 0 = PSEN cannot access secondary NVM.
1 = PSEN can access secondary NVM.
FL_code 0 = PSEN cannot access primary Flash memory.
1 = PSEN can access primary Flash memory.
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Boot_data 0 = RD cannot access secondary NVM.
1 = RD can access secondary NVM.
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FL_data 0 = RD cannot access primary Flash memory.
1 = RD can access primary Flash memory.
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Peripheral mode 0 = Peripheral mode of port F is disabled.
1 = Peripheral mode of port F is enabled.
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Memory_ID0 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
S_size 3
S_size 2
S_size 1
S_size 0
F_size 3
F_size 2
F_size 1
F_size 0
F_size[3:0] 4h = Primary Flash memory size is 4 Mbit
5h = Primary Flash memory size is 8Mbit
S_size[3:0] 0h = There is no SRAM
1h = SRAM size is 16 Kbit
3h = SRAM size is 64 Kbit
30/120
PSD835G2
Register bit definition
Memory_ID1 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to ’0’)
not used
(set to ’0’)
B_type 1
B_type 0
B_size 3
B_size 2
B_size 1
B_size 0
B_size[3:0] 0h = There is no secondary NVM
2h = Secondary NVM size is 256 Kbit
B_type[1:0] 0h = Secondary NVM is Flash memory
1h = Secondary NVM is EEPROM
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31/120
Detailed operation
6
PSD835G2
Detailed operation
As shown in Figure 2, the PSD consists of six major types of functional blocks:
●
Memory blocks
●
PLD blocks
●
MCU bus interface
●
I/O ports
●
Power management unit (PMU)
●
JTAG/ISP interface
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The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
6.1
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Memory blocks
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The PSD has the following memory blocks:
●
Primary Flash memory
●
Secondary Flash memory
●
SRAM
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The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are
user-defined in PSDsoft.
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Table 6.
Memory block size and organization
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Primary Flash memory
Sector
number
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32/120
SRAM
Sector size
(Kbytes)
Sector
Select
signal
Sector size
(Kbytes)
Sector
Select
signal
SRAM size
(Kbytes)
SRAM
Select
signal
64
FS0
8
CSBOOT0
16
RS0
1
64
FS1
8
CSBOOT1
2
64
FS2
8
CSBOOT2
3
64
FS3
8
CSBOOT3
4
64
FS4
5
64
FS5
6
64
FS6
7
64
FS7
Total
512
8 sectors
32
4 sectors
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Secondary Flash memory
16
PSD835G2
6.2
Detailed operation
Primary Flash memory and secondary Flash memory
description
The primary Flash memory is divided evenly into eight equal sectors. The secondary Flash
memory is divided into four equal sectors of eight Kbytes each. Each sector of either
memory block can be separately protected from program and erase cycles.
Flash memory may be erased on a sector-by-sector basis and programmed word-by-word.
Flash sector erasure may be suspended while data is read from other sectors of the block
and then resumed after reading.
During a program or erase cycle in Flash memory, the status can be output on Ready/Busy
(PE4). This pin is set up using PSDsoft.
6.3
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Memory Block Select signals
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The DPLD generates the Select signals for all the internal memory blocks (see Section 15:
PLDs). Each of the eight sectors of the primary Flash memory has a Select signal (FS0FS7) which can contain up to three product terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-CSBOOT3) which can contain up to three
product terms. Having three product terms for each Select signal allows a given sector to be
mapped in different areas of system memory. When using an MCU with separate program
and data space, these flexible Select signals allow dynamic re-mapping of sectors from one
memory space to the other before and after IAP.
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6.4
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Upper and lower block in main Flash sector
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The PSD835G2’s main Flash memory has eight 64-Kbyte sectors. The 64-Kbyte sector size
may cause some difficulty in code mapping for an 8-bit MCU with only 64-Kbyte address
space. To resolve this mapping issue, the PSD835G2 provides additional logic (see
Figure 5) for the user to split the 8 sectors such that each sector has a lower and upper 32Kbyte block, and the two blocks can reside in different pages but in the same address range.
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If your design works with 64KB sectors, you don’t need to configure this logic. If the design
requires 32KB blocks in each sector, you need to define a “FA15” PLD equation in PSDsoft
as the A15 address input to the main Flash module. FA15 consists of 3 product terms and
will control whether the MCU is accessing the lower or upper 32KB in the selected sector.
Figure 4 shows an example for Flash sector chip select FS0. A typical equation is FA15 =
pgr4 of the Page register. When pgr4 is 0 (page 00), the lower 32KB is selected. When pgr4
is switched to ’1’ by the user, the upper 32KB is selected. PSDsoft will automatically
generate the PLD equations shown, based on your point and click selections.
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If no FA15 equation is defined in PSDsoft, the A15 that comes from the MCU address bus
will be routed as input to the primary Flash memory instead of FA15. The FA15 equation has
no impact on the Sector Erase operation.
Note:
FA15 affects all eight sectors of the primary Flash memory simultaneously. You cannot
direct FA15 to a particular Flash sector only.
33/120
Detailed operation
Figure 4.
PSD835G2
Example for Flash Sector Chip Select FS0
page = [pgr7... pgr0]; “Page Register output
“Sector Chip Select Equation
FS0 = ((0000h
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