SPEAR600-2

SPEAr600 Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface Datasheet − production data Features ■ Dual ARM926EJ-S core up to 333 MHz: – Each with 16 Kbytes instruction cache + 16 Kbytes data cache ■ High performance 8-channel DMA ■ Dynamic power saving features ■ Up to 733 DMIPS ■ Memory: – External DRAM interface: 8/16-bit DDR1333 / DDR2 - 666 – 32 Kbytes BootROM / 8 Kbytes internal SRAM – Flexible static memory controller (FSMC) supporting parallel NAND Flash memory interface, ONFI 1.0 support, internal 1-bit ECC or external 4-bit ECC – Serial NOR Flash Memory interface ■ Connectivity: – 2 x USB 2.0 Host – USB 2.0 Device – Giga Ethernet (GMII port) – I2C and fast IrDA interfaces – 3 x SSP Synchronous serial peripheral (SPI, Microwire or TI protocol) ports – 2 x UART interfaces ■ Peripherals supported: – TFT/STN LCD controller (resolution up to 1024 x 768 and colors up to 24 bpp) – Touchscreen support ■ Miscellaneous functions – Integrated real-time clock, watchdog, and system controller – 8-channel 10-bit ADC, 1 Msps – JPEG codec accelerator – 10 GPIO bidirectional signals with interrupt capability – 10 independent 16-bit timers with programmable prescaler ■ 32-bit width External local bus (EXPI interface). May 2012 This is information on a product in full production. PBGA420 (23 x 23 x 2.06 mm) ■ 3 x I2S interfaces for audio features: – One stereo input and two stereo outputs (audio 3.1 configuration capable) ■ Customizable logic with 600 Kgate standard cell array ■ Software: – System compliant with all operating systems (including Linux) Applications ■ The SPEAr® embedded MPU family targets networked devices used for communication, display and control. This includes diverse consumer, business, industrial and life science applications such as: – IP phones, thin client computers, printers, programmable logic controllers, PC docking stations, – Medical lab/diagnostics equipment, wireless access devices, home appliances, residential control and security systems, digital picture frames, and bar-code scanners/readers. Table 1. Order code Device summary Temp. range SPEAR600-2 -40 to 85 °C Doc ID 16259 Rev 3 Package Packing PBGA420 (23 x 23 x 2.06 mm) Tray 1/97 www.st.com 1 Contents SPEAr600 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 DDR/DDR2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Flexible static memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Multichannel DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 JPEG codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9 8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.11 USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.13 Synchronous Serial Peripheral (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.14 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.15 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.16 Fast IrDA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.17 I2S audio block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.18 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.18.1 2/97 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.19 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.20 Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.21 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.22 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.23 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.24 Reconfigurable array subsystem connectivity (RAS) . . . . . . . . . . . . . . . . 22 2.25 External Port Controller (EXPI I/F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Doc ID 16259 Rev 3 SPEAr600 3 Contents Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Pin descriptions listed by functional block . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 Configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.1 Full features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.2 Disable NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.3 Disable LCD ctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.4 Disable GMAC ctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 Self cfg_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.6 Self cfg_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.7 All processors disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.4 Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5 3.3V I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.6 DDR2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.7 Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.8 Power on reset (MRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.9 ADC electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.1 6.2 6.3 DDR2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.1.1 DDR2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.1.2 DDR2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.1.3 DDR2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 EXPI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2.1 Pad delay disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2.2 Pad delay enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.1 CLCD timing characteristics direct clock . . . . . . . . . . . . . . . . . . . . . . . . 71 Doc ID 16259 Rev 3 3/97 Contents SPEAr600 6.3.2 6.4 I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 6.7 6.5.1 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.2 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Ether MAC 10/100/1000 Mbps (GMAC-Univ) timing characteristics . . . . 80 6.6.1 GMII Transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6.2 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6.3 GMII-MII Receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.6.4 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 SMI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.7.1 6.8 7 4/97 SMI timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.8.1 SPI master mode timings (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.8.2 SPI master mode timings (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.1 8 CLCD timing characteristics divided clock . . . . . . . . . . . . . . . . . . . . . . . 72 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Doc ID 16259 Rev 3 SPEAr600 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 System reset, master clock, RTC and configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SMI, SSP, UART, FIRDA and I2C pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 USB pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Ethernet pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 NAND Flash I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DDR I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 LCD I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LVDS I/F pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 EXPI/I2S pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 EXPI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Maximum current and power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Low voltage TTL DC input specification (3 V< VDD FPGA_AHB-slave SPEAr600_AHB-slave = T(re->io) + T(nfio->FFs) where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal delay (~9 ns). Doc ID 16259 Rev 3 77/97 Timing characteristics SPEAr600 Note: Values in Table 48 are referred to the common internal source clock which has a period of THCLK = 6 ns. 6.5.2 16-bit NAND Flash configuration Figure 28. Output pads for 16-bit NAND Flash configuration NFCLE D HCLK SET CLR NFCE NFWE NFRE NFRWPRT NFALE NFIO_0..7 Q Q ... ... ... D SET CLR Q Q CLPOWER CLLP CLLE CLFP CLCP CLAC CLD_23..22 (NFIO_8..15) Figure 29. Input pads for 16-bit NAND Flash configuration D NFRB NFIO_0..7 HCLK SET CLR Q Q CLPOWER CLLP CLLE ... ... (NFIO_8..15) CLFP CLCP CLAC D CLD_23..22 SET CLR Q Q Figure 30. Output command signal waveforms 16-bit NAND Flash configuration NFCE TCLE NFCLE TWE NFWE TIO NFIO 78/97 Command Doc ID 16259 Rev 3 SPEAr600 Timing characteristics Figure 31. Output address signal waveforms 16-bit NAND Flash configuration NFCE TALE NFALE TWE NFWE TIO NFIO Address Figure 32. In/out data signal waveforms for 16-bit NAND Flash configuration NFCE TWE NFWE TIO NFIO (out) Data Out TRE NFRE (3) TREAD TRE -> IO TNFIO -> FFs NFIO (in) Table 49. Timing characteristics for 16-bit NAND Flash configuration Parameter TCLE TALE Max -16.85 ns -19.38 ns -16.84 ns -19.37 ns (1) 11.10 ns 13.04 ns (1) 11.18 ns 13.05 ns 3.27 ns 11.35 ns TWE (s=1) TRE (s=1) Min TIO (h=1)(2) 1. TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE, respectively. Both are composed by the algebric sum of a fixed part (due to the internal delays of Spear) and a programmable one in a FSMC register. The programmable one is equal to (s+1)*Thclk where s=Tset. The values shown in the table are calculated using s=1 2. TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on the min or the max timing. It's composed by the algebric sum of a fixed part (due to the internal delays of Spear) and a programmable one in a FSMC register. The programmable one is equal to h*Thclk where h=Thiz. The values shown in the table are calculated using h=1. 3. TREAD is the timing between the falling edge and the rising edge of NFRE. This value is fully programmable and it's equal to T(read) = (w+1)*T(hclk) >= T(re->io) + T(nfio->FFs) where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal delay (~9 ns). Doc ID 16259 Rev 3 79/97 Timing characteristics SPEAr600 Note: Values in Table 49 are referred to the common internal source clock which has a period of THCLK = 6 ns. 6.6 Ether MAC 10/100/1000 Mbps (GMAC-Univ) timing characteristics The characterization timing is given for an output load of 5 pF on the GMII TX clock and 10 pF on the other pads. The operating conditions are in worst case V=0.90 V, T=125 ° C and in best case V=1.10 V, T= 40 ° C. 6.6.1 GMII Transmit timing specifications Figure 33. GMII TX waveforms GMIITX_CLK Tmax Tclock Tmin TXD0-TXD3, GMIITX_D4-GMIITX_D7, TXEN, TXER Tf Tr Figure 34. Block diagram of GMII TX pins TX[0..3], GMII_TX[4..7], TXEN, TXER D SET Q t2 CLK CLR Q GMII_TXCLK t3 Table 50. GMII TX timing Parameter 80/97 TX[0..3], GMII_TX[4..7], TXEN, TXER Value using GMII [tCLK period = 8 ns 125 MHz] trise (tr)