ST2S08BPQR

ST2S08B Dual synchronous rectification, 1.5 A, 1.5 MHz adjustable step-down switching regulator Datasheet − production data Features ■ Step-down current mode PWM (1.5 MHz) DCDC converter ■ Adjustable output voltage from 0.8 V ■ 2 % DC output voltage tolerance ■ Synchronous rectification ■ Integrated current limit ■ Inhibit function ■ Soft-start for start delay of 800 µs typ. ■ Typical efficiency: > 80 % at VOUT = 1.2 V ■ 1.5 A output current capability ■ Non-switching quiescent current: max 1.5 mA over temperature range ■ RDS(ON) 150 mΩ (typ.) ■ Uses tiny capacitors and inductors ■ Available in QFN12L (4 x 4 mm) QFN12L (4 x 4 mm) ST2S08B is available in the QFN12L (4 x 4 mm) package. Description The ST2S08B is a dual step-down DC-DC converter optimized for powering low-voltage digital cores in ODD applications and, generally, to replace the high current linear solution when the power dissipation may cause a high heating of the application environment. It provides up to 1.5 A over an input voltage range of 3 V to 5.5 V. A high switching frequency of 1.5 MHz allows the use of tiny surface-mounted components as well as a resistor divider to set the output voltage value. Only an inductor and two capacitors are required. A low output ripple is guaranteed by the current mode PWM topology and the utilization of low ESR SMD ceramic capacitors. The device is thermally protected and current limited. The Table 1. Device summary Order code Package Packaging ST2S08BPQR QFN12L (4 x 4 mm) Tape and reel May 2012 This is information on a product in full production. Doc ID 18290 Rev 2 1/18 www.st.com 18 Contents ST2S08B Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2 Programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.3 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.4 Input and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.5 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 Doc ID 18290 Rev 2 ST2S08B Diagram 1 Diagram Figure 1. Schematic diagram  6)?37 6)?! $ELAY 2EF 37 (6 4RIMMING &" 6)?37 37 &" #/.42/, ,/')# 2EF 3OFT3TART '.$ ).( '.$ !-V * Not available on the ST2S08B version. Doc ID 18290 Rev 2 3/18 Pin configuration ST2S08B 2 Pin configuration Figure 2. Pin connections (top view) Table 2. Pin description Pin n° Name 1 HV Programing pin. It must be floating or connected to GND. 2 FB2 Feedback voltage 3 GND2 Power ground 4 SW2 Switching pin 5 VIN_SW 6 SW1 Switching pin 7 GND1 Power ground 8 FB1 Feedback voltage/output voltage 9 NC Not connect 10 INH Inhibit pin: - High device on - Low device off 11 VIN_A Supply for analog circuit 12 GND_A System ground 4/18 Function Power input voltage pin Doc ID 18290 Rev 2 ST2S08B Maximum ratings 3 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VIN_SW Positive power supply voltage -0.3 to 7 V VIN_A Positive power supply voltage -0.3 to 7 V VINH Inhibit voltage -0.3 to 7 V Max. voltage of output pin -0.3 to 7 V -0.3 to 2.5 V +1 to -1 mA 150 °C -65 to +150 °C 300 °C SWITCH voltage VFB1,2 Feedback voltage/output voltage Current into VFB pin Common mode input voltage TJ Max junction temperature TSTG Storage temperature range TLEAD Lead temperature (soldering) 10 sec. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junction-case 10 °C/W RthJA Thermal resistance junction-ambient 60 °C/W Table 5. Symbol ESD ESD performance Parameter ESD protection voltage Test conditions HBM-DH11C Doc ID 18290 Rev 2 Value Unit 4 kV 5/18 Electrical characteristics 4 ST2S08B Electrical characteristics VIN_SW = VIN_A = 5 V, VO1,2 =1.2 V, C1= 4.7 µF, C2 = C3 = 22 µF, L1 = L2 = 3.3 µH, TJ = -30 to 125 °C, unless otherwise specified. Typical values refer to 25 °C. Table 6. Symbol Electrical characteristics Parameter FB1,2 Feedback voltage IFB1,2 VFB pin bias current IQ Quiescent current Min. Typ. Max. Unit 784 800 816 mV VFB = 1 V 600 nA VINH > 1.2 V, VFB = 1 V 1.5 mA VINH = GND IO1,2 Output current IMIN Minimum output current VINH Test conditions Inhibit threshold VIN = 3.0 to 5.5 V TJ = - 30 to 85 °C 20 (1) , 1.5 A 1 mA 3.0 V < VIN < 5 V 1.2 3.0 V < VIN < 5.5 V 1.3 V Device OFF IINH1,2 µA 0.4 Inhibit pin current 2 µA %VO1,2/ ΔVIN Reference line regulation 3.0 V < VIN < 5.5 V 0.04 %VO/ VIN ΔVO1,2 Reference load regulation 10 mA < IO < 1.5 A 10 mV PWM fS PWM switching frequency VFB = 0.7 V, TA = 25 °C 1.2 1.5 Maximum duty cycle VFB = 0.7 V, TA = 25 °C 85 94 % ISWL Switching current limitation (2) 2 A ILKN NMOS leakage current VFB = 0.9 V, TA = 25 °C 0.1 µA ILKP PMOS leakage current VFB = 0.9 V, TA = 25 °C 0.1 µA DMAX 1.8 MHz RDSon-N NMOS switch on resistance ISW = 250 mA 0.15 0.3 Ω RDSon-P PMOS switch on resistance ISW = 250 mA 0.2 0.4 Ω η Efficiency IO = 20 mA to 100 mA 75 % IO = 100 mA to 1.5 A 80 % TSHDN Thermal shutdown 150 °C THYS Thermal shutdown hysteresis 15 °C ISC - VIN Short-circuit VIN range (2) Output short-circuit to ground 1. VO= 90 % of nominal value. 2. Guaranteed by design, but not tested in production. 6/18 Doc ID 18290 Rev 2 3 5.3 V ST2S08B Typical application 5 Typical application Figure 3. Application circuit L2 VIN VIN_A SW2 VIN_SW VFB2 R3 NC GND1 GND2 HV VO2 L1 3.3 µF ST2S08B INH 3.3 µH SW1 R1 VO1 VFB1 GND_A C1 R2 4.7 µF C2 22 µF R4 C3 22 µF AM07870v1 Note: R1, R2 and R3, R4 are calculated according to the following equations: - VO1 = VFB1 (1 + R1 / R2) - VO2 = VFB2 (1 + R3 / R4) Doc ID 18290 Rev 2 7/18 Typical performance characteristics ST2S08B 6 Typical performance characteristics Figure 4. Feedback voltage vs. temperature Efficiency vs. output current 1 AM07883v1 0.84 0.83 VIN = 5 V, Vfb1,Vfb2 connected to VO1-2 , IO1 = IO2 = 10 mA EFFICIENCY [%] 0.82 0.81 VFB [V] Figure 5. 0.8 0.79 0.78 0.77 0.76 -50 -25 0 25 50 75 100 125 AM07884v1 100 90 80 70 60 50 40 30 20 10 0 VIN = 5 V, VO1 = 1.2 V , VO2 NO LOAD 0 0.25 0.5 Temperature [°C] Figure 6. Efficiency vs. output current 2 Figure 7. AM07885v1 100 90 80 70 60 50 40 30 20 10 0 1.25 1.5 Switching frequency vs. temperature AM07886v1 1.9 Frequency [MHz] EFFICIENCY [%] VIN = 5 V, VO2 = 3.3 V, VO1 NO LOAD 1.7 1.6 1.5 1.4 1.3 VIN = 5 V, VFB1 = VFB2 = 0.7 V 1.2 1.1 0.25 0.5 0.75 1 1.25 -50 1.5 -25 0 Figure 8. 25 50 75 100 Duty cycle vs. temperature Figure 9. Inhibit threshold vs. temperature AM07887v1 100 98 96 94 92 90 88 86 84 82 80 125 Temperature [°C] Output Current 2 [A] AM07889v1 1.4 1.2 1 VINH (V) Duty Cycle [%] 1 1.8 0 0.8 0.6 0.4 VIN = 5 V, VFB1 = VFB2 = 0.7 V ON VIN = 5.5 V , IO1 = IO2 = 100 mA 0.2 OFF 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 T [°C] Temperature [°C] 8/18 0.75 Output current 1 [A] Doc ID 18290 Rev 2 75 100 125 ST2S08B Typical performance characteristics ISW2 [A] Figure 10. Switching current limitation vs. temperature Figure 11. Load transient response AM07888v1 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 VIN = 5 V, Output1 maximum load current -50 -25 0 25 50 75 100 125 Temperature [°C] VIN = 5 V, IO1 from 250 mA to 1.5 A VO1 @ 1.2 V Figure 12. Inhibit transient INH VINH = from 0 V to 2 V, VIN = 5.5 V, IO1 = IO2 = 1.5 A Doc ID 18290 Rev 2 9/18 General information 7 ST2S08B General information The ST2S08B is a dual adjustable current mode PWM step-down DC-DC converter. It is a complete 1.5 A switching regulator with internal compensation that eliminates the need for additional components. The constant frequency, current mode, PWM architecture and stable operation with ceramic capacitors, results in low, predictable output ripple. To clamp the error amplifier reference voltage, a soft-start control block, generating a voltage ramp, has been implemented. Other circuits fitted to the device protection are the thermal shut-down block, which turns off the regulator when the junction temperature exceeds 150 °C (typ.), and cycle-by-cycle switching current limiting. Operation of the device requires few components: 2 inductors, 3 capacitors, and a resistor divider. The chosen inductor must be capable of not saturating at the peak current level. Its value should be selected keeping in mind that a large inductor value increases the efficiency at low output current and reduces output voltage ripple, while a smaller inductor can be chosen when it is important to reduce package size and total application cost. Finally, the ST2S08 has been designed to work properly with X5R or X7R SMD ceramic capacitors both at input and at output. These types of capacitors, due to their very low series resistance (ESR), minimize the output voltage ripple. Other low ESR capacitors can be used, according to the needs of the application, without compromising the correct functioning of the device. 10/18 Doc ID 18290 Rev 2 ST2S08B Application information 8 Application information 8.1 Introduction The following technical information is used for estimating typical external component characteristics using standard equations. Nevertheless, it is strongly recommended to validate the suitability of external components to the application requirements by thoroughly testing any solution at bench level on a real evaluation circuit. 8.2 Programming the output voltage The output voltage for both channels can be adjusted from 0.8 V up to 85 % of the input voltage value by connecting a resistor divider between VO and GND, the middle point of the divider must be connected to the feedback (FB) pin, as shown in Figure 3. The resistor divider must be chosen according to the following equations: Equation 1 R1 ⎞ ⎛ VO1 = VFB 1 × ⎜⎜ 1 + ⎟ R 2 ⎟⎠ ⎝ Equation 2 R3 ⎞ ⎛ VO 2 = VFB 2 × ⎜⎜ 1 + ⎟ R4 ⎟⎠ ⎝ Using a resistor with a value in the range of 1 kΩ to 50 kΩ is recommended. Lower values are also suitable, but increase current consumption. 8.3 Inductor selection The inductor is the key passive component for switching converters. The critical inductance values can then be obtained according to the following formulas: Equation 3 LMIN = VO × (VIN _ MAX − VO ) VIN _ MAX × FSW × ΔIL FSW = switching frequency ΔIL = the peak-to-peak inductor ripple current. As a rule of thumb, the peak-to-peak ripple can be set at 20 % - 40 % of the output current. The peak current of the inductor can be calculated as: Doc ID 18290 Rev 2 11/18 Application information ST2S08B Equation 4 IPEAK = (IO / 0.8) + VO × (VIN _ MAX − VO ) 2 × VIN _ MAX × FSW × L In addition to the inductance value, in order to avoid saturation, the maximum saturation current of the inductor must be higher than that of the IPEAK. 8.4 Input and output capacitor selection It is recommended to use ceramic capacitors with X5R or X7R dielectric and low ESR as input and output capacitors, in order to filter any disturbance present in the input line and to obtain stable operation. The output capacitor is very important for satisfying the output voltage ripple requirements. The output voltage ripple (VO_RIPPLE), in continuous mode, for the step-down channel, can be calculated as: Equation 5 ⎤ ⎡ 1 VO _ RIPPLE = ΔIL × ⎢ESR + ⎥ 8 C F × × OUT SW ⎦ ⎣ where Δ IL is the ripple current and FSW is the switching frequency. The use of ceramic capacitors with voltage ratings in the range higher than 1.5 times the maximum input or output voltage is recommended. 8.5 Layout considerations Due to the high switching frequency and peak current, the layout is an important design step for all switching power supplies. Important parameters (efficiency, output voltage ripple, switching noise immunity, etc.) can be affected if the PCB layout is not designed paying close attention to the following DC-DC general layout rules: ● Short, wide traces must be implemented for mains current and for power ground paths. The input capacitor must be placed as close as possible to the IC pins as well as the inductor and output capacitor. ● The FB pin connection to the external resistor divider is a high impedance node, so interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. To reduce pick-up noise, the resistor divider must be placed very close to the device. ● A common ground node minimizes ground noise. ● The exposed pad of the package must be connected to the common ground node. Moreover, the exposed pad ground connection must be properly designed in order to facilitate heat dissipation from the exposed pad to the ground layer using PCB vias. 12/18 Doc ID 18290 Rev 2 ST2S08B 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST registered trademark. Doc ID 18290 Rev 2 13/18 Package mechanical data ST2S08B QFN12L (4x4) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. 0.80 0.90 1.00 0.031 0.035 0.039 A1 0.02 0.05 0.001 0.002 A3 0.20 A 0.008 b 0.25 0.30 0.35 0.010 0.012 0.014 D 3.90 4.00 4.10 0.154 0.157 0.161 D2 2.00 2.15 2.25 0.079 0.085 0.089 E 3.90 4.00 4.10 0.154 0.157 0.161 E2 2.00 2.15 2.25 0.079 0.085 0.089 e L 0.80 0.45 0.55 0.031 0.65 0.018 0.022 0.026 7936361B 14/18 Doc ID 18290 Rev 2 ST2S08B Package mechanical data Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 330 C 12.8 D 20.2 N 99 13.2 Max. 12.992 0.504 0.519 0.795 101 T 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 18290 Rev 2 15/18 Package mechanical data ST2S08B Figure 13. QFN12L (4 x 4 mm) footprint recommended data 16/18 Doc ID 18290 Rev 2 ST2S08B Revision history 10 Revision history Table 7. Document revision history Date Revision Changes 30-Nov-2010 1 Initial release. 18-May-2012 2 Modified max 1.0 mA ==> max 1.5 mA : Features on page 1. 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