STD105N10F7AG

STD105N10F7AG Automotive-grade N-channel 100 V, 6.8 mΩ typ., 80 A, STripFET™ F7 Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. STD105N10F7AG 100 V  Figure 1: Internal schematic diagram     8 mΩ ID PTOT 80 A 120 W Designed for automotive applications and AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Applications D(2, TAB)  Switching applications Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. G(1) S(3) AM01475v1_Tab Table 1: Device summary Order code Marking Package Packing STD105N10F7AG 105N10F7 DPAK Tape and reel June 2016 DocID027071 Rev 4 This is information on a product in full production. 1/14 www.st.com Contents STD105N10F7AG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/14 DPAK (TO-252) type A2 package information................................. 10 Revision history ............................................................................ 13 DocID027071 Rev 4 STD105N10F7AG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ± 20 V ID Drain current (continuous) at TC = 25 °C 80 A ID Drain current (continuous) at TC = 100 °C 62 A IDM(1) Drain current (pulsed) 320 A PTOT Total dissipation at TC = 25 °C 120 W Tstg Storage temperature range TJ Operation junction temperature range -55 to 175 °C Value Unit Notes: (1)Pulse width limited by safe operating area. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Thermal resistance junction-case 1.25 Thermal resistance junction-pcb 50 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2oz Cu. Table 4: Avalanche characteristics Symbol Parameter Value Unit EAS Single pulse avalanche energy TJ = 25 °C, L = 3.5 mH, IAS = 15 A, VDD = 50 V, VGS = 10 V 400 mJ DocID027071 Rev 4 3/14 Electrical characteristics 2 STD105N10F7AG Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 5: On/Off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage (VGS = 0) ID = 250 μA Zero gate voltage drain current (VGS = 0) VDS = 100 V IDSS IGSS Gate body leakage current (VDS = 0) VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS , ID = 250 μA RDS(on) Static drain-source on-resistance VGS = 10 V, ID= 40 A Min. Typ. Max. 100 Unit V VDS = 100 V, TC = 125 °C (1) 2.5 6.8 1 µA 100 µA ± 100 nA 4.5 V 8 mΩ Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Test conditions Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 50 V, ID = 80 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") Min. Typ. Max. Unit - 4369 - pF - 823 - pF - 36 - pF - 61 - nC - 26 - nC - 13 - nC Min. Typ. Max. Unit - 27 - ns - 40 - ns - 46 - ns - 15 - ns Table 7: Switching times Symbol td(on) tr td(off) tf 4/14 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 50 V, ID = 40 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") DocID027071 Rev 4 STD105N10F7AG Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 80 A ISDM(1) Source-drain current (pulsed) - 320 A VSD(2) Forward on voltage - 1.2 V trr ISD = 80 A, VGS = 0 V Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 80 A, di/dt = 100 A/µs VDD = 80 V, Tj = 150 °C - 77 ns - 146 nC - 4 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5 %. DocID027071 Rev 4 5/14 Electrical characteristics 2.1 6/14 STD105N10F7AG Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Normalized V(BR)DSS vs temperature Figure 7: Static drain-source on-resistance DocID027071 Rev 4 STD105N10F7AG Electrical characteristics Figure 8: Gate charge vs gate-source voltage Figure 9: Capacitance variations Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics DocID027071 Rev 4 7/14 Test circuits 3 8/14 STD105N10F7AG Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID027071 Rev 4 STD105N10F7AG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID027071 Rev 4 9/14 Package information 4.1 STD105N10F7AG DPAK (TO-252) type A2 package information Figure 19: DPAK (TO-252) type A2 package outline 0068772_type-A2_rev21 10/14 DocID027071 Rev 4 STD105N10F7AG Package information Table 9: DPAK (TO-252) type A2 mechanical data mm Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 5.10 5.25 6.60 1.00 0.20 0° DocID027071 Rev 4 8° 11/14 Package information STD105N10F7AG Figure 20: DPAK (TO-252) recommended footprint (dimensions are in mm) 12/14 DocID027071 Rev 4 STD105N10F7AG 5 Revision history Revision history Table 10: Document revision history Date Revision 23-Oct-2014 1 First release. 30-Oct-2014 2 Document status promoted from preliminary to production data. 20-May-2016 3 Updated Section 4.1: "DPAK (TO-252) type A2 package information". Minor text changes. 4 Updated title and features in cover page. Updated Table 5: "On/Off states". Minor text changes. 03-Jun-2016 Changes DocID027071 Rev 4 13/14 STD105N10F7AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 14/14 DocID027071 Rev 4