STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer
Features
■
Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■
Conforms to the transition minimized
differential signaling (TMDS) voltage standard
on input and output channels
■
340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■
3.4 Gbps data rate per channel
■
Fully automatic adaptive equalizer for cables
lengths up to 25 m
■
Single supply VCC: 3.135 to 3.465 V
■
ESD:
■
Integrated open-drain I2C buffer for display
data channel (DDC)
■
> ± 5 KV HBM for all TMDS I/Os
5.3 V tolerant DDC and HPD I/Os
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Lock-up free operation of I C bus
■
0 to 400 kHz clock frequency for I2C bus
■
Low capacitance of all the channels
■
Equalizer regenerates the incoming attenuated
TMDS signal
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TQFP48
QFN48
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■
Buffer drives the TMDS outputs over long PCB
track lengths
■
Low output skew and jitter
■
Tight input thresholds reduce bit error rates
■
On-chip selectable 50 Ω input termination
■
Low ground bounce
■
Data and control inputs provide undershoot
clamp diode
■
Demonstration kit is available
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Device summary
Order code
Operating temperature
Package
Packaging
STDVE001ABTR
-40 °C to 85 °C
TQFP48
Tape and reel
STDVE001AQTR
-40 °C to 85 °C
QFN48
Tape and reel
30 August 2011
Doc ID 14855 Rev 5
1/48
www.st.com
48
Contents
STDVE001A
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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5.1
Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
I2C
5.6
Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7
Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.8
Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.9
CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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7.1
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2
DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 25
7.3
DC electrical characteristics (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5
Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . 29
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Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2
Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.4
I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Doc ID 14855 Rev 5
STDVE001A
Contents
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Contents
STDVE001A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Adaptive equalizer gain with frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC specifications for TMDS differential outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs . . . . . . . 22
Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Status pins (HPD_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Status pins (HPD_EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC electrical characteristics (CEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Status pins (HPD_INT, HPD_EXT, OE_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TQFP48 (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
QFN48 (7 x 7 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Doc ID 14855 Rev 5
STDVE001A
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
STDVE001A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DDC I2C bus repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
STDVE001A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin configuration (TQFP48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin configuration (QFN48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STDVE001A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test circuit for turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test circuit for short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
tSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
tSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
tSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TQFP48 (7 x 7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TQFP48 (7 x 7 mm) footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TQFP48 (7 x 7 mm) tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
QFN48 (7 x 7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Description
1
STDVE001A
Description
The STDVE001A integrates a 4-channel 3.4 Gbps TMDS equalizer. High-speed data paths
and flow-through pinout minimize the internal device jitter and simplify the board layout.
The equalizer overcomes the intersymbol interference (ISI) jitter effects from lossy cables.
The buffer/driver on the output can drive the TMDS output signals over long distances. In
addition to this, STDVE001A integrates the 50 Ω termination resistor on all the input
channels to improve performance and reduce board space. The device can be placed in
a low-power mode by disabling the output current drivers. The STDVE001A is ideal for
advanced TV and STB applications supporting HDMI/DVI standard. The differential signal
from the HDMI/DVI ports can be routed through the STDVE001A to guarantee good signal
quality at the HDMI receiver. Designed for very low skew, jitter and low I/O capacitance, the
switch preserves the signal integrity to pass the stringent HDMI compliance requirements.
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STDVE001A
2
Block diagram
Block diagram
Figure 1.
STDVE001A block diagram
4-$3
DIFFERENTIAL
INPUTS
)NPUT
TERMINATION
SELECTABLE
)NPUT
STAGE
RECEIVER
%QUALIZER
4-$3
DIFFERENTIAL
OUTPUTS
/UTPUT
DRIVER
TRANSMITTER
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Block diagram
STDVE001A
Figure 2.
Equalizer functional diagram (one signal pair)
%1?"//34
/%? .
02%
$ATA
TERMINATION
SELECTABLE
%QUALIZER
0RE
AMP
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DDC I2C bus repeater
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STDVE001A
3
Application diagram
Application diagram
Figure 4.
STDVE001A in a digital TV
$6$
2
34"
"ACKPANEL
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END 46
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Pin configuration
4
STDVE001A
Pin configuration
Figure 5.
Pin configuration (TQFP48 package)
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STDVE001A
Pin configuration
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3$!?).4
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Pin configuration (QFN48 package)
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Pin configuration
Table 2.
STDVE001A
Pin description
Pin
number
Pin name
1
GND
Power Ground
2
VCC
Power 3.3 V ± 5% DC supply
3
CEC_IO
I/O
CEC signal to/from the connector end
4
CEC_IO_INT
I/O
CEC signal to/from TV end
5
GND
Power Ground
6
REXT
Analog
Connect to GND through a 4.7 KΩ ± 1% precision reference resistor. Sets the
output current to generate the output voltage compliant with TMDS.
7
HPD_EXT
Output
0 to 5.0 V (nominal) output signal. Hot plug detector output. Open-drain output.
Connect an external resistor according to the HDMI specification.
8
SDA_EXT
I/O
DDC data I/O. Pulled-up by external termination to VCC.
9
SCL_EXT
I/O
DDC clock I/O. Pulled-up by external termination to VCC.
Type
Function
10
PRE
PRE
Input
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TMDS output deemphasis adjustment
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Output deemphasis
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3.3 V
0 dB
3 dB
11
VDD_EXT
12
GND
13
OUT_D4+
Output
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal
with OUT_D4-.
14
OUT_D4-
Output
HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output signal
with OUT_D4+.
15
VCC
16
OUT_D3+
ete
17
OUT_D3-
l
o
s
18
b
O
GND
Power DC supply for DDC, HPD and CEC (can be 5 V or 3.3 V or unconnected).
O
)
Power Ground
s
(
t
c
u
d
o
Power 3.3 V ± 10% DC supply
Pr
Output
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal
with OUT_D3-.
Output
HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output signal
with OUT_D3+.
Power Ground
19
OUT_D2+
Output
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal
with OUT_D2-.
20
OUT_D2-
Output
HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output signal
with OUT_D2+.
21
VCC
22
OUT_D1+
Output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal
with OUT_D1-.
23
OUT_D1-
Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output signal
with OUT_D1+.
24
GND
12/48
Power 3.3 V ± 10% DC supply
Power Ground
Doc ID 14855 Rev 5
STDVE001A
Table 2.
Pin configuration
Pin description (continued)
Pin
number
Pin name
Type
Function
Active low enable signal.
25
OE_N
Input
OE_N
N_D termination
IOUT_D outputs
1
High-Z
High-Z
0
50 Ω
Active
26
VDD_INT
27
GND
28
SCL_INT
I/O
DDC Clock I/O. Pulled-up by external termination to VCC.
29
SDA_INT
I/O
DDC Data I/O. Pulled-up by external termination to VCC.
30
HPD_INT
31
GND
32
DDC_EN
Power DC supply for DDC, HPD and CEC (can be 5 V or 3.3 V or unconnected).
Power Ground
Input
u
d
o
r
P
e
Power Ground
Input
t
e
l
o
I2C repeater enable signal
DDC_EN
0V
s
b
O
3.3 V
33
)
(s
VCC
)
s
(
ct
Sink side, low-frequency, 0 V to 5 V (nominal) hot plug detector input signal.
Voltage high indicates “plugged” state; voltage low indicates “unplugged” state.
High: 5 V power signal asserted from source to sink and EDID is ready.
Low: No 5 V power signal is asserted from source to sink or EDID is not ready.
I2C repeater
Disabled, high-Z
Enabled, active
Power 3.3 V ± 10% DC supply
TMDS input equalization selector (control pin).
34-35
EQ_BOOST1,
EQ_BOOST2
EQ_BOOST1
Setting at 825 MHz
0
0
11 dB
0
1
9 dB
1
0
4 dB
1
1
16 dB
od
Input
Pr
37
e
t
e
l
38
IN_D1-
Input
HDMI 1.3 compliant TMDS input. IN_D1- makes a differential pair with IN_D1+.
39
IN_D1+
Input
HDMI 1.3 compliant TMDS input. IN_D1+ makes a differential pair with IN_D1-.
40
VCC
41
IN_D2-
Input
HDMI 1.3 compliant TMDS input. IN_D2- makes a differential pair with IN_D2+.
42
IN_D2+
Input
HDMI 1.3 compliant TMDS input. IN_D2+ makes a differential pair with IN_D2-.
43
GND
44
IN_D3-
Input
HDMI 1.3 compliant TMDS input. IN_D3- makes a differential pair with IN_D3+.
45
IN_D3+
Input
HDMI 1.3 compliant TMDS input. IN_D3+ makes a differential pair with IN_D3-.
46
VCC
47
IN_D4-
Input
HDMI 1.3 compliant TMDS input. IN_D4- makes a differential pair with IN_D4+.
48
IN_D4+
Input
HDMI 1.3 compliant TMDS input. IN_D4+ makes a differential pair with IN_D4-.
36
o
s
b
O
t
c
u
EQ_BOOST2
GND
Power Ground
GND
Power Ground
Power 3.3 V ± 10% DC supply
Power Ground
Power 3.3 V ± 10% DC supply
Doc ID 14855 Rev 5
13/48
Functional description
5
STDVE001A
Functional description
The STDVE001A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standard like TMDS. The device passes the
differential inputs from a video source to a common display when it is in the active mode of
operation. The device conforms to the TMDS standard on both inputs and outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE001A result in a very
small propagation delay. Additionally, it supports the DDC, HPD and CEC signaling.
The I2C interface of the enabled input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the enabled input port is output to HPD_EXT.
5.1
)
s
(
ct
Adaptive equalizer
u
d
o
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when VCC is absent or 0 V. In all other cases, the 50 Ω termination resistors
on input channels are present.
r
P
e
t
e
l
o
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
s
b
O
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The default setting of EQ = 00 is
recommended on EQ pins for optimized operation.
Table 3.
O
14/48
od
Gain in dB
(EQ = 01)
Gain in dB
(EQ = 10)
Gain in dB
(EQ = 11)
3
2
0
6.5
325
5
3
1
8.5
410
6.5
4.5
1.5
11
825
11
9
4
16
1650
16
14
8.5
21.5
r
P
e
225
let
t
c
u
Adaptive equalizer gain with frequency
Gain in dB
(EQ = 00)
Freq (MHz)
o
s
b
)
(s
Doc ID 14855 Rev 5
STDVE001A
Functional description
Figure 7.
STDVE001A gain vs. frequency
Gain v/s Freq (STDVE001A)
25
Gain (dB)
20
Gain (EQ=00)
15
Gain (EQ=01)
10
Gain (EQ=10)
Gain (EQ=11)
5
0
225
325
410
825
)
s
(
ct
1650
Freq (MHz)
u
d
o
The equalizer of STDVE001A is fully adaptive and automatic in function. The default setting
of EQ = 00 is recommended for optimal operation. The equalizer performance is optimized
for all frequencies over the cable lengths from 1 m to 25 m at EQ = 00. If cable lengths
greater than 25 m are desired in application, then EQ = 11 setting is recommended. The
other two EQ settings of 01 and 10 are provided simply for fine-tuning purposes and can be
used for very short external cables or PCB traces only if deemed necessary.
r
P
e
t
e
l
o
Input termination
s
b
O
The STDVE001A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE001A produces TMDS output levels for point-to-point
links that are doubly terminated (100 Ω at each end). With the typical 10 mA output current,
the STDVE001A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving
a termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.
)
(s
t
c
u
d
o
r
P
e
s
b
O
t
e
l
o
Output buffers
Each differential output of the STDVE001A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.
The driver outputs are short-circuit current limited and are high-impedance to ground when
OE_N = H or the device is not powered. The current steering architecture requires
a resistive load to terminate the signal to complete the transmission loop from VCC to GND
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage
drop across the termination resistor. The output current drivers are controlled by the OE_N
pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by bandgap voltage
across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.
Doc ID 14855 Rev 5
15/48
Functional description
STDVE001A
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses
a lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
5.2
Operating modes
Table 4.
OE_N operating modes
Input
)
s
(
ct
Output
Function
OE_N
IN+
IN-
OUT+
OUT-
L
H
L
H
L
L
L
H
L
H
X
X
e
t
e
ol
Hi-Z
Pr
u
d
o
H
Hi-Z
Active mode
Active mode
Low power mode
The OE_N input activates a hardware power down mode. When the power down mode is
active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off
and disabled.
s
b
O
Outputs are tri-stated in power-down mode. When exiting power-down mode, there is
a delay associated with turning on band-references and input/output buffer circuits.
)
(s
Note that the OE_N pin is only used to disable the TMDS paths in the chip to same
maximum amount of current. It does not affect the HPD, DDC and CEC portions. The DDC
is controlled only by the DDC_EN pin whereas the HPD and CEC are always active as long
as the supply to the chip is present.
t
c
u
5.3
d
o
r
t
e
l
o
s
b
O
5.4
P
e
HPD pins
The input pin HPD_INT is 5 V tolerant, allowing direct connection to 5 V signals. The output
HPD pin has open-drain structure so that the disabled HPD output is driven to GND
whereas the enabled HPD port has the same polarity as the HPD_INT. Note that the HPD
output should have an external pull-up resistor connected to +5 V from the HDMI source.
DDC channels
The DDC channels are designed together with a bi-directional buffer so as to ensure the
voltage levels on the I2C lines are met even after long capacitive cables. This feature
eliminates the errors during EDID and HDCP reading.
5.5
I2C DDC line repeater
The device contains two identical bi-directional open-drain, non-inverting buffer circuits that
enable I2C DDC bus lines to be extended without degradation in system performance. The
16/48
Doc ID 14855 Rev 5
STDVE001A
Functional description
STDVE001A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C
bus, while retaining all the operating modes and features of the I2C system. This enables
two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers
are operational from a supply V of 3.0 V to 3.6 V.
The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
STDVE001A enables the system designer to isolate the two halves of a bus,
accommodating more I2C devices or longer trace lengths. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz
bus is isolated when 400 kHz operation of the other bus is required. The STDVE001A can
be used to run the I2C bus at both 5 V and 3.3 V interface levels.
The DDC_EN acts as the enable for the DDC buffer. The DDC_EN line should not change
state during an I2C operation, because disabling during bus operation hangs the bus and
enabling port may through a bus cycle could confuse the I2C ports being enabled. The
DDC_EN input should change state only when the global bus and repeater port are in idle
state, to prevent system failures.
)
s
(
ct
u
d
o
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage
of each internal buffer must be 70 mV or more below the output low level, when the output
internally is driven low. This prevents a lock-up condition from occurring when the input low
condition is released.
r
P
e
t
e
l
o
As with the standard I2C system, pull up resistors are required to provide the logic high
levels on the buffered bus. The STDVE001A has standard open collector configuration of
the I2C bus. The size of the pull up resistors depends on the system, but each side of the
repeater must have a pull up resistor.
s
b
O
This part is designed to work with standard mode and fast mode I2C devices. Standard
mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA
in a generic I2C system where standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
)
(s
t
c
u
d
o
r
5.6
Power-down condition
P
e
The OE_N pin can be used to disable the device. The OE_N is used to disable most of the
internal circuitry of STDVE001A that puts the device in a low power mode of operation.
s
b
O
t
e
l
o
5.7
Bias
The bandgap reference voltage over the external REXT reference resistor sets the internal
bias reference current. This current and its factors (achieved by employing highly accurate
and well matched current mirror circuit topologies) are generated on-chip and used by
several internal modules. The 10 mA current used by the transmitter block is also generated
using this reference current. It is important to ensure that the REXT value is within the ±1%
tolerance range of its typical value.
Table 5.
Bias parameter
Parameter
Bandgap voltage
Min
Typ
Max
Unit
−
1.2
−
V
Doc ID 14855 Rev 5
17/48
Functional description
STDVE001A
The output voltage swing depends on 3 components: supply voltage (Vsupply), termination
resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V ± 5%,
termination resistor can vary from 50 Ω ± 10%.
The voltage on the output is given by:
Vsupply - Idrive x RT.
The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within
the HDMI specification under all conditions.
This is achieved when:
400 mV ≤ Idrive x RT ≤ 600 mV with typical value centered at 500 mV.
5.8
)
s
(
ct
Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is
complete.
u
d
o
r
P
e
As soon as the discovery is finished by the HPD detection, the configuration data is
exchanged between a source and sink through the I2C DDC interface. The STDVE001A
DDC interface is ready for communication as soon as the power supply to the chip is
present and stable. When the desired port is enabled and the chip is out of shutdown mode,
the I2C DDC lines can be used for communication.
t
e
l
o
s
b
O
Thus, as soon as the HPD detection sequence is complete, the DDC interface can be
readily used. There is no delay between the HPD detection and I2C DDC interface to be
ready.
5.9
)
(s
t
c
u
CEC
d
o
r
The CEC channel is a dedicated single pin bus and electrically translates to a bi-directional
buffer used to ensure that the electrical specs of the CEC are met even with high
capacitance on the single CEC line. The pull-up resistor of 26 KΩ is integrated on either
sides of the buffer. The CEC is used for AV control of the electronic devices connected in
a HDMI cluster. The drive of the buffer is set to meet the requirements of the CEC. This is
optionally used for higher-level user functions such as automatic set-up tasks or tasks
typically associated with infrared remote control usage.
P
e
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b
O
18/48
The CEC line is continuously monitored during the power-on state and is not monitored
during powered-off state. In powered off state, the CEC line should not be pulled low and it
should not affect the CEC communication between other devices. The maximum
capacitance on the CEC lines can be 7.2 nF.
Doc ID 14855 Rev 5
STDVE001A
6
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in Table 6 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 6.
Absolute maximum ratings
Symbol
VCC
VI
Parameter
Value
TSTG
TL
-0.5 to +4.0
V
DC input voltage (TMDS ports)
1.7 to +4.0
V
OE_N, DDC_EN, PRE, EX_BOOST1, EX_BOOST2
-0.5 to +4.0
V
-0.5 to +6.0
V
120
mA
-65 to +150
°C
300
°C
DC output current
Storage temperature
e
t
e
ol
Lead temperature (10 sec.)
Table 7.
Thermal data
Symbol
ΘJA
)
s
(
ct
Supply voltage to ground
u
d
o
SDA_INT, SCL_INT, SDA_EXT, SCL_EXT, HPD_INT, HPD_EXT
IO
Unit
s
b
O
Parameter
)
(s
Thermal coefficient (junction-ambient)
Pr
TQFP48
QFN48
48
Unit
°C/W
t
c
u
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o
r
P
e
t
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o
s
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Doc ID 14855 Rev 5
19/48
DC and AC characteristics
STDVE001A
7
DC and AC characteristics
7.1
DC electrical characteristics(a)
TA = -40 to +85 °C, VCC = 3.3 V ± 5%.
Table 8.
Power supply characteristics
Value
Symbol
VCC
ICC
Table 9.
Symbol
Parameter
Test condition
Unit
Supply voltage
Supply current
All inputs/outputs
are enabled.
Inputs are
terminated with
50 Ω to VCC.
VCC = 3.465 V
data rate =
3.4 Gbps
Min
Typ
Max
3.135
3.3
3.465
−
u
d
o
r
P
e
130
)
s
(
ct
−
V
mA
t
e
l
o
s
b
O
DC specifications for TMDS differential inputs
Parameter
Test condition
)
(s
Value
Unit
Min
Typ
Max
−
0
150
mV
VTH
Differential input high
threshold
(peak-to-peak)
VCC = 3.465 V
over the entire
VCMR
VTL
Differential input low
threshold
Pr
VCC = 3.465 V
over the entire
VCMR
-150
0
−
mV
VCC = 3.465 V
150
−
1560
mV
VCC - 0.3
−
VCC - 0.04
V
−
3.5
−
pF
u
d
o
e
t
e
ol
VID
s
b
O
VCMR
CIN
ct
Differential input
voltage
(peak-to-peak)(1)
Common mode
voltage range
Input capacitance
IN+ or IN- to
GND
F = 1 MHz
1. Differential output voltage is defined as | (OUT+ - OUT-) |.
Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
20/48
Doc ID 14855 Rev 5
STDVE001A
Table 10.
DC and AC characteristics
DC specifications for TMDS differential outputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VOH
Single-ended high level
output voltage
VCC-10
−
VCC+10
mV
VOL
Single-ended low level
output voltage
VCC-600
−
VCC-400
mV
mV
Single ended output
swing voltage
VCC = 3.3 V
RTERM = 50 Ω
400
500
600
VOD
Differential output
voltage
(peak-to-peak)(1)
VCC = 3.3 V
RTERM = 50 Ω
800
1000
1200
IOH
Differential output high
level current
0
−
IOL
Differential output low
level current
8
10
−
e
t
e
ol
Vswing
| ISC |
COUT
Output driver shortcircuit current
(continuous)
OUT± = GND
through a 50 Ω
resistor.
see Figure 12
Output capacitance
OUT+ or OUTto GND when tristate
F = 1 MHz
)-
s
b
O
−
)
s
(
ct
du
50
o
r
P
mV
µA
12
mA
−
12
mA
5.5
−
pF
s
(
t
c
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |.
u
d
o
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P
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Doc ID 14855 Rev 5
21/48
DC and AC characteristics
Table 11.
STDVE001A
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs
Value
Symbol
Parameter
Test condition
Typ
Max
VIH
HIGH level input voltage
High level
guaranteed
2.0
−
−
V
VIL
LOW level input voltage
Low level
guaranteed
-0.5
−
0.8
V
VIK
Clamp diode voltage
VCC = 3.465 V
IIN = -18 mA
-1.2
-0.8
−
V
IIH
Input high current
VCC = 3.465 V
VIN = VCC
-5
−
+5
IIL
Input low current
VCC = 3.465 V
VIN = GND
-5
−
+5
CIN
Input capacitance
Pin to GND
F = 1 MHz
−
3.5
Table 12.
Input termination resistor
Symbol
RTERM
Table 13.
Parameter
IIN = -10 mA
t
c
u
)
(s
s
b
O
45
−
Value
50
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
Test condition
Differential input
termination resistor on
IN ± channels relative to
VCC
µA
µA
pF
Unit
55
Ω
External reference resistor
od
Symbol
Parameter
r
P
e
Resistor for TMDS
compliant voltage swing
range
let
REXT
o
s
b
Value
Test condition
Tolerance for
R = ± 1%
O
22/48
Unit
Min
Doc ID 14855 Rev 5
Unit
Min
Typ
Max
−
4.7
−
KΩ
STDVE001A
Table 14.
DC and AC characteristics
DDC I/O pins
Value
Symbol
Parameter
Test condition
Unit
Min
VI(DDC)
II(leak)
CI/O
Table 15.
Input voltage
GND
5.3
V
µA
VCC = 3.465 V
input port= 5.3 V
output port = 0.0 V
switch is isolated
−
−
6
VCC = 3.465 V
input port = 3.3 V
output port = 0.0 V
switch is isolated
−
−
2
VI = 0 V
F = 1 MHz
switch disabled
−
5
u
d
o
pF
9
−
pF
r
P
e
Input/output capacitance
VI = 0 V
F = 1 MHz
switch enabled
Parameter
High level input voltage
VIL
Low level input voltage
o
s
b
t
e
l
o
r
P
e
-O
−
)
s
(
ct
µA
Value
Test condition
)
s
(
ct
u
d
o
let
−
Status pins (HPD_INT)
VIH
s
b
O
Max
Input leakage current
Symbol
II(leak)
Typ
Unit
Min
Typ
Max
VCC = 3.3 V
high level guaranteed
2.0
−
5.3
V
VCC = 3.3 V
low level guaranteed
GND
−
0.8
V
VCC = 3.465 V
output = 5.3 V
−
−
4
µA
VCC = 3.465 V
output = 3.3 V
−
−
2
µA
Input leakage current
Doc ID 14855 Rev 5
23/48
DC and AC characteristics
Table 16.
STDVE001A
Status pins (HPD_EXT)(1)
Value
Symbol
V
Parameter
Test condition
Unit
Min
Typ
Max
GND
−
5.3
V
VI = 0 V
F = 1 MHz
switch disabled
−
5
−
pF
CI/O
VI = 0 V
F = 1 MHz
switch enabled
−
9
−
pF
VCC = 3.3 V
IOL = 8 mA
−
−
Voltage
Input/output capacitance
Output low voltage
(open-drain I/Os)
VOL
u
d
o
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
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Doc ID 14855 Rev 5
)
s
(
ct
0.4
V
STDVE001A
DC and AC characteristics
DC electrical characteristics (I2C repeater)
7.2
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified).
Table 17.
Supplies
Value
Symbol
Parameter
Test condition
VCC
DC supply voltage
Unit
Table 18.
Min
Typ
Max
3.135
3.3
3.465
V
Input/output SDA, SCL
)
s
(
t
Value
Symbol
Parameter
Test condition
Unit
Min
VIH
High level input
voltage
0.7 VCC
−
VIL
Low level input
voltage(1)
-0.5
−
VILc
Low level input voltage
contention(1)
-0.5
−
VIK
Input clamp voltage
II = -18 mA
−
IIL
Input current low
(SDA, SCL)
Input current low
(SDA, SCL)
bs
Input current high
(SDA, SCL)
IIH
IOH
let
so
CI
r
P
e
Output high level
leakage current
Input capacitance
Max
c
u
d
5.3
V
0.3 VCC
V
0.4
V
−
-1.2
V
−
−
1
µA
VI = 3.465 V
(SDA, SCL)
−
−
10
µA
VI = 5.3 V
(SDA, SCL)
−
−
10
µA
IOL = 3 mA
0.4
V
IOL = 6 mA
0.65
V
O
)
s
(
t
c
u
d
o
Low level output
voltage
VOL
b
O
Typ
e
t
e
ol
o
r
P
VO = 3.6 V;
driver disabled
−
−
10
µA
VO = 5.3 V;
driver disabled
−
−
10
µA
VI = 3 V or 0 V
−
6
7(2)
pF
1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen
by the SDA/SCL lines.
2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE001A should be used in applications where power is
secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
Doc ID 14855 Rev 5
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DC and AC characteristics
7.3
STDVE001A
DC electrical characteristics (CEC)
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified).
Table 19.
DC electrical characteristics (CEC)
Value
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
3.135
3.3
3.465
V
VCC
DC supply voltage
VOL
Logic 0 output
0.0
−
0.6
V
VOH
Logic 1 output
2.5
−
3.63
V
)
s
(
t
VHL(th)
High to low input V
treshold for logic ‘0’
−
VCEC(‘0’)
≤ 0.8
−
VLH(th)
Low to high input V
treshold for logic ‘1’
−
VCEC(‘1’)
≥ 2.0
−
Typical input hysteresis(1)
−
0.4
c
u
d
−
V
−
250
µs
Vhys
o
r
P
V
V
tr
Maximum rise time
(10% to 90%)
CL= 7.2 nF
−
tf
Maximum fall time
(90% to 10%)
CL= 7.2 nF
−
−
50
µs
23.4
26
28.6
KΩ
−
−
1.8
µA
RPU
Internal pull-up resistor(2)
IOFF
CEC IO current in
unpowered state
)-
e
t
e
ol
s
b
O
VCC = 0.0 V
s
(
t
c
1. Input hysteresis is normally supplied by the microprocessor input circuit. In this case, additional hysteresis
circuitry is not needed.
u
d
o
2. The internal device pull-up should be disconnected from the line when the device is powered-off.
r
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b
O
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Doc ID 14855 Rev 5
STDVE001A
DC and AC characteristics
Dynamic switching characteristics(b)
7.4
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, RTERM = 50 Ω ± 5%, CL = 5 pF).
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 20.
Clock and data rate
Value
Symbol
fCK
Drate
Table 21.
Parameter
Test condition
Unit
Clock frequency
(1/10 th of the
differential data rate)
Signaling rate
Min
Typ
Max
25
−
340
−
−
3.4
)
s
(
ct
u
d
o
Differential output timings
r
P
e
MHz
Gbps
Value
Symbol
Parameter
Differential data and
clock output rise/fall
times
tr
tf
tPLH
tPHL
Table 22.
Skew times
P
e
bs
)
(s
t
c
u
d
o
r
Parameter
t
e
l
o
tSK(O)
s
b
O
80% to 20% of VOD
Pulse skew
tSK(D)
Intra-pair differential
skew
tSK(CC)
Output channel to
channel skew
Typ
Max
75
150
240
ps
75
150
240
ps
250
−
800
ps
250
−
800
ps
Value
Test condition
Inter-pair channel-tochannel output skew
tSK(P)
Unit
Min
t
e
l
o
20% to 80% of VOD
Differential low to high Alternating 1 and 0 pattern at
propagation delay
slow and fast data rates
Differential high to low Measure at 50% VOD between
input to output
propagation delay
Symbol
O
Test condition
| tPLH - tPHL |
Difference in propagation delay
(tPLH or tPHL) among all output
channels
Unit
Min
Typ
Max
−
−
100
ps
−
25
80
ps
−
−
44
ps
−
50
125
ps
b. The timing values in this section are tested during characterization and are guaranteed by design and simulation. Not
tested in production.
Doc ID 14855 Rev 5
27/48
DC and AC characteristics
Table 23.
STDVE001A
Turn-on and turn-off times
Value
Symbol
tON
tOFF
Table 24.
Parameter
Test condition
Unit
Min
Typ
Max
TMDS output enable
time
Time from
OE_N to OUT ±
change from tristate to active
−
12
20
ns
TMDS output disable
time
Time from
OE_N to OUT ±
change from
active to tristate
−
6
10
ns
Status pins (HPD_INT, HPD_EXT, OE_N)
u
d
o
Value
Symbol
Parameter
Test condition
Min
tPD(HPD)
Propagation delay
(from Y_HPD to the
active port of HPD)
tON/OFF
Switch time
(from port select to the
CL = 10 pF
latest valid status of
HPD)
Table 25.
Symbol
tJIT
CL = 10 pF,
RPU = 1 KΩ
o
s
b
O
)
s
(
t
c
Jitter
du
Parameter
o
r
P
Total jitter(1)
e
t
e
ol
let
−
−
r
P
e
Typ
)
s
(
ct
150
−
ns
50
−
ns
Value
Test condition
PRBS pattern
at 1.6 Gbps
(800 MHz)
Unit
Max
Unit
Min
Typ
Max
−
35
−
ps (p-p)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been
subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr = tf = 50 ps (20% to 80%).
Jitter parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
s
b
O
28/48
Doc ID 14855 Rev 5
STDVE001A
DC and AC characteristics
Dynamic switching characteristics (I2C repeater)
7.5
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%)
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 26.
.
I2C repeater(1)
Symbol
Parameter
Value
Test condition
Unit
Min Typ Max
I2C clock frequency
fSCL
tLOW
Low duration on SCL pin
Standard mode
−
−
100
kHz
Fast mode
−
−
400
kHz
−
−
µs
4.7
400 KHz
see Figure 20
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
1.3
−
−
µs
100 KHz
see Figure 20
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
4.7
−
−
µs
400 KHz
see Figure 20
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
1.3
−
−
µs
100 KHz
see Figure 20
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
4.0
−
−
µs
400 KHz
see Figure 20
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
0.6
−
−
µs
e
t
e
ol
d
o
r
P
e
t
e
l
o
s
b
O
tHIGH
High duration on SCL
pin
)
(s
du
o
r
P
s
b
O
t
c
u
Low duration on SCL pin
tLOW
)
s
(
ct
100 KHz
see Figure 20
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
Doc ID 14855 Rev 5
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DC and AC characteristics
Table 26.
STDVE001A
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min Typ Max
High duration on SCL
pin
tHIGH
100 KHz
see Figure 20
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
4.0
−
−
µs
400 KHz
see Figure 20
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
Depends on input signal rise time. Includes the 20%
time intervals on both transitions.
0.6
−
−
µs
−
t
c
u
−
250
µs
(s)
Propagation delay
400 KHz
waveform 1 (Figure 18)
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
tPLH
Propagation delay
400 KHz
waveform 1 (Figure 18)
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
300
µs
tPHL
Propagation delay
400 KHz
waveform 1 (Figure 18)
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
250
ns
tPLH
Propagation delay
400 KHz
waveform 1 (Figure 18)
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
450
ns
tPHL
Propagation delay
100 KHz
waveform 1 (Figure 18)
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
250
ns
Propagation delay
100 KHz
waveform 1 (Figure 18)
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
300
ns
Propagation delay
100 KHz
waveform 1 (Figure 18)
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
250
ns
Propagation delay
100 KHz
waveform 1 (Figure 18)
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
450
ns
tPHL
s
b
O
tPHL
tPLH
30/48
r
P
e
let
o
s
b
O
)
s
(
t
c
u
d
o
r
P
e
t
e
l
o
tPLH
od
Doc ID 14855 Rev 5
STDVE001A
DC and AC characteristics
I2C repeater(1) (continued)
Table 26.
Value
Symbol
Parameter
Test condition
Unit
Min Typ Max
400 KHz
waveform 1 (Figure 18)(2)
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
300
ns
400 KHz
waveform 1(2)
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
300
ns
100 KHz
waveform 1 (Figure 18) (2)
voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 KΩ
−
−
300
Output fall time
tf
−
−
300
ns
−
−
300
ns
400 KHz
waveform 1 (Figure 18)(2), voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 KΩ
−
−
300
ns
100 KHz
waveform 1(2), voltage on line = 5 V, Cmax = 400 pF,
Rmax = 2 KΩ
−
− 1000 ns
−
− 1000 ns
100 KHz
waveform 1 (Figure 18)(2)
voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 KΩ
400 KHz
waveform 1 (Figure 18)(2), voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 KΩ
o
s
b
O
)
tr
Output rise time
s
(
t
c
u
d
o
r
P
e
od
r
P
e
let
Output rise time
tr
ns
t
c
u
Output fall time
tf
(s)
100 KHz
waveform 1 (Figure 18)(2), voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 KΩ
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in
production.
t
e
l
o
2. The tr transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load
resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Refer to Figure 10.
s
b
O
Table 27.
Symbol
ESD performance
Parameter
Test conditions
Min
Typ
Max
Unit
TMDS I/Os
Human body model
−
±5
−
kV
Other I/Os
Human body model
−
±2
−
kV
ESD
Doc ID 14855 Rev 5
31/48
DC and AC characteristics
Figure 8.
STDVE001A
Test circuit for electrical characteristics
6##
#,
6/54
6).
6).
0ULSE
GENERATOR
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)
s
(
ct
!-6
1. CL = load capacitance: include jig and probe capacitance.
u
d
o
2. RT = termination resistance; should be equal to ZOUT of the pulse generator.
Figure 9.
TMDS output driver
r
P
e
6##
t
e
l
o
bs
24
24
-O
:/ 24
4-$3
)
s
(
ct
u
d
o
DRIVER
4-$3
:/ 24
RECEIVER
r
P
e
t
e
l
o
s
b
O
32/48
#36
1. ZO = characteristic impedance of the cable.
2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50 Ω.
Doc ID 14855 Rev 5
STDVE001A
DC and AC characteristics
Figure 10. Test circuit for HDMI receiver and driver
)
s
(
ct
u
d
o
1. RT = 50 Ω.
t
e
l
o
Figure 11. Test circuit for turn-on and turn-off times
e
t
e
l
du
o
r
P
6
b
O
so
)
(s
ct
6
6
r
P
e
s
b
O
#,
6).
6##
6
34$6%!
6).
6
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2%84
0ULSE
GENERATOR
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!-6
1. CL = 5 pF.
Doc ID 14855 Rev 5
33/48
DC and AC characteristics
STDVE001A
Figure 12. Test circuit for short-circuit output current
)3#
4-$3
DRIVER
6OR6
)
s
(
ct
#36
Figure 13. Propagation delays
u
d
o
r
P
e
6!
6##
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6#-
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6#-
6"
)-
s
b
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6##n
6
s
(
t
c
6)$
6)$P
P
6)$
du
e
t
e
ol
s
b
O
/UTPUT
6
o
r
P
6
T0,(
T0(,
6/$/
6/$P
P
6DIFFERENTIAL
6/$5
TR
TF
!-
34/48
Doc ID 14855 Rev 5
STDVE001A
DC and AC characteristics
Figure 14. Turn-on and turn-off times
6
3($.?.
6
6
6
T/&&
T/.
6/54 WHEN6 )$ M6
6/54
WHEN6 )$
M6
6/(
6
T/&&
6/54 WHEN6 )$
M6
6/54
WHEN6 )$ M6
u
d
o
r
P
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t
e
l
o
)
(s
)
s
(
ct
T/.
s
b
O
6
6/,
!-
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Doc ID 14855 Rev 5
35/48
DC and AC characteristics
STDVE001A
Figure 15. tSK(O)
6
6
$ATA).
6
T0(,8
T0,(8
6/(
6
6
)
s
(
ct
$ATA/54ATPORT
u
d
o
T3+/
T3+/
r
P
e
t
e
l
o
$ATA/54ATPORT
bs
T0,(9
)
s
(
ct
-O
6/,
6/(
6
6/,
T0(,9
T3+/ \T0,(9nT0,(8\OR\T0(,9nT0(,8\
Figure 16. tSK(P)
!-
u
d
o
r
P
e
t
e
l
o
s
b
O
)NPUT
6
6
6
T0,(
T0(,
6/(
6
/UTPUT
6/,
T3+0 \T0(,nT0,(
\
!-
36/48
Doc ID 14855 Rev 5
STDVE001A
DC and AC characteristics
Figure 17. tSK(D)
69
6/(
6:
6/,
T3+$
!-
)
s
(
ct
Figure 18. AC waveform 1 (I2C lines)
6
)NPUT
6
bs
6
(s)
r
P
e
t
e
l
o
40(,
/UTPUT
u
d
o
6
-O
6
40,(
6
6
T4(,
6/,
T4,(
t
c
u
!-
d
o
r
Figure 19. Test circuit for AC measurements (I2C lines)
P
e
t
e
l
o
bs
05,3%
'%.%2!4/2
O
6##
6##
6).
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#,
4ESTCIRCUITFOROPENDRAINOUTPUTS
!-
1. RL = load resistor; 1.35 kΩ.
2. CL= load capacitance includes jig and probe capacitance; 7 pF.
3. RT = termination resistance should be equal to ZOUT of pulse generator.
Doc ID 14855 Rev 5
37/48
DC and AC characteristics
STDVE001A
Figure 20. I2C bus timing
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
38/48
Doc ID 14855 Rev 5
STDVE001A
Application information
8
Application information
8.1
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to
always apply VCC before applying any signals to the input/output or control pins.
8.2
Power supply requirements
Bypass each of the VCC pins with 0.1 μF and 1 nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as
possible.
)
s
(
ct
All VCC pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected
from each VCC pin directly to ground to filter supply noise. The maximum power supply
variation can only be ± 5% as per the HDMI specifications.
u
d
o
r
P
e
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
8.3
t
e
l
o
Differential traces
s
b
O
The high-speed TMDS inputs are the most critical parts for the device. There are several
considerations to minimize discontinuities on these transmission lines between the
connectors and the device.
)
(s
a)
Maintain 100-Ω differential transmission line impedance into and out of the
STDVE001A.
b)
Keep an uninterrupted ground plane below the high-speed I/Os.
c)
Keep the ground-path vias to the device as close as possible to allow the shortest
return current path.
d)
Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
8.4
Output trace characteristics affect the performance of the STDVE001A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
I2C lines application information
A typical application is shown in the figure below. In the example, the system master is
running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at
100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz.
Master devices can be placed on either bus.
Doc ID 14855 Rev 5
39/48
Application information
STDVE001A
Figure 21. Typical application of I2C bus system
6
6
3$!
3$!
3$!
3$!
3#,
3#,
3#,
3#,
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u
d
o
)
s
(
ct
!-6
The STDVE001A DDC lines are 5 V tolerant; so it does not require any extra circuitry to
translate between the different bus voltages.
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
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s
b
O
40/48
Doc ID 14855 Rev 5
STDVE001A
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 22. TQFP48 (7 x 7 mm) package outline
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
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Package mechanical data
Table 28.
STDVE001A
TQFP48 (7 x 7 mm) mechanical data
Millimeters
Symbol
Min
Typ
Max
A
-
-
1.20
A1
0.05
0.10
0.15
A2
0.95
1.00
1.05
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
L
0.45
0.60
L1
−
1.00
T
0.70
0.15
T1
0.10
0.13
1.15
a
0°
−
7°
b
0.17
b1
0.17
e
−
o
s
b
O
)
−
ccc / ddd
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7.10
0.75
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P
du
−
0.20
0.22
0.27
0.20
0.23
0.500
−
0.08
−
STDVE001A
Package mechanical data
Figure 23. TQFP48 (7 x 7 mm) footprint recommendation
)
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Package mechanical data
STDVE001A
Figure 24. TQFP48 (7 x 7 mm) tape and reel information
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STDVE001A
Package mechanical data
Figure 25. QFN48 (7 x 7 mm) package outline
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Package mechanical data
Table 29.
STDVE001A
QFN48 (7 x 7 mm) package mechanical data
Millimeters
Symbol
Min
Typ
Max
A
0.80
0.90
1.00
A1
−
0.02
0.05
A2
−
0.65
1.00
A3
−
0.25
−
b
0.18
0.23
0.30
D
6.85
7.00
7.15
D2
2.25
4.70
E
6.85
7.00
E2
2.25
4.70
e
0.45
0.50
L
0.30
0.40
ddd
−
e
t
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l
−
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5.25
Pr
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7.15
5.25
0.55
0.50
0.08
STDVE001A
10
Revision history
Revision history
Table 30.
Document revision history
Date
Revision
02-Jul-2008
1
Initial release.
21-Jul-2008
2
Modified: Figure 2 and Section 5: Functional description on page 14
Replaced ‘equation’ with ‘equalizer in the Features section.
28-Jul-2009
3
Document status promoted from preliminary data to datasheet.
Updated: ESD values.
4
Document reformatted, updated Features, Section 5, title of
Figure 11, replaced VDD by VCC in Table 2, corrected typo in Table 1,
to Table 3, Table 6, Table 8 to Table 10, Table 13 to Table 16,
Table 19, Table 20, Table 22, Table 24 to Table 26, Figure 1,
Figure 2, Figure 4 to Figure 6, Figure 8 to Figure 19, Figure 21,
Section 4, Section 5, Section 6, Section 8, removed Table 24 - DDC
I/O pins.
06-Dec-2010
30-Aug-2011
Changes
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Changed the maximum value of parameter A to 1.20 in Table 28.
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STDVE001A
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