STH2N120K5-2AG

STH2N120K5-2AG Datasheet Automotive-grade N-channel 1200 V, 7.25 Ω typ., 1.5 A, MDmesh K5 Power MOSFET in an H²PAK-2 package Features TAB 2 Order code VDS RDS(on) max. ID PTOT STH2N120K5-2AG 1200 V 10 Ω 1.5 A 60 W 3 1 H2PAK-2 D(TAB) • • AEC-Q101 qualified Industry’s lowest RDS(on) x area • • • Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Applications • Switching applications G(1) Description S(2, 3) DTG1S23NZ This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status STH2N120K5-2AG Product summary(1) Order code STH2N120K5-2AG Marking 2N120K5 Package H²PAK-2 Packing Tape and reel 1. HTRB test was performed at 80% of V(BR)DSS according to AEC-Q101 rev. C. All other tests were performed according to AEC-Q101 rev. D. DS12486 - Rev 5 - June 2020 For further information contact your local STMicroelectronics sales office. www.st.com STH2N120K5-2AG Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS ID Parameter Value Unit Gate-source voltage ±30 V Drain current (continuous) at TC = 25 °C 1.5 Drain current (continuous) at TC = 100 °C 1 A IDM(1) Drain current (pulsed) 2.5 A PTOT Total power dissipation at TC = 25 °C 60 W dv/dt(2) Peak diode recovery voltage slope 4.5 V/ns dv/dt(3) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature range -55 to 150 °C Value Unit TJ Operating junction temperature range 1. Pulse width is limited by safe operating area. 2. ISD ≤ 1.5 A, di/dt = 100 A/μs, VDS (peak) < V(BR)DSS, VDD = 80% V(BR)DSS. 3. VDS ≤ 960 V. Table 2. Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.08 Rthj-pcb(1) Thermal resistance junction-pcb 30 °C/W 1. When mounted on an 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol (1) Parameter Value Unit IAR Avalanche current, repetitive or not repetitive 0.5 A EAS(2) Single pulse avalanche energy 80 mJ 1. Pulse width is limited by TJ max. 2. Starting TJ = 25 °C, ID = IAR, VDD = 50 V. DS12486 - Rev 5 page 2/14 STH2N120K5-2AG Electrical characteristics 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage Min. VGS = 0 V, ID = 1 mA Typ. Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 0.5 A VGS = 0 V, VDS = 1200 V, TC = 125 Unit 1200 V VGS = 0 V, VDS = 1200 V IDSS Max. 0.5 °C(1) µA 100 ±100 nA 3 4 V 7.25 10 Ω Min. Typ. Max. Unit - 124 - - 13 - - 0.5 - - 15 - 2 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Co(tr)(1) Co(er)(2) Time-related equivalent capacitance Energy-related equivalent capacitance RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V pF VGS = 0 V, VDS = 0 to 960 V f = 1 MHz, ID = 0 A VDD = 960 V, ID = 1.5 A, VGS = 0 to 10 V (see Figure 13. Test circuit for gate charge behavior) pF - 5 - - 16 - - 5.3 - - 0.8 - - 3.5 - Ω nC 1. Co(tr) is a constant capacitance value giving the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value giving the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS12486 - Rev 5 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 600 V, ID = 0.75 A, - 10.3 - Rise time RG = 4.7 Ω, VGS = 10 V - 7.8 - Turn-off delay time (see Figure 12. Test circuit for resistive load switching times and Figure 17. Switching time waveform) - 34 - - 39 - Fall time Unit ns page 3/14 STH2N120K5-2AG Electrical characteristics Table 7. Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 1.5 A ISDM(1) Source-drain current (pulsed) - 2.5 A VSD(2) Forward on voltage VGS = 0 V, ISD = 1.5 A - 1.5 V trr Reverse recovery time ISD = 1.5 A, di/dt = 100 A/µs, - 350 ns Qrr Reverse recovery charge VDD = 60 V - 1.35 µC Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 7.7 A trr Reverse recovery time ISD = 1.5 A, di/dt = 100 A/µs, - 600 ns Qrr Reverse recovery charge VDD = 60 V, TJ = 150 °C - 2.09 µC IRRM Reverse recovery current (see Figure 14. Test circuit for inductive load switching and diode recovery times) - 7.7 A IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS12486 - Rev 5 page 4/14 STH2N120K5-2AG Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area GADG050320181141SOA ID (A) Operation in this area is limited by R DS(on) tp = 10 µs 100 tp = 100 µs 10-1 Single pulse, TC = 25 °C TJ ≤150 °C 10-2 tp = 1 ms tp = 10 ms 10-3 10-1 100 101 102 103 VDS (V) Figure 3. Output characteristics ID (A) Figure 4. Transfer characteristics ID (A) GADG050320181127OCH VGS = 8, 9, 10 V 2.5 GADG050320181127TCH 2.5 2 VDS = 30 V 2 VGS = 7 V 1.5 1.5 VGS = 6 V 1 1 VGS = 5 V 0.5 0 0 8 16 24 0.5 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) RDS(on) (Ω) 800 8.5 600 8 400 7.5 200 7 0 Qg (nC) 6.5 0 VDS VDD = 960 V ID = 1.5 A 12 8 2 4 6 8 VGS (V) Figure 6. Static drain-source on-resistance GADG050320181127QVG VDS (V) 16 0 0 GADG050320181140RID VGS = 10 V Qgs 4 Qgd 0 0 DS12486 - Rev 5 2 4 6 0.5 1 1.5 ID (A) page 5/14 STH2N120K5-2AG Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG050320181128CVR VGS(th) (norm.) 10 3 1.2 CISS 10 2 10 1 f = 1 MHz 0.8 CRSS 10 0 10 1 0.6 0.4 -75 VDS (V) 10 2 -25 25 75 125 Tj (°C) Figure 10. Normalized V(BR)DSS vs temperature Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) ID = 100 µA 1 COSS 10 0 10 -1 10 -1 GADG050320181127VTH V(BR)DSS (norm.) GADG050320181128RON GADG050320181129BDV 2.5 1.08 ID = 1 mA VGS = 10 V 2 1.5 1 1 0.92 0.5 0 -75 -25 25 75 125 0.84 -75 Tj (°C) -25 25 75 125 Tj (°C) Figure 11. Source- drain diode forward characteristics VSD (V) GADG050320181128SDF TJ = -55 °C 1 TJ = 25 °C 0.8 TJ = 150 °C 0.6 0.4 0 DS12486 - Rev 5 0.5 1 1.5 ISD (A) page 6/14 STH2N120K5-2AG Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior VDD RL RL 2200 + μF 3.3 μF VDD VD IG= CONST VGS + pulse width RG VGS D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v10 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A VD 100 µH fast diode B B B 3.3 µF D G + Figure 15. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 17. Switching time waveform Figure 16. Unclamped inductive waveform ton V(BR)DSS td(on) toff td(off) tr tf VD 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS12486 - Rev 5 page 7/14 STH2N120K5-2AG Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 H²PAK-2 package information Figure 18. H²PAK-2 package outline 8159712_9 DS12486 - Rev 5 page 8/14 STH2N120K5-2AG H²PAK-2 package information Table 8. H²PAK-2 package mechanical data Dim. mm Min. Typ. Max. A 4.30 4.70 A1 0.03 0.20 C 1.17 1.37 D 8.95 9.35 e 4.98 5.18 E 0.50 0.90 F 0.78 0.85 F2 1.14 1.70 H 10.00 10.40 H1 7.40 J1 2.49 2.69 L 15.30 15.80 L1 1.27 1.40 L2 4.93 5.23 L3 6.85 7.25 L4 1.50 1.70 M 2.60 2.90 R 0.20 0.60 V 0° 8° - 7.80 Figure 19. H²PAK-2 recommended footprint 8159712_9 Note: DS12486 - Rev 5 Dimensions are in mm. page 9/14 STH2N120K5-2AG Packing information 4.2 Packing information Figure 20. Tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F K0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v2 DS12486 - Rev 5 page 10/14 STH2N120K5-2AG Packing information Figure 21. Reel outline T REEL DIMENSIONS 40 mm min. Access hole At slot location B D C N A G measured Tape slot In core for Full radius At hub Tape start Table 9. Tape and reel mechanical data Tape Dim. DS12486 - Rev 5 Reel mm mm Dim. Min. Max. Min. Max. A0 10.5 10.7 A B0 15.7 15.9 B 1.5 D 1.5 1.6 C 12.8 D1 1.59 1.61 D 20.2 E 1.65 1.85 G 24.4 F 11.4 11.6 N 100 K0 4.8 5.0 T P0 3.9 4.1 P1 11.9 12.1 Base quantity 1000 P2 1.9 2.1 Bulk quantity 1000 R 50 T 0.25 0.35 W 23.7 24.3 330 13.2 26.4 30.4 page 11/14 STH2N120K5-2AG Revision history Table 10. Document revision history DS12486 - Rev 5 Date Version Changes 23-Mar-2018 1 30-Jul-2018 2 31-Jul-2018 3 Updated the current table. The date for revision 2 was erroneously reported as "19-Jun-2018" instead of "30-Jul-2018". 05-Sep-2018 4 Updated IDSS parameter in Table 4. Static. 16-Jun-2020 5 Updated Section 4 Package information. Initial release. The document status is preliminary data. The document status was promoted from preliminary to production data. Updated title and features on cover page. page 12/14 STH2N120K5-2AG Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 H²PAK-2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DS12486 - Rev 5 page 13/14 STH2N120K5-2AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS12486 - Rev 5 page 14/14