STL13NM60N

STL13NM60N N-channel 600 V, 0.320 Ω, 10 A PowerFLAT™ (8x8) HV MDmesh™ II Power MOSFET Features Order code STL13NM60N VDSS @ TJmax 650 V RDS(on) max < 0.385 Ω ID 10 A (1) 1. The value is rated according to Rthj-case ■ ■ ■ 100% avalanche tested Low input capacitance and gate charge Low gate input resistance Application Switching applications Description This device is a N-channel Power MOSFETs made using the second generation of MDmesh™ technology. This revolutionary transistor associates a new vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Figure 1. Internal schematic diagram Table 1. Device summary Marking 13NM60N Package PowerFLAT™ (8x8) HV Packaging Tape and reel Order code STL13NM60N May 2011 Doc ID 018870 Rev 1 1/14 www.st.com 14 Contents STL13NM60N Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 Test circuits .............................................. 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 Doc ID 018870 Rev 1 STL13NM60N Electrical ratings 1 Electrical ratings Table 2. Symbol VDS VGS ID (1) Absolute maximum ratings Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C (steady state) Total dissipation at TC = 25 °C (steady state) Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Peak diode recovery voltage slope Storage temperature Max. operating junction temperature Value 600 ± 25 10 6.5 1.9 1.1 7.6 3 90 3 93 15 - 55 to 150 150 Unit V V A A A A A W W A mJ V/ns °C °C ID (1) ID(2) ID(2) IDM (2),(3) PTOT (3) PTOT(1) IAR EAS dv/dt (4) Tstg Tj 1. The value is rated according to Rthj-case 2. Pulse width limited by safe operating area 3. When mounted on FR-4 board of inch², 2oz Cu 4. ISD ≤ 10 A, di/dt ≤ 400 A/µs, VDSpeak ≤ V(BR)DSS, VDD = 80% V(BR)DSS Table 3. Symbol Rthj-case Rthj-amb(1) Thermal data Parameter Thermal resistance junction-case max Thermal resistance junction-amb max Value 1.38 45 Unit °C/W °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu Doc ID 018870 Rev 1 3/14 Electrical characteristics STL13NM60N 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On /off states Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 Min. 600 1 100 100 2 3 0.320 4 0.385 Typ. Max. Unit V µA µA nA V Ω VDS = Max rating Zero gate voltage drain current (VGS = 0) VDS = Max rating, TC=125 °C Gate-body leakage current (VDS = 0) VGS = ± 25 V Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source on resistance VGS = 10 V, ID = 5 A Table 5. Symbol Ciss Coss Crss Coss eq.(1) RG Qg Qgs Qgd Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Output equivalent capacitance Intrinsic gate resistance Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 790 60 3.6 135 4.7 30 4 15 Max. Unit pF pF pF pF Ω nC nC nC VDS = 50 V, f = 1 MHz, VGS = 0 - - VDS = 0 to 480 V, VGS = 0 f = 1 MHz open drain VDD = 480 V, ID = 10 A, VGS = 10 V (see Figure 14) - - - - 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS. Table 6. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 10 A, RG = 4.7 Ω, VGS = 10 V (see Figure 18) Min. Typ. 13 25 85 50 Max Unit ns ns ns ns - - 4/14 Doc ID 018870 Rev 1 STL13NM60N Electrical characteristics Table 7. Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 10 A, VGS = 0 ISD = 10 A, di/dt = 100 A/µs VDD = 100 V (see Figure 15) ISD = 10 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 15) Test conditions Min. 340 2 18 290 190 17 Typ. Max. Unit 10 40 1.6 A A V ns µC A ns µC A - 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 018870 Rev 1 5/14 Electrical characteristics STL13NM60N 2.1 Figure 2. Electrical characteristics (curves) Safe operating area Figure 3. K δ=0.5 Thermal impedance Zth PowerFLAT 8x8 HV 0.2 0.1 10 -1 0.05 0.02 0.01 Single pulse 10 -5 10 -2 10 -4 10 -3 10 -2 tp (s) Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized BVDSS vs temperature Figure 7. RDS(on) (Ω) 0.335 0.330 0.325 0.320 0.315 0.310 0.305 0.300 0 Static drain-source on resistance AM09779v1 VGS=10V 1 2 3 4 5 6 7 8 9 10 ID(A) 6/14 Doc ID 018870 Rev 1 STL13NM60N Figure 8. Gate charge vs gate-source voltage Figure 9. Electrical characteristics Capacitance variations Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Figure 12. Source-drain diode forward characteristics Doc ID 018870 Rev 1 7/14 Test circuits STL13NM60N 3 Test circuits Figure 14. Gate charge test circuit VDD 12V 2200 Figure 13. Switching times test circuit for resistive load 47kΩ 100nF 1kΩ RL VGS VD RG PW D.U.T. μF 3.3 μF VDD Vi=20V=VGMAX 2200 μF IG=CONST 2.7kΩ 47kΩ PW 1kΩ 100Ω D.U.T. VG AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A D G S B 25 Ω D.U.T. A FAST DIODE B A L=100μH B D G 3.3 μF 1000 μF L VD 2200 μF 3.3 μF VDD VDD ID RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform V(BR)DSS VD Figure 18. Switching time waveform ton tdon tr toff tdoff tf 90% IDM 90% 10% ID VDD VDD 0 10% VDS 90% VGS AM01472v1 0 10% AM01473v1 8/14 Doc ID 018870 Rev 1 STL13NM60N Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 018870 Rev 1 9/14 Package mechanical data STL13NM60N Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. A A1 b c D E D2 E2 e L 0.40 7.05 4.15 0.95 0.80 Typ. 0.90 0.02 1.00 0.10 8.00 8.00 7.20 4.30 2.00 0.50 0.60 7.30 4.40 Max. 1.00 0.05 1.05 10/14 Doc ID 018870 Rev 1 STL13NM60N Package mechanical data Figure 19. PowerFLAT™ 8x8 HV drawing mechanical data e L b BOTTOM VIEW PIN#1 ID E2 D 0.40 D2 INDEX AREA E SIDE VIEW TOP VIEW A A1 SEATING PLANE 0.08 C AM05542v1 Doc ID 018870 Rev 1 11/14 Package mechanical data STL13NM60N Figure 20. PowerFLAT™ 8x8 HV recommended footprint 7.30 2.00 1.05 0.60 AM05543v1 12/14 Doc ID 018870 Rev 1 4.40 STL13NM60N Revision history 5 Revision history Table 9. Date 23-May-2011 Document revision history Revision 1 First release. Changes Doc ID 018870 Rev 1 13/14 STL13NM60N Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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