STLC60134S

® STLC60134S TOSCA™ INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT FULLY INTEGRATED AFE FOR ADSL OVERALL 12 BIT RESOLUTION, 1.1MHz SIGNAL BANDWIDTH 8.8MS/s ADC 8.8MS/s DAC THD: -60dB @FULL SCALE 4-BIT DIGITAL INTERFACE TO/FROM THE DMT MODEM 1V FULL SCALE INPUT DIFFERENTIAL ANALOG I/O ACCURATE CONTINUOUS-TIME CHANNEL FILTERING 3rd & 4th ORDER TUNABLE CONTINUOUS TIME LP FILTERS 0.5 WATT AT 3.3V 0.5µm HCMOS5 LA TECHNOLOGY 64 PIN TQFP PACKAGE DESCRIPTION STLC60134S is the Analog Front End of the STMicroelectronics Tosca™ ADSL chipset and when coupled with STLC60135 (DTM modem) alF igure 1. Block Diagram TQFP64 ORDERING NUMBER: STLC60134S lows to get a T1.413 Issue 2 compliant solution. The STLC60134S analog front end handles 2 transmission channels on a balanced 2 wire interconnection; a 16 to 640Kbit/s upstream channel and a 1.536 to 8.192Mbit/s downstream channel. A 256 carrier DMT coding (frequency spacing 4.3125kHz) transforms the downstream channel to a 1MHz bandwidth analog signal (tones 32255) and the upstream channel (tones 8-31) to a 100kHz bandwidth signal on the line. This asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both R-MOS-C TUNING I/V-REF XTAL-DRIVER VCXO DAC ADC G=-15...0dB step=1dB -+ + - ERROR CORRECTION 13 bits TXP TXN ANALOG LOOP MUX 1.1MHz 1.1MHz 138KHz 4 bits DIGITAL IF DIGITAL LOOP AGCtx HC2 HC1 SC2 G=0..31dB step=1dB + -+ RXP(0:1) RXN(0:1) DAC 12 bits MUX 4 bits AGCrx D99TL453 August 1999 1/22 STLC60134S t he ATU-C/ATU-R receivers and transmitters. External low noise driver and input stage used with STLC60134S guarantee low noise performances. The STLC60134S chip can be used at ATU-C and ATU-R ends (behaviour set by LTNT pin). The selection consists mainly of a filter interchange between the RX and TX path. The filters (with a programmable cutoff frequency) use automatic Continuous Time Tuning to avoid time varying phase characteristic which can be of dramatic consequence for DMT modem. It requires few external components, uses a 3.3V supply (a separate 3.0V supply of the digital part is possible) and is packaged in a 64-pin TQFP in order to reduce PCB area. The Receiver (RX) part The DMT signal coming from the line to the STLC60134S is first filtered by the two following external filters: POTS HP filter: Attenuation of speech and POTS signalling Channel filter: Attenuation of echo signal to improve RX dynamic pendent frequency pulling. The DAC which is driven by the CTRLIN pin provides a current output with 8-bit resolution and can be used to tune the XTAL frequency with the help of external components. A time constant between DAC input and VCXO output can be introduced (via the CTLIN interface) and programmed with the help of an external capacitor (on VCOC pin). See chapter ’VCXO’ for the external circuit related to the VCXO. The Digital Interface part The digital part of the STLC60134S can be divided in 3 sections: The data interface converts the multiplexed data from/to the DMT signal processor into valid representation for the TX DAC and RX ADC. It performs also the error correction mechanism needed at the (redundant) ADC output. The control interface allows the board processor to configure the STLC60134S paths (RX/TX gains, filter band, ...) or settings (OSR, vcodac enable, digital / analog loopback,...). The test interface to enable digital (Full Scan, nandtree, loop backs, functional,...) or analog (TIN, TOUT assignation) tests to be performed. DMT Signal A DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct carrier. The frequency separation of each carrier is 4.3125kHz with a total number of 256 carriers (ANSI). For N large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to tradeoff the resulting SNR loss against AD/DA dynamic. A clipping factor (Vpeak/Vrms = ”crest factor”) of 5 will be used resulting in a maximum SNR of 75dB. ADSL DMT signals are nominally sent at -40dBm/Hz ±3dB (-3.65dBm/carrier) with a maximal power of 100mW for down link transmitter and 15.7mW for uplink transmitter. DMT symbols are transmitted without ’windowing’ causing sin (x)/x like sidelobes. For spectral response shaping, the 1st sidelobe level is assumed to be 13dB under the carrier level with an attenuation of -20dB/dec. The minimum SNR + D neede d for DMT carrier demodulation is about (3 ⋅ N + 20) dB with a minimum of 38dB were N is the constellation size of a carrier (in bits). An analog multiplexer allows the selection between two input ports which can be used to select an attenuated(0, 10dB for ex.) version of the signal in case of short loop or large echo. The signal is amplified by a low noise gain stage (031dB) then low-pass filtered to avoid anti-aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise. A 12-bit A/D converter samples the data at 8.832MS/s (or 4.416MS/s in alternative mode), transforms the signal into a digital representation and sends it to the DMT signal processor via the digital interface. The Transmitter (TX) part The 12-bit data words at 8.832MS/s (or 4.416MS/s) coming from the DMT signal processor through the digital interface are transformed by D/A converter into a analog signal. This signal is then filtered to decrease DMT sidelobes level and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signal for the external line driver and in case of short loop provide attenuation (-15...0dB). The VCXO part The VCXO is divided in a XTAL driver and a auxiliary 8 bits DAC for timing recovery. The XTAL driver is able to operate at 35.328MHz and provides an amplitude regulation mechanism to avoid temperature / supply / technology de2/22 STLC60134S Maximum / minimum signal levels The following table gives the transmitted and received signal levels for both ATU-R and ATU-C sides. All the levels are referred to the line voltages (i.e. after hybrid and transformers in TX direction, before hybrid and transformer in RX direction). Note that signal amplitudes shown below are for illustration purpose and depending on the transTable 1. Target Signal Levels (on the line). Parameter RX Max level Max RMS level Min level Min RMS level 839 mVpdif 168 mVrms 54 mVpdif 11 mVrms ATU - C TX 15.8 Vpdif 3.16 Vrms 3.95 Vpdif 791 mVrms RX 3.95 Vpdif 791 mVrms 42 mVpdif 8 mVrms 3.4 Vpdif 671 mVrms 839 mVpdif 168 mVrms ATU - R TX mit power and line impedance signal amplitudes can differ from these values. The reference line impedance for all power calculations is 100Ω. PACKAGE The STLC60134S is packaged in a 64-pin TQFP package (body size 10x10mm, pitch 0.5mm). Table 2. Total Signal Level (on the line). Parameter RX Max level for receiver 4 Vpdif (Long line) ATU - C TX RX 4.2 Vpdif (Short line) ATU - R TX Figure 2. Pin Connection AVDD1 AVDD2 XTALO DVSS2 AVSS1 AVSS2 AVSS6 RXIN1 RXIP1 VCXO XTALI IVCO IREF RES TX2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RES GP0 DVDD2 AVSS3 VRAN VRAP VREF LTNT AVDD3 PDOWN RESETN AVDD4 NC0 NC1 TXN TXP TX3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TX1 TX0 NU3 NU2 NU1 NU0 CTRLIN DVSS1 CLKM CLNIB CLWD RX3 RX2 RX1 RX0 DVDD1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RXIP0 RXIN0 GC1 GC0 VCOC GP2 AVDD6 AVDD5 RES RES AGND RES RES AVSS5 AVSS4 GP1 D98TL355mod 3/22 STLC60134S T able 3. Pin Functions. N. 24 25 26 31 32 38 44 45 46 47 48 49 50 53 55 56 59 60 1 2 7 9 10 11 12 13 14 15 18 19 20 22 33 43 63 64 21 36, 37, 39, 40, 57 8 16 17 23 27 4/22 Name VRAP VREF VRAN TXP TXN AGND VCOC GC0 GC1 RXN0 RXP0 RXN1 RXP1 IREF IVCO VCXO XTALI XTALO TX1 TX0 CTRLIN CLKM CLNIB CLWD RX3 RX2 RX1 RX0 PDOWN LTNT RESETN GP0 GP1 GP2 TX3 TX2 RES RES Function positive voltage reference ADC ground reference ADC negative voltage reference ADC pre driver output pre driver output virtual analog ground (AVDD/2 = 1.65V) VCODAC time constant capacitor External gain control output LSB External gain control output MSB analog receive negative input Gain 0 analog receive positive input Gain 0 analog receive negative input Gain 1 (most sensitive input) analog receive positive input Gain 1 (most sensitive input) current reference TX DAC/DACE current reference VCO DAC VXCO control current XTAL oscillator input pin XTAL oscillator output pin PCB connection Decoupling network Decoupling network Decoupling network Line driver input Line driver input Decoupling network VCODAC cap. Supply ANALOG INTERFACE AVDD3 AVDD3 AVDD3 AVDD4 AVDD4 AVDD5 AVDD5 AVDD5 AVDD5 Echo filter output AVDD5 Echo filter output AVDD5 Echo filter output AVDD5 Echo filter output AVDD5 Decoupling network AVDD2 VCO bias network AVDD1 VCXO filter AVDD1 Crystal + varicap AVDD1 Crystal + varicap AVDD1 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 AVDD AVDD AVDD DVDD2 DVDD2 DIGITAL INTERFACE digital transmit input, parallel data digital transmit input, parallel data serial data input (settings) Async Interface master clock output, f = 35.328MHz Load = CL