STM8AL318x STM8AL3L8x
Automotive 8-bit ultra-low-power MCU, 64-Kbyte Flash, RTC, LCD,
data EEPROM, timers, USARTs, I2C, SPIs, ADC, DAC, COMPs
Datasheet - production data
Features
• AEC-Q100 grade 1 qualified
• Operating conditions
– Operating power supply range 1.8 V to
3.6 V (down to 1.65 V at power down)
– Temp. range: -40 to 85 or 125 °C
• Low-power features
– 5 low-power modes: Wait, Low-power run
(5.9 µA), Low-power wait (3 µA), Activehalt with full RTC (1.4 µA), Halt (400 nA)
– Consumption: 200 µA/MHz+330 µA
– Fast wake up from Halt mode (4.7 µs)
– Ultra-low leakage per I/0: 50 nA
• Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
• Reset and supply management
– Low power, ultra safe BOR reset with 5
programmable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock management
– 32 kHz and 1-16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC and
38 kHz low consumption RC
– Clock security system
• Low-power RTC
– BCD calendar with alarm interrupt,
– Digital calibration with +/- 0.5ppm accuracy
– Advanced anti-tamper detection
• DMA
– 4 ch. for ADC, DACs, SPIs, I2C, USARTs,
Timers, 1 ch. for memory-to-memory
• LCD: 8x40 or 4x44 w/ step-up converter
LQFP80
14x14 mm
LQFP64
10x10 mm
LQFP48
7x7 mm
• 12-bit ADC up to 1 Msps /
28 channels,
– Temp. sensor and internal ref.
voltage
• Memories
– Up to 64 Kbytes of Flash with up to
2 Kbytes of data EEPROM with ECC and
RWW
– Flexible write/read protection modes
– Up to 4 Kbytes of RAM
• 2x12-bit DAC (dual mode) with output buffer
• 2 ultra-low-power comparators
– 1 with fixed threshold and 1 rail to rail
– Wakeup capability
• Timers
– Three 16-bit timers with 2 channels (IC,
OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– One window and one independent
watchdog
– Beeper timer with 1, 2 or 4 kHz frequencies
• Communication interfaces
– Two synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– Three USARTs (IrDA, LIN 1.3, LIN2.0)
• Up to 67 I/Os, all mappable on interrupt vectors
• Fast on-chip programming and non-intrusive
debugging with SWIM, Bootloader using
USART
• 96-bit unique ID
July 2017
This is information on a product in full production.
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STM8AL318x STM8AL3L8x
Table 1. Device summary
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Reference
Part number
STM8AL318x
STM8AL3188, STM8AL3189, STM8AL318A
STM8AL3L8x
STM8AL3L88, STM8AL3L89, STM8AL3L8A
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
2.1
STM8AL ultra-low-power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . .11
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
3.2.1
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Low-power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10
Digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11
Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12
System configuration controller and routing interface . . . . . . . . . . . . . . . 22
3.13
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14
3.15
3.13.1
16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13.2
16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . . 23
3.13.3
8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.1
Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.2
Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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STM8AL318x STM8AL3L8x
3.16
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16.1
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16.2
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16.3
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17
Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1
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Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3.2
Embedded reset and power control block characteristics
9.3.3
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.3.4
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.3.6
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.8
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.9
LCD controller (STM8AL3L8x only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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9.4
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Contents
9.3.10
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.3.11
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.3.12
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.3.13
12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.14
12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.3.15
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
10.1
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
10.2
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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List of tables
STM8AL318x STM8AL3L8x
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
High-density STM8AL3x8x low-power device features and peripheral counts . . . . . . . . . . 13
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
High-density STM8AL3x8x pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Operating lifetime (OLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Total current consumption and timing in low-power run mode at VDD = 1.65 V
to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Total current consumption in low-power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . 77
Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 79
Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 81
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 94
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
List of tables
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 112
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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7
List of figures
STM8AL318x STM8AL3L8x
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
8/132
High-density STM8AL3x8x device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM8AL318A 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8AL3L8A 80-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8AL3189 64-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8AL3L89 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8AL3188 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM8AL3L88 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz(1) . . . . . . . . . . . . . 72
Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . 73
Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . . 75
Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . . . . . . . . 75
Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 76
Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF(1) . . . . . . . . . . . . . . . . . . 77
Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 81
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Typical application with I2C bus and timing diagram(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 114
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 114
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 118
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
List of figures
LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 122
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 125
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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9
Introduction
1
STM8AL318x STM8AL3L8x
Introduction
This document describes the features, pinout, mechanical data and ordering information of
the high-density STM8AL318x and STM8AL3L8x devices (microcontrollers with 64 Kbyte
Flash memory density). These devices are referred to as high-density devices in
STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L MCU
lines reference manual (RM0031) and in the STM8L and STM8AL Flash programming
manual (PM0054).
For more details on the whole STMicroelectronics ultra-low-power family please refer to
Section 3: Functional overview on page 14.
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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STM8AL318x STM8AL3L8x
2
Description
Description
The high-density STM8AL3x8x ultra-low-power devices feature an enhanced STM8 CPU
core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low-power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming.
All high-density STM8AL3x8x microcontrollers feature embedded data EEPROM and lowpower low-voltage single-supply program Flash memory.
The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit
ADC, two DACs, two comparators, a real-time clock, 8x40 or 4x44-segment LCD, four 16-bit
timers, one 8-bit timer, as well as standard communication interfaces such as two SPIs, an
I2C interface, and three USARTs. One 8x40 or 4x44-segment LCD is available on the
STM8AL3L8x devices. The modular design of the peripheral set allows the same
peripherals to be found in different ST microcontroller families including 32-bit families. This
makes any transition to a different family very easy, and simplified even more by the use of
a common set of development tools.
2.1
STM8AL ultra-low-power 8-bit family benefits
High-density STM8AL3x8x devices are part of the STM8AL automotive ultra-low-power 8-bit
family providing the following benefits:
•
•
•
•
Integrated system
–
64 Kbytes of high-density embedded Flash program memory
–
2 Kbytes of data EEPROM
–
4 Kbytes of RAM
–
Internal high-speed and low-power low speed RC.
–
Embedded reset
Ultra-low-power consumption
–
1 µA in Active-halt mode
–
Clock gated system and optimized power management
–
Capability to execute from RAM for Low-power wait mode and Low-power run
mode
Advanced features
–
Up to 16 MIPS at 16 MHz CPU clock frequency
–
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
–
Wide choice of development tools
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60
Description
STM8AL318x STM8AL3L8x
STM8AL ultra-low-power microcontrollers operates either from 1.8 to 3.6 V (down to 1.65 V
at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to
+125 °C temperature ranges.
These features make the STM8AL ultra-low-power microcontroller families suitable for a
wide range of applications.
The devices are offered in three different packages from 48 to 80 pins. Different sets of
peripherals are included depending on the device. Refer to Section 3 for an overview of the
complete range of peripherals proposed in this family.
All STM8AL ultra-low-power products are based on the same architecture with the same
memory mapping and a coherent pinout.
Figure 1 shows the block diagram of the high-density STM8AL3x8x families.
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STM8AL318x STM8AL3L8x
2.2
Description
Device overview
Table 2. High-density STM8AL3x8x low-power device features and peripheral counts
Features
STM8AL3xx8
STM8AL3xx9
Flash (Kbyte)
64
Data EEPROM (Kbyte)
LCD
Timers
Communication
interfaces
STM8AL3xxA
2
8x28 or
4x32(1)
8x36 or 4x40(1)
8x40 or 4x44(1)
Basic
1
(8-bit)
1
(8-bit)
1
(8-bit)
General purpose
3
(16-bit)
3
(16-bit)
3
(16-bit)
Advanced control
1
(16-bit)
1
(16-bit)
1
(16-bit)
SPI
2
2
2
I2C
1
1
1
USART
3
3
3
GPIOs
41
(2)
54(2)
68(2)
12-bit synchronized ADC
(number of channels)
1
(25)
1
(28)
1
(28)
Number of channels
2
2
2
2
2
2
Comparators (COMP1/COMP2)
2
2
2
12-Bit DAC
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external
oscillator
CPU frequency
Operating voltage
16 MHz
1.8 to 3.6 V (down to 1.65 V at power-down) with BOR
-40 to +85 °C / -40 to +125 °C
Operating temperature
Packages
LQFP48
LQFP64
LQFP80
1. STM8AL3L8x versions only.
2. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as
general purpose output only (PA1).
DocID027179 Rev 7
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60
Functional overview
3
STM8AL318x STM8AL3L8x
Functional overview
Figure 1. High-density STM8AL3x8x device block diagram
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1. Legend: AF: alternate function
ADC: Analog-to-digital converter
BOR: Brownout reset
DMA: Direct memory access
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STM8AL318x STM8AL3L8x
Functional overview
DAC: Digital-to-analog converter
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
LCD: Liquid crystal display
POR/PDR: Power on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
3.1
Low-power modes
The high-density STM8AL3x8x devices support five low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
•
Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal
or external interrupt or a Reset is used to exit the microcontroller from Wait mode (WFE
or WFI mode).
•
Low-power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low-power run mode by software and exits from this mode
by software or by a reset.
All interrupts must be masked and are not used to exit the microcontroller from this
mode.
•
Low-power wait mode: This mode is entered when executing a Wait for event in Lowpower run mode. It is similar to Low-power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low-power run mode.
All interrupts must be masked and arenot used to exit the microcontroller from this
mode.
•
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
is triggered by RTC interrupts, external interrupts or reset.
•
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
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60
Functional overview
STM8AL318x STM8AL3L8x
3.2
Central processing unit STM8
3.2.1
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
•
Harvard architecture
•
3-stage pipeline
•
32-bit wide program memory bus - single cycle fetching most instructions
•
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
•
8-bit accumulator
•
24-bit program counter - 16 Mbyte linear memory space
•
16-bit stack pointer - access to a 64 Kbyte level stack
•
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•
20 addressing modes
•
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
•
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
3.2.2
•
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
Interrupt controller
The high-density STM8AL3x8x devices feature a nested vectored interrupt controller:
16/132
•
Nested interrupts with 3 software priority levels
•
32 interrupt vectors with hardware priority
•
Up to 40 external interrupt sources on 11 vectors
•
Trap and reset interrupts
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Functional overview
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
3.3.2
•
VSS1, VDD1, VSS2, VDD2, VSS3, VDD3, VSS4, VDD4= 1.65 to 3.6 V: external power supply
for I/Os and for the internal regulator. Provided externally through VDD pins, the
corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3/VDD4
must not be left unconnected.
•
VSSA, VDDA = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must
be connected to VDD and VSS, respectively.
•
VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
•
VREF+ (for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
externally through VREF+.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. As soon as the 1.8 V BOR threshold is
reached, the option byte loading process starts, either to confirm or modify the default
thresholds, or to disable BOR permanently. In this latter case, the VDD min value at power
down is 1.65 V.
Five BOR thresholds are available through option byte, starting from 1.8 V to 3 V. To reduce
the power consumption in Halt mode, it is possible to automatically switch off the internal
reference voltage (and consequently the BOR) in Halt mode. The device remains in reset
state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt is generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine generates then a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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Functional overview
3.3.3
STM8AL318x STM8AL3L8x
Voltage regulator
The high-density STM8AL3x8x devices embed an internal voltage regulator for generating
the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
•
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
•
Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and
Low-power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness.
Features
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•
Clock prescaler: to get the best compromise between speed and current
consumption, the clock frequency to the CPU and peripherals has to be adjusted by a
programmable prescaler
•
Safe clock switching: Clock sources are adaptable safely on the fly in run mode
through a configuration register.
•
Clock management: To reduce power consumption, the clock controller stops the
clock to the core, individual peripherals or memory.
•
System clock sources: 4 different clock sources are available to drive the system
clock:
–
1-16 MHz High speed external crystal (HSE)
–
16 MHz High speed internal RC oscillator (HSI)
–
32.768 Low speed external crystal (LSE)
–
38 kHz Low speed internal RC (LSI)
•
RTC and LCD clock sources: the above four sources are available to clock the RTC
and the LCD, whatever the system clock.
•
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source is adjustable by the
application program as soon as the code execution starts.
•
Clock security system (CSS): This feature is enabled by software. If a HSE clock
failure occurs, the system clock is automatically switched to HSI.
•
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Functional overview
Figure 2. Clock tree diagram
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STM8AL318x STM8AL3L8x
Electrical parameters
Table 24. Total current consumption in low-power wait mode at VDD = 1.65 V to 3.6 V
Symbol
Conditions(1)
Parameter
Supply current in
IDD(LPW) low-power wait
mode
LSI RC osc.
(at 38 kHz)
all peripherals OFF
LSE external
clock(4)
(32.768 kHz)
Typ.
Max.
TA = -40 °C to 25 °C
3.00
3.30(2)
TA = 85 °C
4.40
9.00(3)
TA = 125 °C
11.00 18.00(3)
TA = -40 °C to 25 °C
2.35
2.70(2)
TA = 85 °C
3.10
3.70(2)
TA = 125 °C
12.0
14.0(2)
Unit
μA
1. No floating I/Os.
2. Guaranteed by characterization results.
3. Tested at 85°C for temperature range A or 125°C for temperature range C.
4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 33.
Figure 18. Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF(1)
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Electrical parameters
STM8AL318x STM8AL3L8x
In the following table, data are based on characterization results, unless otherwise
specified.
Table 25. Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V
Symbol
Conditions(1)
Parameter
LCD OFF(3)
IDD(AH)
Supply current in
Active-halt mode
LSI RC
(at 38 kHz)
LCD ON
(static duty/
external
VLCD) (4)
LCD ON
(1/4 duty/
external
VLCD) (5)
LCD ON
(1/4 duty/
internal
VLCD) (6)
LCD OFF(8)
IDD(AH)
Supply current in
Active-halt mode
LSE external
clock
(32.768 kHz)
(7)
LCD ON
(static duty/
external
VLCD) (4)
LCD ON
(1/4 duty/
external
VLCD) (5)
LCD ON
(1/4 duty/
internal
VLCD) (6)
IDD(WUFAH)
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Supply current
during wakeup
time from Activehalt mode
(using HSI)
-
-
DocID027179 Rev 7
Typ.
Max.(2)
TA = -40 °C to 25 °C
0.90
2.10
TA = 85 °C
1.50
3.40
TA = 125 °C
5.10
12.00
TA = -40 °C to 25 °C
1.40
3.10
TA = 85 °C
1.90
4.30
TA = 125 °C
5.50
13.00
TA = -40 °C to 25 °C
1.90
4.30
TA = 85 °C
2.40
5.40
TA = 125 °C
6.00
15.00
TA = -40 °C to 25 °C
3.90
8.75
TA = 85 °C
4.50
10.20
TA = 125 °C
6.80
16.30
TA = -40 °C to 25 °C
0.50
1.20
TA = 85 °C
0.90
2.10
TA = 125 °C
4.80
11.00
TA = -40 °C to 25 °C
0.85
1.90
TA = 85 °C
1.30
3.20
TA = 125 °C
5.00
12.00
TA = -40 °C to 25 °C
1.50
2.50
TA = 85 °C
1.80
4.20
TA = 125 °C
5.70
14.00
TA = -40 °C to 25 °C
3.40
7.60
TA = 85 °C
3.90
9.20
TA = 125 °C
6.30
15.20
2.40
-
-
Unit
μA
μA
mA
STM8AL318x STM8AL3L8x
Electrical parameters
Table 25. Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V (continued)
Conditions(1)
Symbol
Parameter
tWU_HSI(AH)(9)(10)
Wakeup time from
Active-halt mode
to Run mode
(using HSI)
-
-
tWU_LSI(AH)(9)(10)
Wakeup time from
Active-halt mode
to Run mode
(using LSI)
-
-
Typ.
Max.(2)
Unit
-
4.70
7.00
μs
-
150.0
-
μs
1. No floating I/O, unless otherwise specified.
2. Guaranteed by characterization results.
3. RTC enabled. Clock source = LSI
4. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
5. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
6. LCD enabled with internal LCD booster VLCD = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 33
8. RTC enabled. Clock source = LSE
9. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
10. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 26. Typical current consumption in Active-halt mode, RTC clocked by LSE
external crystal
Symbol
Condition(1)
Parameter
VDD = 1.8 V
IDD(AH) (2)
Supply current in Active-halt
mode
VDD = 3 V
VDD = 3.6 V
Typ.
LSE
1.15
LSE/32(3)
1.05
LSE
1.30
LSE/32(3)
1.20
LSE
1.45
LSE/32(3)
1.35
Unit
µA
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
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Electrical parameters
STM8AL318x STM8AL3L8x
Figure 19. Typical IDD(AH) vs. VDD (LSI clock source)
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STM8AL318x STM8AL3L8x
Electrical parameters
In the following table, data are based on characterization results, unless otherwise
specified.
Table 27. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V
Condition(1)
Symbol
Parameter
IDD(Halt)
Supply current in Halt mode
(ultra-low-power ULP bit =1 in
the PWR_CSR2 register)
Typ.
Max.
TA = -40 °C to 25 °C
0.4
0.9(2)
TA = 85 °C
0.9
2.8(3)
TA = 125 °C
4.4
13(3)
IDD(WUHalt)
Supply current during wakeup
time from Halt mode (using
HSI)
-
2.4
-
tWU_HSI(Halt)(4)(5)
Wakeup time from Halt to Run
mode (using HSI)
-
4.7
7(2)
Wakeup time from Halt mode
to Run mode (using LSI)
-
150
-
tWU_LSI(Halt)
(4)(5)
Unit
µA
mA
µs
1. TA = -40 to 125 °C, no floating I/O, unless otherwise specified.
2. Guaranteed by characterization results.
3. Tested at 85 °C for temperature range A or 125°C for temperature range C.
4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
5. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU.
Figure 20. Typical IDD(Halt) vs. VDD (internal reference voltage OFF)
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Electrical parameters
STM8AL318x STM8AL3L8x
Current consumption of on-chip peripherals
Table 28. Peripheral current consumption
Symbol
Typ.
Parameter
VDD = 3.0 V
IDD(TIM1)
TIM1 supply current(1)
10
IDD(TIM2)
TIM2 supply current (1)
7
IDD(TIM3)
TIM3 supply current (1)
7
IDD(TIM5)
TIM5 supply current (1)
7
IDD(TIM4)
TIM4 timer supply current (1)
3
IDD(USART1)
USART1 supply current (2)
5
IDD(USART2)
USART2 supply current (2)
5
IDD(USART3)
USART3 supply current (2)
5
IDD(SPI1)
SPI1 supply current (2)
3
IDD(SPI2)
SPI2 supply current (2)
3
IDD(I2C1)
I2C1 supply current (2)
4
IDD(DMA1)
DMA1 supply current(2)
3
IDD(WWDG)
WWDG supply current(2)
1
Peripherals ON(3)
63
IDD(ALL)
IDD(ADC1)
ADC1 supply current(4)
1500
IDD(DAC)
DAC supply current(5)
370
IDD(COMP1)
Comparator 1 supply current(6)
IDD(COMP2)
Comparator 2 supply current(6)
IDD(PVD/BOR)
IDD(BOR)
IDD(IDWDG)
µA/MHz
0.160
Slow mode
2
Fast mode
5
Power voltage detector and brownout Reset unit supply
current (7)
2.6
Brownout Reset unit supply current (7)
2.4
Independent watchdog supply current
Unit
including LSI supply
current
0.45
excluding LSI
supply current
0.05
µA
1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, TIM5, USART1, USART2, USART3, SPI1,
SPI2, I2C1, DMA1, WWDG.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
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Electrical parameters
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD /2. Floating DAC output.
6. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
7. Including supply current of internal reference voltage.
Table 29. Current consumption under external reset
Symbol
IDD(RST)
Parameter
Supply current under
external reset (1)
Conditions
PB1/PB3/PA5 pins are
externally tied to VDD
Typ.
VDD = 1.8 V
48
VDD = 3 V
80
VDD = 3.6 V
95
Unit
µA
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
9.3.4
Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
Table 30. HSE external clock characteristics
Symbol
fHSE_ext(1)
Parameter
External clock source
frequency
VHSEH
OSC_IN input pin highlevel voltage
VHSEL
OSC_IN input pin lowlevel voltage
Cin(HSE)(1) OSC_IN input capacitance
ILEAK_HSE
Conditions
OSC_IN input leakage
current
-
Min.
Typ.
Max.
Unit
1
-
16
MHz
0.7 x VDD
-
VDD
VSS
-
0.3 x VDD
-
2.6
-
pF
-
-
±500
nA
V
VSS < VIN < VDD
1. Guaranteed by design.
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Electrical parameters
STM8AL318x STM8AL3L8x
LSE external clock (LSEBYP=1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
Table 31. LSE external clock characteristics
Symbol
fLSE_ext
Parameter
Min.
Typ.
Max.
Unit
-
kHz
External clock source frequency
32.768
-
-
VDD(1)
VLSEH
OSC32_IN input pin high-level voltage
0.7xVDD(1)
VLSEL
OSC32_IN input pin low-level voltage
VSS(1)
-
0.3xVDD(1)
OSC32_IN input capacitance
-
0.6
-
pF
OSC32_IN input leakage current
-
-
±500
nA
Cin(LSE)
ILEAK_LSE
V
1. Guaranteed by characterization results.
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 32. HSE oscillator characteristics
Symbol
Conditions
Min.
Typ.
Max.
Unit
High speed external oscillator
frequency
-
1
-
16
MHz
RF
Feedback resistor
-
-
200
-
kΩ
(1)(2)
Recommended load capacitance
-
-
20
-
pF
C = 20 pF,
fOSC = 16 MHz
-
-
2.5 (startup)
0.7 (stabilized)(3)
fHSE
C
IDD(HSE)
gm
tSU(HSE)(4)
Parameter
HSE oscillator power consumption
-
-
2.5 (startup)
0.46 (stabilized)(3)
-
3.5(3)
-
-
mA/V
1
-
ms
Oscillator transconductance
Startup time
mA
C = 10 pF,
fOSC =16 MHz
VDD is stabilized
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Guaranteed by design.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it varies significantly with the crystal manufacturer.
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Electrical parameters
Figure 21. HSE oscillator circuit diagram
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g mcrit = ( 2 × Π × f HSE ) 2 × R m ( 2Co + C )
2
Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),
Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit
LSE crystal/ceramic resonator oscillator
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
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Electrical parameters
STM8AL318x STM8AL3L8x
Table 33. LSE oscillator characteristics
Symbol
Parameter
fLSE
Low speed external oscillator
frequency
RF
Feedback resistor
C(1)(2)
IDD(LSE)
Conditions
Min.
Typ.
Max.
Unit
-
-
32.768
-
kHz
ΔV = 200 mV
-
1.2
-
MΩ
-
-
8
-
pF
VDD = 1.8 V
-
450
-
VDD = 3 V
-
600
-
-
Recommended load capacitance
LSE oscillator power consumption
VDD = 3.6 V
Oscillator transconductance
gm
tSU(LSE)
(4)
-
Startup time
3
VDD is stabilized
nA
750
-
(3)
-
-
µA/V
-
1
-
s
1. C=CL1=CL2 is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Guaranteed by design.
4.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it varies significantly with the crystal manufacturer.
Figure 22. LSE oscillator circuit diagram
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Internal clock sources
Subject to general operating conditions for VDD, and TA.
High speed internal RC oscillator (HSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
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Electrical parameters
Table 34. HSI oscillator characteristics
Symbol
fHSI
ACCHSI
Conditions(1)
Parameter
Min.
Typ.
Max.
Unit
MHz
Frequency
VDD = 3.0 V
-
16
-
HSI oscillator user
trimming accuracy
Trimmed by the application for any VDD
and TA conditions
-1
-
1
-5
-
5
Trimming code ≠ multiple of 16
-
0.4
0.7(2)
Trimming code = multiple of 16
-
-
± 1.5(2)
HSI oscillator accuracy VDD ≤1.8 V≤ VDD ≤ 3.6 V
(factory calibrated)
-40 °C ≤TA ≤ 125 °C
%
TRIM
HSI user trimming
step(2)
tsu(HSI)
HSI oscillator setup
time (wakeup time)
-
-
3.7
6 (3)
µs
IDD(HSI)
HSI oscillator power
consumption
-
-
100
140(3)
µA
%
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
3. Guaranteed by design.
Figure 23. Typical HSI frequency vs. VDD
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Electrical parameters
STM8AL318x STM8AL3L8x
Low speed internal RC oscillator (LSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 35. LSI oscillator characteristics
Symbol
fLSI
Parameter
Conditions(1)
Min.
Typ.
Max.
Unit
-
26
38
56
kHz
Frequency
tsu(LSI)
LSI oscillator wakeup time
D(LSI)
LSI oscillator frequency
drift(3)
0 °C ≤TA ≤ 85 °C
(2)
-
-
200
-12
-
11
µs
%
1. VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.
2. Guaranteed by design.
3. This is a deviation for an individual part, once the initial frequency has been measured.
Figure 24. Typical LSI clock source frequency vs. VDD
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9.3.5
Memory characteristics
TA = -40 to 125 °C unless otherwise specified.
Table 36. RAM and hardware registers
Symbol
VRM
Parameter
Data retention mode
(1)
Conditions
Min.
Typ.
Max.
Unit
Halt mode (or Reset)
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization results.
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STM8AL318x STM8AL3L8x
Electrical parameters
Flash memory
Table 37. Flash program memory/data EEPROM memory
Symbol
VDD
tprog
Iprog
Parameter
Conditions
Min.
fSYSCLK = 16 MHz
1.65
-
3.6
V
Programming time for 1 or 128 byte (block)
erase/write cycles (on programmed byte)
-
-
6
-
ms
Programming time for 1 to 128 byte (block)
write cycles (on erased byte)
-
-
3
-
ms
TA=+25 °C, VDD = 3.0 V
-
TA=+25 °C, VDD = 1.8 V
-
Operating voltage
(all modes, read/write/erase)
Programming/ erasing consumption
Typ. Max.
-
0.7
-
Unit
mA
Table 38. Flash program memory
Symbol
Parameter
Conditions
Min.
Max.
Unit
TWE
Temperature for writing and erasing
-
-40
125
°C
NWE
Flash program memory endurance
(erase/write cycles)(1)
TA= 25 °C
1000
-
cycles
tRET
Data retention time
TA= 25 °C
40
-
TA= 55 °C
20
-
years
1. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a write/erase operation
addresses a single byte.
Data memory
Table 39. Data memory
Symbol
Parameter
TWE
Temperature for writing and erasing
NWE
Data memory endurance
(erase/write cycles)(1)
tRET
Data retention time
Conditions
Min.
Max.
Unit
-
-40
125
°C
TA= 25 °C
300 k
-
TA= -40 to 125 °C
100 k(2)
-
TA= 25 °C
40(2) (3)
-
TA= 55 °C
(2) (3)
-
20
cycles
years
1. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a write/erase operation
addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is available in a
separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.
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117
Electrical parameters
9.3.6
STM8AL318x STM8AL3L8x
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 40. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
9.3.7
Description
Negative
injection
Positive
injection
Injected current on true open-drain pins
-5
+0
Injected current on all 5 V tolerant (FT) pins
-5
+0
Injected current on any other pin
-5
+5
Unit
mA
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
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STM8AL318x STM8AL3L8x
Electrical parameters
Table 41. I/O static characteristics
Symbol
VIL
VIH
Vhys
Ilkg
Conditions(1)
Parameter
Input low-level voltage
Input high-level voltage
Schmitt trigger voltage hysteresis (3)
Input leakage current (4)
Min.
Typ.
Max.
Unit
Vss-0.3
-
0.3 x VDD
V
Input voltage on true
open-drain pins (PC0
and PC1)
with VDD < 2 V
-
5.2(2)
Input voltage on true
open-drain pins (PC0
and PC1)
with VDD ≥ 2 V
-
5.5(2)
Input voltage on all
pins
Input voltage on fivevolt tolerant (FT) pins
with VDD < 2 V
0.70 x VDD
V
-
5.2(2)
Input voltage on fivevolt tolerant (FT) pins
with VDD ≥ 2 V
-
5.5(2)
Input voltage on any
other pin
-
VDD+0.3(2)
Standard I/Os
-
200
-
True open drain I/Os
-
200
-
VSS≤VIN≤VDD
Standard I/Os
-
-
50
VSS≤VIN≤VDD
True open drain I/Os
-
-
200
VSS≤VIN≤VDD
PA0 with high sink LED
driver capability
-
-
200
30(6)
45
60(6)
kΩ
-
5
-
pF
RPU
Weak pull-up equivalent resistor(5)
VIN=VSS
CIO
I/O pin capacitance
-
mV
nA
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. If VIH maximum is not respected, the injection current must be limited externally to IINJ(PIN) maximum.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 28).
6. Guaranteed by characterization results.
DocID027179 Rev 7
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117
Electrical parameters
STM8AL318x STM8AL3L8x
Figure 25. Typical VIL and VIH vs. VDD (standard I/Os)
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Figure 26. Typical VIL and VIH vs. VDD (true open drain I/Os)
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STM8AL318x STM8AL3L8x
Electrical parameters
Figure 27. Typical pull-up resistance RPU vs. VDD with VIN=VSS
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Figure 28. Typical pull-up current Ipu vs. VDD with VIN=VSS
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Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
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117
Electrical parameters
STM8AL318x STM8AL3L8x
Table 42. Output driving current (high sink ports)
I/O
Symbol
Type
Output low-level voltage for an I/O pin
Standard
VOL (1)
Parameter
VOH (2) Output high-level voltage for an I/O pin
Conditions
Min.
Max.
Unit
IIO = +2 mA,
VDD = 3.0 V
-
0.45
V
IIO = +2 mA,
VDD = 1.8 V
-
0.45
V
IIO = +10 mA,
VDD = 3.0 V
-
0.7
V
IIO = -2 mA,
VDD = 3.0 V
VDD-0.45
-
V
IIO = -1 mA,
VDD = 1.8 V
VDD-0.45
-
V
IIO = -10 mA,
VDD = 3.0 V
VDD-0.7
-
V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 16 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD.
Table 43. Output driving current (true open drain ports)
Open drain
I/O
Symbol
Type
VOL
(1)
Parameter
Output low-level voltage for an I/O pin
Conditions
Min.
Max.
IIO = +3 mA,
VDD = 3.0 V
-
0.45
IIO = +1 mA,
VDD = 1.8 V
-
Unit
V
0.45
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Table 44. Output driving current (PA0 with high sink LED driver capability)
IR
I/O
Symbol
Type
VOL (1)
Parameter
Output low-level voltage for an I/O pin
Conditions
Min.
Max.
Unit
IIO = +20 mA,
VDD = 2.0 V
-
0.45
V
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
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STM8AL318x STM8AL3L8x
Electrical parameters
Figure 29. Typical VOL @ VDD = 3.0 V (high sink Figure 30. Typical VOL @ VDD = 1.8 V (high sink
ports)
ports)
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Figure 31. Typical VOL @ VDD = 3.0 V (true open Figure 32. Typical VOL @ VDD = 1.8 V (true open
drain ports)
drain ports)
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#
#
#
#
#
#
#
6/, ;6=
6/, ;6=
)/, ;M!=
)/, ;M!=
BJ
AI
Figure 33. Typical VDD - VOH @ VDD = 3.0 V (high Figure 34. Typical VDD - VOH @ VDD = 1.8 V (high
sink ports)
sink ports)
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#
#
#
#
#
#
#
6$$
6/( ;6=
6$$
6/( ;6=
)/( ;M!=
) /( ;M!=
AI
DocID027179 Rev 7
BJ
95/132
117
Electrical parameters
STM8AL318x STM8AL3L8x
NRST pin
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 45. NRST pin characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VIL(NRST)
NRST input low-level voltage
-
VSS(1)
-
0.8(1)
VIH(NRST)
NRST input high-level voltage (1)
-
1.4(1)
-
VDD(1)
IOL = 2 mA
for 2.7 V ≤VDD ≤ 3.6 V
-
-
IOL = 1.5 mA
for VDD < 2.7 V
-
VOL(NRST)
VHYST
NRST output low-level voltage (1)
V
0.4(1)
-
10%VDD
(2)(3)
-
-
mV
-
30(1)
45
60(1)
kΩ
NRST input filtered pulse
-
-
-
50(3)
NRST input not filtered pulse
-
300(3)
-
-
NRST input hysteresis
-
NRST pull-up equivalent resistor
VF(NRST)
VNF(NRST)
RPU(NRST)
Unit
ns
1. Guaranteed by characterization results.
2. 200 mV min.
3. Guaranteed by design.
Figure 35. Typical NRST pull-up resistance RPU vs. VDD
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STM8AL318x STM8AL3L8x
Electrical parameters
Figure 36. Typical NRST pull-up current Ipu vs. VDD
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The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin goes below the VIL max. level specified in
Table 45. Otherwise the reset is not taken into account internally. For power consumptionsensitive applications, the capacity of the external reset capacitor has to be reduced to limit
the charge/discharge current. If the NRST signal is used to reset the external circuitry, the
user must pay attention to the charge/discharge time of the external capacitor to meet the
reset timing conditions of the external devices. The minimum recommended capacity is 10
nF.
Figure 37. Recommended NRST pin configuration
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DocID027179 Rev 7
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117
Electrical parameters
9.3.8
STM8AL318x STM8AL3L8x
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 46. SPI1 characteristics
Symbol
Conditions(1)
Min.
Max.
Master mode
0
8
Slave mode
0
8
SPI1 clock rise and fall
time
Capacitive load: C = 30 pF
-
30
tsu(NSS)(2)
NSS setup time
Slave mode
4 x 1/fSYSCLK
-
th(NSS)(2)
NSS hold time
Slave mode
80
-
SCK high and low time
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
105
145
Master mode
30
-
Slave mode
3
-
Master mode
15
-
Slave mode
0
-
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
(2)
tw(SCKH)
tw(SCKL)(2)
Parameter
SPI1 clock frequency
tsu(MI) (2)
tsu(SI)(2)
Data input setup time
th(MI) (2)
th(SI)(2)
Data input hold time
ta(SO)(2)(3)
Data output access time
Slave mode
-
3x 1/fSYSCLK
tdis(SO)(2)(4)
30
-
Data output disable time
Slave mode
(2)
Data output valid time
Slave mode (after enable edge)
-
60
tv(MO)(2)
Data output valid time
Master mode (after enable
edge)
-
20
Slave mode (after enable edge)
15
-
Master mode (after enable
edge)
1
-
tv(SO)
th(SO)(2)
th(MO)(2)
Data output hold time
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Guaranteed by characterization results or by design.
3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.
4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.
98/132
DocID027179 Rev 7
Unit
MHz
ns
STM8AL318x STM8AL3L8x
Electrical parameters
Figure 38. SPI1 timing diagram - slave mode and CPHA=0
Figure 39. SPI1 timing diagram - slave mode and CPHA=1(1)
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
DocID027179 Rev 7
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117
Electrical parameters
STM8AL318x STM8AL3L8x
Figure 40. SPI1 timing diagram - master mode(1)
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM8AL318x STM8AL3L8x
Electrical parameters
I2C - Inter IC control interface
Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.
The STM8AL I2C interface (I2C1) meets the requirements of the Standard I2C
communication protocol described in the following table with the restriction mentioned
below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 47. I2C characteristics
Standard mode I2C
Symbol
Parameter
Fast mode I2C(1)
Min.(2)
Max. (2)
Min. (2)
Max. (2)
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
0
-
0
900
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
START condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated START condition setup
time
4.7
-
0.6
-
tsu(STO)
STOP condition setup time
4.0
-
0.6
-
STOP to START condition time (bus
free)
4.7
-
1.3
-
-
400
-
400
tw(STO:STA)
Cb
Capacitive load for each bus line
Unit
μs
ns
μs
pF
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
Note:
For speeds around 200 kHz, the achieved speed has a ± 5% tolerance.
For other speed ranges, the achieved speed has a ± 2% tolerance.
The above variations depend on the accuracy of the external components used.
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Electrical parameters
STM8AL318x STM8AL3L8x
Figure 41. Typical application with I2C bus and timing diagram(1))
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102/132
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STM8AL318x STM8AL3L8x
9.3.9
Electrical parameters
LCD controller (STM8AL3L8x only)
In the following table, data are guaranteed by design, not tested in production.
Table 48. LCD characteristics
Symbol
Parameter
Min.
Typ.
Max.
VLCD
LCD external voltage
-
-
3.6
VLCD0
LCD internal reference voltage 0
-
2.6
-
VLCD1
LCD internal reference voltage 1
-
2.7
-
VLCD2
LCD internal reference voltage 2
-
2.8
-
VLCD3
LCD internal reference voltage 3
-
3.0
-
VLCD4
LCD internal reference voltage 4
-
3.1
-
VLCD5
LCD internal reference voltage 5
-
3.2
-
VLCD6
LCD internal reference voltage 6
-
3.4
-
VLCD7
LCD internal reference voltage 7
-
3.5
-
CEXT
VLCD external capacitance
0.1
1
2
at VDD = 1.8 V
-
3
-
at VDD = 3 V
-
3
-
IDD
Supply
current(1)
Supply current
(1)
Unit
V
µF
µA
RHN(2)
High value resistive network (low drive)
-
6.6
-
MΩ
(3)
Low value resistive network (high drive)
-
240
-
kΩ
V33
Segment/Common higher level voltage
-
-
VLCDx
V34
Segment/Common 3/4 level voltage
-
3/4VLCDx
-
V23
Segment/Common 2/3 level voltage
-
2/3VLCDx
-
V12
Segment/Common 1/2 level voltage
-
1/2VLCDx
-
V13
Segment/Common 1/3 level voltage
-
1/3VLCDx
-
V14
Segment/Common 1/4 level voltage
-
1/4VLCDx
-
V0
Segment/Common lowest level voltage
0
-
-
RLN
V
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
2. RHN is the total high value resistive network.
3. RLN is the total low value resistive network.
VLCD external capacitor (STM8AL3L8x only)
The application achieves a stabilized LCD reference voltage when connecting an external
capacitor CEXT to the VLCD pin. CEXT is specified in Table 48.
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Electrical parameters
9.3.10
STM8AL318x STM8AL3L8x
Embedded reference voltage
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 49. Reference voltage characteristics
Symbol
IREFINT
TS_VREFINT(1)(2)
IBUF(1)
VREFINT out
Parameter
Conditions
Min.
Typ.
Max.
Unit
Internal reference voltage
consumption
-
-
1.4
-
µA
ADC sampling time when reading the
internal reference voltage
-
-
5
10
µs
Internal reference voltage buffer
consumption (used for ADC)
-
-
13.5
25
µA
Reference voltage output
-
Internal reference voltage low-power
buffer consumption (used for
comparators or output)
1.202
(3)
1.224
-
-
Buffer output current
-
Reference voltage output load
tVREFINT(1)
tBUFEN(1)(2)
ILPBUF(1)
IREFOUT(1)(4)
CREFOUT
ACCVREFINT(5)
STABVREFINT
STABVREFINT
1.242
(3)
V
730
1200
nA
-
-
1
µA
-
-
-
50
pF
Internal reference voltage startup
time
-
-
2
3
ms
Internal reference voltage buffer
startup time once enabled
-
-
-
10
µs
Accuracy of VREFINT stored in the
VREFINT_Factory_CONV byte
-
-
-
±5
mV
-
20
50
ppm/°C
Stability of VREFINT over temperature -40 °C ≤TA ≤ 125 °C
Stability of VREFINT over temperature
0 °C ≤TA ≤ 50 °C
-
-
20
ppm/°C
Stability of VREFINT after 1000 hours
-
-
-
TBD
ppm
1. Guaranteed by design.
2. Defined when ADC output reaches its final value ±1/2LSB
3. Tested in production at VDD = 3 V ±10 mV.
4. To guarantee less than 1% VREFOUT deviation
5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.
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9.3.11
Electrical parameters
Temperature sensor
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 50. TS characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
V125 (1)
Sensor reference voltage at 125°C
±5 °C,
0.640
0.660
0.680
V
TL
VSENSOR linearity with temperature
-
±1
±2
°C
Avg_slope
IDD(TEMP)
Average slope
1.59
Consumption
(2)
1.62
-
TSTART(3)
Temperature sensor startup time
-
TS_TEMP
ADC sampling time when reading the
temperature sensor
-
1.65
3.4
6
(2)
mV/°C
(2)
µA
-
10(2)
µs
5
10(2)
µs
1. Tested in production at VDD = 3 V ±10 mV. The 8 LSB of the V125 ADC conversion result are stored in the
TS_Factory_CONV_V125 byte.
2. Guaranteed by design.
3. Defined for ADC output reaching its final value ±1/2LSB.
9.3.12
Comparator characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 51. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
3.6
V
VDDA
Analog supply voltage
-
1.65
R400K
R400K value
-
-
400
-
R10K
R10K value
-
-
10
-
Comparator 1 input
voltage range
-
0.6
Comparator startup time
-
-
7
10
-
-
3
10
-
-
±3
±10
mV
0
1.5
10
mV/1000 h
-
160
260
nA
VIN
tSTART
td
Propagation delay
Voffset
Comparator offset
dVoffset/dt
ICOMP1
(2)
Comparator offset
variation in worst voltage
stress conditions
Current consumption(3)
VDDA = 3.6 V
VIN+ = 0 V
VIN- = VREFINT
TA = 25 ° C
-
VDDA
kΩ
V
µs
1. Guaranteed by characterization results .
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
DocID027179 Rev 7
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117
Electrical parameters
STM8AL318x STM8AL3L8x
In the following table, data are guaranteed by design, not tested in production, unless
otherwise specified.
Table 52. Comparator 2 characteristics
Symbol
VDDA
VIN
Parameter
Min
Analog supply voltage
-
1.65
-
3.6
V
Comparator 2 input voltage range
-
0
-
VDDA
V
Fast mode
-
15
20
Slow mode
-
20
25
1.65 V ≤VDDA ≤2.7 V
-
1.8
3.5
2.7 V ≤VDDA ≤3.6 V
-
2.5
6
1.65 V ≤VDDA ≤2.7 V
-
0.8
2
2.7 V ≤VDDA ≤3.6 V
-
1.2
4
-
-
±4
±20
mV
VDDA = 3.3V
TA = 0 to 50 ° C
V- = VREF+, 3/4
VREF+,
1/2 VREF+, 1/4 VREF+.
-
15
30
ppm
/°C
Fast mode
-
3.5
5
Slow mode
-
0.5
2
tSTART
Comparator startup time
td slow
Propagation delay(2) in slow mode
td fast
Propagation delay(2) in fast mode
Voffset
Comparator offset error
dThreshold/dt
ICOMP2
Typ Max(1) Unit
Conditions
Threshold voltage temperature
coefficient
Current consumption(3)
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
106/132
DocID027179 Rev 7
µs
µA
STM8AL318x STM8AL3L8x
9.3.13
Electrical parameters
12-bit DAC characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 53. DAC characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VDDA
Analog supply voltage
-
1.8
-
3.6
VREF+
Reference supply voltage
-
1.8
-
VDDA
VREF+ = 3.3 V, no
load, middle code
(0x800)
-
130
220
VREF+ = 3.3 V, no
load, worst code
(0x000)
-
220
350
VDDA = 3.3 V, no
load, middle code
(0x800)
-
210
320
VDDA = 3.3 V, no
load, worst code
(0x000)
-
320
520
-
-40
-
125
Resistive load
DACOUT buffer ON
5
-
Output impedance
DACOUT buffer OFF
-
8
10
kΩ
-
-
-
50
pF
DACOUT buffer ON
0.2
-
VDDA - 0.2
V
DACOUT buffer OFF
0
-
VREF+ -1 LSB
V
Settling time (full scale: for a 12bit input code transition between
the lowest and the highest input
codes when DAC_OUT reaches
the final value ±1LSB)
RL ≥5 kΩ, CL≤ 50 pF
-
7
12
µs
Max frequency for a correct
DAC_OUT (@95%) change
Update rate
when small variation of the input
code (from code i to i+1LSB).
RL ≥ 5 kΩ, CL ≤50 pF
-
-
1
Msps
IVREF
IVDDA
TA
RL(1) (2)
RO
CL
(3)
DAC_OUT
(4)
tsettling
Current consumption on VREF+
supply
Current consumption on VDDA
supply
Temperature range
Capacitive load
DAC_OUT voltage
V
µA
°C
kΩ
tWAKEUP
Wakeup time from OFF state.
Input code between lowest and
highest possible codes.
RL ≥5 kΩ, CL≤50 pF
-
9
15
µs
PSRR+
Power supply rejection ratio (to
VDDA) (static DC measurement)
RL≥ 5 kΩ, CL≤50 pF
-
-60
-35
dB
1. Resistive load between DACOUT and GNDA
2. Output on PF0 or PF1
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC
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117
Electrical parameters
STM8AL318x STM8AL3L8x
In the following table, data are based on characterization results, not tested in production.
Table 54. DAC accuracy
Symbol
Parameter
Typ.
Max.(1)
1.5
3
1.5
3
2
4
2
4
±10
±25
No load
DACOUT buffer OFF
±5
±8
DACOUT buffer OFF
±1.5
±5
Conditions
RL ≥5 kΩ, CL≤50 pF
DNL
DACOUT buffer ON(3)
Differential non linearity(2)
No load
DACOUT buffer OFF
RL ≥5 kΩ, CL≤ 50 pF
INL
DACOUT buffer ON(3)
Integral non linearity(4)
No load
DACOUT buffer OFF
RL ≥5 kΩ, CL≤ 50 pF
Offset
Offset1
DACOUT buffer ON(3)
Offset error(5)
Offset error at Code 1 (6)
RL ≥5 kΩ, CL≤ 50 pF
Gain error
Gain
DACOUT buffer ON(3)
error(7)
No load
DACOUT buffer OFF
RL ≥5 kΩ, CL≤ 50 pF
TUE
DACOUT buffer ON(3)
Total unadjusted error
No load -DACOUT buffer OFF
Unit
12-bit
LSB
+0.1/-0.2 +0.2/-0.5
%
+0/-0.2
+0/-0.4
12
30
8
12
12-bit
LSB
1. Not tested in production.
2. Difference between two consecutive codes - 1 LSB.
3. In 48-pin package devices the DAC2 output buffer must be kept off and no load must be applied on the DAC_OUT2 output.
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF
when buffer is ON, and from Code giving 0.2 V and (VDDA -0.2) V when buffer is OFF.
108/132
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Electrical parameters
In the following table, data are guaranteed by design, not tested in production.
Table 55. DAC output on PB4-PB5-PB6(1)
Symbol
Rint
Parameter
Internal resistance
between DAC output and
PB4-PB5-PB6 output
Conditions
Max
2.7 V < VDD < 3.6 V
1.4
2.4 V < VDD < 3.6 V
1.6
2.0 V < VDD < 3.6 V
3.2
1.8 V < VDD < 3.6 V
8.2
Unit
kΩ
1. 32 or 28-pin packages only. The DAC channel is routed either on PB4, PB5 or PB6 using the routing
interface I/O switch registers.
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117
Electrical parameters
9.3.14
STM8AL318x STM8AL3L8x
12-bit ADC1 characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 56. ADC1 characteristics
Symbol
Parameter
VDDA
Analog supply voltage
VREF+
Reference supply
voltage
VREF-
Conditions
Min.
Typ.
Max.
Unit
-
1.8
-
3.6
V
2.4 V ≤VDDA≤ 3.6 V
2.4
-
VDDA
V
1.8 V≤VDDA≤ 2.4 V
VDDA
V
Lower reference voltage
-
VSSA
V
IVDDA
Current on the VDDA
input pin
-
-
-
-
IVREF+
Current on the VREF+
input pin
1000
400
-
-
1450
µA
700
(peak)(1)
µA
450
(average)(1)
µA
VAIN
Conversion voltage
range
-
0(2)
-
VREF+
TA
Temperature range
-
-40
-
125
°C
on PF0/1/2/3 fast
channels
-
-
50(3)
kΩ
on all other channels
-
-
on PF0/1/2/3 fast
channels
-
on all other channels
-
2.4 V≤VDDA≤3.6 V
without zooming
0.320
-
16
MHz
1.8 V≤VDDA≤2.4 V
with zooming
0.320
-
8
MHz
VAIN on PF0/1/2/3 fast
channels
-
-
1(3)(4)
MHz
VAIN on all other
channels
-
-
760(3)(4)
kHz
RAIN
CADC
fADC
fCONV
External resistance on
VAIN
Internal sample and hold
capacitor
ADC sampling clock
frequency
12-bit conversion rate
16
-
pF
-
fTRIG
External trigger
frequency
-
-
-
tconv
1/fADC
tLAT
External trigger latency
-
-
-
3.5
1/fSYSCLK
110/132
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Electrical parameters
Table 56. ADC1 characteristics (continued)
Symbol
tS
Parameter
Sampling time
tconv
12-bit conversion time
tWKUP
Conditions
Min.
Typ.
Max.
VAIN PF0/1/2/3 fast
channels
VDDA < 2.4 V
0.43(3)(4)
-
-
VAIN PF0/1/2/3 fast
channels
2.4 V ≤VDDA≤ 3.6 V
0.22(3)(4)
-
-
VAIN on slow channels
VDDA < 2.4 V
0.86(3)(4)
-
-
VAIN on slow channels
2.4 V ≤VDDA≤ 3.6 V
0.41(3)(4)
-
-
-
Unit
µs
12000000 / fADC + tS
16 MHz
1(3)
-
Wakeup time from OFF
state
-
-
-
3
tIDLE(5)
Time before a new
conversion
-
-
-
∞
s
tVREFINT
Internal reference
voltage startup time
-
-
-
refer to
Table 49
ms
-
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- must be tied to ground.
3. Minimum sampling and conversion time is reached for maximum RAIN= 0.5 kΩ..
4. Value obtained for continuous conversion on fast channel.
5. In the RM0031, tIDLE defines the time between 2 conversions, or between ADC ON and the first conversion. tIDLE is not
relevant for this device.
DocID027179 Rev 7
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117
Electrical parameters
STM8AL318x STM8AL3L8x
In the following three tables, data are guaranteed by characterization result, not tested in
production.
Table 57. ADC1 accuracy with VDDA = 3.3 V to 2.5 V
Symbol
Typ.
Max.(1)
1
1.6
Differential non linearity fADC = 8 MHz
1
1.6
fADC = 4 MHz
1
1.5
fADC = 16 MHz
1.2
2
fADC = 8 MHz
1.2
1.8
fADC = 4 MHz
1.2
1.7
fADC = 16 MHz
2.2
3.0
fADC = 8 MHz
1.8
2.5
fADC = 4 MHz
1.8
2.3
fADC = 16 MHz
1.5
2
fADC = 8 MHz
1
1.5
fADC = 4 MHz
0.7
1.2
1
1.5
Parameter
Conditions
fADC = 16 MHz
DNL
INL
Integral non linearity
TUE
Total unadjusted error
Offset
Offset error
fADC = 16 MHz
Gain
Gain error
fADC = 8 MHz
Unit
LSB
LSB
fADC = 4 MHz
1. Guaranteed by characterization results.
Table 58. ADC1 accuracy with VDDA = 2.4 V to 3.6 V
Symbol
Parameter
Typ.
Max.(1)
Unit
1
2
LSB
1.7
3
LSB
DNL
Differential non linearity
INL
Integral non linearity
TUE
Total unadjusted error
2
4
LSB
Offset
Offset error
1
2
LSB
Gain
Gain error
1.5
3
LSB
1. Guaranteed by characterization results.
Table 59. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V
Symbol
112/132
Parameter
Typ.
Max.(1)
Unit
DNL
Differential non linearity
1
2
LSB
INL
Integral non linearity
2
3
LSB
TUE
Total unadjusted error
3
5
LSB
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Electrical parameters
Table 59. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V (continued)
Symbol
Parameter
Typ.
Max.(1)
Unit
Offset
Offset error
2
3
LSB
Gain
Gain error
2
3
LSB
1. Guaranteed by characterization results.
Figure 42. ADC1 accuracy characteristics
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Figure 43. Typical connection diagram using the ADC
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1. Refer to Table 56 for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 44 or Figure 45,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
DocID027179 Rev 7
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117
Electrical parameters
STM8AL318x STM8AL3L8x
Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA)
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Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA)
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069
114/132
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
9.3.15
Electrical parameters
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
•
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms to the ANSI/ESDA/JEDEC JS001, JESD22-A115 and ANSI/ESD S5.3.1.
•
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) are
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress is applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software is hardened to
prevent unrecoverable errors occurring (see application note AN1015).
Table 60. EMS data
Symbol
Parameter
Conditions
VFESD
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on
any I/O pin to induce a functional fCPU= 16 MHz,
disturbance
conforms to IEC 61000
VEFTB
Fast transient voltage burst limits
VDD = 3.3 V, TA = +25 °C,
to be applied through 100 pF on
Using HSI
fCPU = 16 MHz,
VDD and VSS pins to induce a
conforms to IEC 61000
Using HSE
functional disturbance
DocID027179 Rev 7
Level/
Class
2B
4A
2B
115/132
117
Electrical parameters
STM8AL318x STM8AL3L8x
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
Table 61. EMI data (1)
Symbol
SEMI
Parameter
Peak level
Conditions
VDD = 3.6 V,
TA = +25 °C,
LQFP80
conforming to
IEC61967-2
Max vs.
Monitored
frequency band
Unit
16 MHz
0.1 MHz to 30 MHz
10
30 MHz to 130 MHz
4
130 MHz to 1 GHz
1
EMI Level
dBμV
1.5
-
1. Guaranteed by characterization results.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
are simulated: human body model and charge device model. This test conforms to the
ANSI/ESDA/JEDEC JS-001, JESD22-A115 and ANSI/ESD S5.3.1.
Table 62. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = 25 °C, conforming
to ANSI/ESDA/
JEDEC JS-001
2
2000
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming
to ANSI/ESD S5.3.1
C4B
500
VESD(MM)
Electrostatic discharge voltage
(machine model)
TA = 25 °C, conforming
to JESD22-A115
M2
200
1. Guaranteed by characterization results.
116/132
Maximum
Unit
value (1)
DocID027179 Rev 7
V
STM8AL318x STM8AL3L8x
Electrical parameters
Static latch-up
•
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
Table 63. Electrical sensitivities
Symbol
LU
Parameter
Class (1)
Conditions
TA = 125 °C
Static latch-up class
A
1. Class description: the class is an STMicroelectronics internal specification. The class limits are higher than
the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
9.4
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 19: General operating conditions on page 68.
The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
•
TAmax is the maximum ambient temperature in ° C
•
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
•
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
•
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
•
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*I OH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high-level in
the application.
Table 64. Thermal characteristics(1)
Symbol
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm
65
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 64- 10 x 10 mm
48
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 80- 14 x 14 mm
38
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
DocID027179 Rev 7
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117
Package information
10
STM8AL318x STM8AL3L8x
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10.1
LQFP80 package information
Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline
C
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1. Drawing is not to scale.
118/132
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Package information
Table 65. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
mechanical data(1)
millimeters
inches
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.220
0.320
0.380
0.0087
0.0126
0.0150
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.350
-
-
0.4862
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.350
-
-
0.4862
-
e
-
0.650
-
-
0.0256
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID027179 Rev 7
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129
Package information
STM8AL318x STM8AL3L8x
Figure 47. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
recommended footprint
4@'1
1. Dimensions are expressed in millimeters.
Device marking for LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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STM8AL318x STM8AL3L8x
Package information
Figure 48. LQFP80 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DocID027179 Rev 7
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129
Package information
10.2
STM8AL318x STM8AL3L8x
LQFP64 package information
Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
PP
*$8*(3/$1(
F
$
$
$
6($7,1*3/$1(
&
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'
'
'
.
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1. Drawing is not to scale.
Table 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
inches(1)
millimeters
Symbol
122/132
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Package information
Table 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
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129
Package information
STM8AL318x STM8AL3L8x
Device marking for LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 51. LQFP64 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
124/132
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
LQFP48 package information
Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
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10.3
Package information
E
"?-%?6
1. Drawing is not to scale.
DocID027179 Rev 7
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129
Package information
STM8AL318x STM8AL3L8x
Table 67. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM8AL318x STM8AL3L8x
Package information
Figure 53. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint
AID
1. Dimensions are expressed in millimeters.
DocID027179 Rev 7
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129
Package information
STM8AL318x STM8AL3L8x
Device marking for LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 54. LQFP48 marking example (package top view)
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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
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STM8AL318x STM8AL3L8x
11
Ordering information
Ordering information
Table 68. Ordering information scheme
Example:
STM8 AL
31
8
A
T C
Y
Device family
STM8 microcontroller
Product type
AL = automotive low-power(1)
Device subfamily
31: standard devices
3L: devices with LCD
Program memory size
8 = 64 Kbytes of Flash memory
Pin count
A = 80 pins
9 = 64 pins
8 = 48 pins
Package
T = LQFP
Temperature range
C = -40 to 125 °C
A = -40 to 85 °C
Packing
Y = tray
X = Tape and reel compliant with EIA 481-C
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 and Q002 or equivalent.
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the
nearest ST sales office.
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Revision history
12
STM8AL318x STM8AL3L8x
Revision history
Table 69. Document revision history
Date
Revision
03-Feb-2015
1
Initial release.
2
Added:
– Figure 50: LQFP64 - 64-pin, 10 x 10 mm low-profile
quad flat package recommended footprint,
– Figure 48: LQFP80 marking example (package top
view),
– Figure 51: LQFP64 marking example (package top
view),
– Figure 54: LQFP48 marking example (package top
view).
Corrected OPT0 default value in Table 12: Option byte
addresses.
27-Jul-2015
3
Updated
– the document confidentiality level to “Public”,
– Table 1: Device summary, replacing STM8AL318AT
with STM8AL318A.
19-Aug-2015
4
Datasheet status changed to “production data”.
5
– Updated Table 5: High-density STM8AL3x8x pin
description: two pin names changed from
PI0/RTC_TAMP1/[SPI2_NSS]/[TIM3_CH3 to
PI0/RTC_TAMP1/[SPI2_NSS]/[TIM3_CH1
and from
PF2/ADC1_IN26/[SPI2_SCK]/[USART3_SCK] to
PF2/ADC1_IN26/[SPI1_SCK]/[USART3_SCK]
– Updated device marking part of Section 10.1: LQFP80
package information, Section 10.2: LQFP64 package
information and Section 10.3: LQFP48 package
information
– Updated Section 9.2: Absolute maximum ratings
– Updated table footnotes in Chapter 9: Electrical
parameters
– Updated Figure 12: Power supply thresholds
22-Apr-2015
1-Dec-2016
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Changes
DocID027179 Rev 7
STM8AL318x STM8AL3L8x
Revision history
Table 69. Document revision history (continued)
Date
5-Dec-2016
25-Jul-2017
Revision
Changes
6
– Updated Table 5: High-density STM8AL3x8x pin
description: pin name changed from
PC3/USART1_TX/LCD_SEG23(3)/ADC1_IN5/COMP
_IN3M/COMP2_INM/COMP1_INP to
PC3/USART1_TX/LCD_SEG23(3)/ADC1_IN5/COMP
2_INM/COMP1_INP.
7
– Updated introductory text on Section : LSE external
clock (LSEBYP=1 in CLK_ECKCR) and Section : LSE
crystal/ceramic resonator oscillator
– Updated section naming and footnotes on Section :
Device marking for LQFP80 - 80-pin, 14 x 14 mm lowprofile quad flat package, Section : Device marking for
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package and Section : Device marking for LQFP48 48-pin, 7 x 7 mm low-profile quad flat package.
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STM8AL318x STM8AL3L8x
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