STM8AL31E8x STM8AL3LE8x
Automotive 8-bit ultra-low-power MCU, 64 KB Flash, EEPROM,
RTC, AES, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, COMPs
Datasheet - production data
Features
• AEC-Q100 grade 1 qualified
• Operating conditions
– Operating power supply range 1.8 V to
3.6 V (down to 1.65 V at power down)
– Temp. range: -40 to 85 or 125 °C
• Low-power features
– 5 low-power modes: Wait, Low-power run
(5.9 µA), Low-power wait (3 µA), Activehalt with full RTC (1.4 µA), Halt (400 nA)
– Consumption: 200 µA/MHz+330 µA
– Fast wake up from Halt mode (4.7 µs)
– Ultra-low leakage per I/0: 50 nA
• Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
• Reset and supply management
– Low power, ultra safe BOR reset with 5
programmable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock management
– 32 kHz and 1-16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC and
38 kHz low consumption RC
– Clock security system
• Low-power RTC
– BCD calendar with alarm interrupt,
– Digital calibration with +/- 0.5ppm accuracy
– Advanced anti-tamper detection
• DMA
– 4 ch. for ADC, encryption hardware
accelerator (AES), DACs, SPIs, I2C,
USARTs, Timers, 1 ch. for memory-tomemory
• LCD: 8x40 or 4x44 w/ step-up converter
December 2016
This is information on a product in full production.
LQFP80
14x14 mm
LQFP64
10x10 mm
LQFP48
7x7 mm
• 12-bit ADC up to 1 Msps /
28 channels,
– Temp. sensor and internal ref.
voltage
• Memories
– Up to 64 Kbytes of Flash with up to
2 Kbytes of data EEPROM with ECC and
RWW
– Flexible write/read protection modes
– Up to 4 Kbytes of RAM
• 2x12-bit DAC (dual mode) with output buffer
• 2 ultra-low-power comparators
– 1 with fixed threshold and 1 rail to rail
– Wakeup capability
• Timers
– Three 16-bit timers with 2 channels (IC,
OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– One window and one independent
watchdog
– Beeper timer with 1, 2 or 4 kHz frequencies
• Communication interfaces
– Two synchronous serial interface (SPI)
– Fast I2C 400 kHz SMBus and PMBus
– Three USARTs (IrDA, LIN 1.3, LIN2.0)
• Up to 67 I/Os, all mappable on interrupt vectors
• Fast on-chip programming and non-intrusive
debugging with SWIM, Bootloader using
USART
• 96-bit unique ID
DocID027180 Rev 5
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STM8AL31E8x STM8AL3LE8x
Table 1. Device summary
2/133
Reference
Part number
STM8AL31E8x
STM8AL31E88, STM8AL31E89, STM8AL31E8A
STM8AL3LE8x
STM8AL3LE88, STM8AL3LE89, STM8AL3LE8A
DocID027180 Rev 5
STM8AL31E8x STM8AL3LE8x
Contents
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
2.1
STM8AL ultra-low-power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . .11
2.2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
3.2.1
Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Low-power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10
Digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11
Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12
System configuration controller and routing interface . . . . . . . . . . . . . . . 22
3.13
AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15
3.14.1
16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.2
16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . . 23
3.14.3
8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.1
Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.2
Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Contents
STM8AL31E8x STM8AL3LE8x
3.16
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.1
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.2
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.3
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18
Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.19
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8
Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1
4/133
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.3.2
Embedded reset and power control block characteristics
9.3.3
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.3.4
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.6
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.7
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.8
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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9.4
10
Contents
9.3.9
LCD controller (STM8AL3LE8x only) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.3.10
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.11
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.12
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.13
12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.14
12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.3.15
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.1
LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.2
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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List of tables
STM8AL31E8x STM8AL3LE8x
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
6/133
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
High-density STM8AL3xE8x low-power device features and peripheral counts. . . . . . . . . 13
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
High-density STM8AL3xE8x pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operating lifetime (OLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 70
Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Total current consumption and timing in low-power run mode at VDD = 1.65 V
to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Total current consumption in low-power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . 78
Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal . . 80
Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 82
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 96
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DocID027180 Rev 5
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Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
List of tables
I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 114
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
STM8AL31E8x STM8AL3LE8x ordering information scheme . . . . . . . . . . . . . . . . . . . . . 131
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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7
List of figures
STM8AL31E8x STM8AL3LE8x
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
8/133
High-density STM8AL3xE8x device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STM8AL31E8A 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8AL3LE8A 80-pin package pinout (with LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8AL31E89 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM8AL3LE89 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STM8AL31E88 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM8AL3LE88 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz(1) . . . . . . . . . . . . . 73
Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . 74
Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . . 76
Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . . . . . . . . 76
Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 77
Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF(1) . . . . . . . . . . . . . . . . . . 78
Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 82
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Typical application with I2C bus and timing diagram(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 116
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 116
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 120
LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DocID027180 Rev 5
STM8AL31E8x STM8AL3LE8x
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
List of figures
LQFP80 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 124
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 127
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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9
Introduction
1
STM8AL31E8x STM8AL3LE8x
Introduction
This document describes the features, pinout, mechanical data and ordering information of
the high-density STM8AL31E8x and STM8AL3LE8x devices (microcontrollers with 64 Kbyte
Flash memory density). These devices are referred to as high-density devices in
STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L MCU
lines reference manual (RM0031) and in the STM8L and STM8AL Flash programming
manual (PM0054).
For more details on the whole STMicroelectronics ultra-low-power family please refer to
Section 3: Functional overview on page 14.
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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STM8AL31E8x STM8AL3LE8x
2
Description
Description
The high-density STM8AL3xE8x ultra-low-power devices feature an enhanced STM8 CPU
core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low-power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming.
All high-density STM8AL3xE8x microcontrollers feature embedded data EEPROM and lowpower low-voltage single-supply program Flash memory.
The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit
ADC, two DACs, two comparators, a real-time clock, AES, 8x40 or 4x44-segment LCD, four
16-bit timers, one 8-bit timer, as well as standard communication interfaces such as two
SPIs, an I2C interface, and three USARTs. One 8x40 or 4x44-segment LCD is available on
the STM8AL3LE8x devices. The modular design of the peripheral set allows the same
peripherals to be found in different ST microcontroller families including 32-bit families. This
makes any transition to a different family very easy, and simplified even more by the use of
a common set of development tools.
2.1
STM8AL ultra-low-power 8-bit family benefits
High-density STM8AL3xE8x devices are part of the STM8AL automotive ultra-low-power 8bit family providing the following benefits:
•
•
•
•
Integrated system
–
64 Kbytes of high-density embedded Flash program memory
–
2 Kbytes of data EEPROM
–
4 Kbytes of RAM
–
Internal high-speed and low-power low speed RC.
–
Embedded reset
Ultra-low-power consumption
–
1 µA in Active-halt mode
–
Clock gated system and optimized power management
–
Capability to execute from RAM for Low-power wait mode and Low-power run
mode
Advanced features
–
Up to 16 MIPS at 16 MHz CPU clock frequency
–
Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
Short development cycles
–
Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
–
Wide choice of development tools
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61
Description
STM8AL31E8x STM8AL3LE8x
STM8AL ultra-low-power microcontrollers operates either from 1.8 to 3.6 V (down to 1.65 V
at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to
+125 °C temperature ranges.
These features make the STM8AL ultra-low-power microcontroller families suitable for a
wide range of applications.
The devices are offered in one 48-pin package. Different sets of peripherals are included
depending on the device. Refer to Section 3 for an overview of the complete range of
peripherals proposed in this family.
All STM8AL ultra-low-power products are based on the same architecture with the same
memory mapping and a coherent pinout.
Figure 1 shows the block diagram of the high-density STM8AL3xE8x families.
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2.2
Description
Device overview
Table 2. High-density STM8AL3xE8x low-power device features and peripheral counts
Features
STM8AL3xx8
STM8AL3xx9
Flash (Kbyte)
64
Data EEPROM (Kbyte)
2
AES
1
LCD
Timers
Communication
interfaces
STM8AL3xxA
8x28 or
4x32(1)
8x36 or 4x40(1)
8x40 or 4x44(1)
Basic
1
(8-bit)
1
(8-bit)
1
(8-bit)
General purpose
3
(16-bit)
3
(16-bit)
3
(16-bit)
Advanced control
1
(16-bit)
1
(16-bit)
1
(16-bit)
SPI
2
2
2
I2C
1
1
1
USART
3
3
3
GPIOs
41
(2)
54(2)
68(2)
12-bit synchronized ADC
(number of channels)
1
(25)
1
(28)
1
(28)
Number of channels
2
2
2
2
2
2
Comparators (COMP1/COMP2)
2
2
2
12-Bit DAC
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external
oscillator
CPU frequency
Operating voltage
16 MHz
1.8 to 3.6 V (down to 1.65 V at power-down) with BOR
-40 to +85 °C / -40 to +125 °C
Operating temperature
Packages
LQFP48
LQFP64
LQFP80
1. STM8AL3LE8x versions only.
2. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as
general purpose output only (PA1).
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61
Functional overview
3
STM8AL31E8x STM8AL3LE8x
Functional overview
Figure 1. High-density STM8AL3xE8x device block diagram
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1. Legend: AF: alternate function
ADC: Analog-to-digital converter
AES: Advanced encryption standard hardware accelerator
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STM8AL31E8x STM8AL3LE8x
Functional overview
BOR: Brownout reset
DMA: Direct memory access
DAC: Digital-to-analog converter
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
LCD: Liquid crystal display
POR/PDR: Power on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
3.1
Low-power modes
The high-density STM8AL3xE8x devices support five low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
•
Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal
or external interrupt or a Reset is used to exit the microcontroller from Wait mode (WFE
or WFI mode).
•
Low-power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low-power run mode by software and exits from this mode
by software or by a reset.
All interrupts must be masked and are not used to exit the microcontroller from this
mode.
•
Low-power wait mode: This mode is entered when executing a Wait for event in Lowpower run mode. It is similar to Low-power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low-power run mode.
All interrupts must be masked and arenot used to exit the microcontroller from this
mode.
•
Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
is triggered by RTC interrupts, external interrupts or reset.
•
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
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61
Functional overview
STM8AL31E8x STM8AL3LE8x
3.2
Central processing unit STM8
3.2.1
Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
•
Harvard architecture
•
3-stage pipeline
•
32-bit wide program memory bus - single cycle fetching most instructions
•
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
•
8-bit accumulator
•
24-bit program counter - 16 Mbyte linear memory space
•
16-bit stack pointer - access to a 64 Kbyte level stack
•
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•
20 addressing modes
•
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
•
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
3.2.2
•
80 instructions with 2-byte average instruction size
•
Standard data movement and logic/arithmetic functions
•
8-bit by 8-bit multiplication
•
16-bit by 8-bit and 16-bit by 16-bit division
•
Bit manipulation
•
Data transfer between stack and accumulator (push/pop) with direct stack access
•
Data transfer using the X and Y registers or direct memory-to-memory transfers
Interrupt controller
The high-density STM8AL3xE8x devices feature a nested vectored interrupt controller:
16/133
•
Nested interrupts with 3 software priority levels
•
32 interrupt vectors with hardware priority
•
Up to 40 external interrupt sources on 11 vectors
•
Trap and reset interrupts
DocID027180 Rev 5
STM8AL31E8x STM8AL3LE8x
Functional overview
3.3
Reset and supply management
3.3.1
Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
3.3.2
•
VSS1, VDD1, VSS2, VDD2, VSS3, VDD3, VSS4, VDD4= 1.65 to 3.6 V: external power supply
for I/Os and for the internal regulator. Provided externally through VDD pins, the
corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3/VDD4
must not be left unconnected.
•
VSSA, VDDA = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must
be connected to VDD and VSS, respectively.
•
VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
•
VREF+ (for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
externally through VREF+.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. As soon as the 1.8 V BOR threshold is
reached, the option byte loading process starts, either to confirm or modify the default
thresholds, or to disable BOR permanently. In this latter case, the VDD min value at power
down is 1.65 V.
Five BOR thresholds are available through option byte, starting from 1.8 V to 3 V. To reduce
the power consumption in Halt mode, it is possible to automatically switch off the internal
reference voltage (and consequently the BOR) in Halt mode. The device remains in reset
state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt is generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine generates then a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
DocID027180 Rev 5
17/133
61
Functional overview
3.3.3
STM8AL31E8x STM8AL3LE8x
Voltage regulator
The high-density STM8AL3xE8x devices embed an internal voltage regulator for generating
the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
•
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
•
Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and
Low-power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness.
Features
18/133
•
Clock prescaler: to get the best compromise between speed and current
consumption, the clock frequency to the CPU and peripherals has to be adjusted by a
programmable prescaler
•
Safe clock switching: Clock sources are adaptable safely on the fly in run mode
through a configuration register.
•
Clock management: To reduce power consumption, the clock controller stops the
clock to the core, individual peripherals or memory.
•
System clock sources: 4 different clock sources are available to drive the system
clock:
–
1-16 MHz High speed external crystal (HSE)
–
16 MHz High speed internal RC oscillator (HSI)
–
32.768 Low speed external crystal (LSE)
–
38 kHz Low speed internal RC (LSI)
•
RTC and LCD clock sources: the above four sources are available to clock the RTC
and the LCD, whatever the system clock.
•
Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source is adjustable by the
application program as soon as the code execution starts.
•
Clock security system (CSS): This feature is enabled by software. If a HSE clock
failure occurs, the system clock is automatically switched to HSI.
•
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
DocID027180 Rev 5
STM8AL31E8x STM8AL3LE8x
Functional overview
Figure 2. Clock tree diagram
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