STM8AL3LE88TCX

STM8AL3xxx STM8Lxxxx6/8 Errata sheet STM8AL318x, STM8AL3L8x, STM8AL3xE8x, STM8L052R8, STM8L15xx6/8 and STM8L162x8 device limitations Applicability This errata sheet applies to the revision Z of STMicroelectronics STM8L052R8, STM8L15xM8/R8/C8/R6, STM8L162x8, STM8AL318x, STM8AL3L8x and STM8AL3xE8x devices. The products are identifiable as shown in Table 1: • by the revision code marked below the product identification area on the package • by the last three digits of the Internal order code printed on the box label Table 1. Device identification(1) . Part number Revision code marked on device STM8L052R8 “Z” STM8L151M8, STM8L152M8, STM8L151R8, STM8L152R8, STM8L151C8, STM8L152C8, STM8L151R6, STM8L152R6, STM8L162M8, STM8L162R8 “Z” STM8AL318x, STM8AL3L8x, STM8AL3xE8x “Z” 1. Refer to STM8AL3xxxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 product datasheets for details on the device marking. Table 2. Device summary Reference July 2021 Part number STM8L052R8 STM8L052R8 STM8L15xM8 STM8L151M8, STM8L152M8 STM8L15xR8 STM8L151R8, STM8L152R8 STM8L15xC8 STM8L151C8, STM8L152C8 STM8L15xR6 STM8L151R6, STM8L152R6 STM8L162x8 STM8L162M8, STM8L162R8 STM8AL318x STM8AL3188, STM8AL3189, STM8AL318A STM8AL3L8x STM8AL3L88, STM8AL3L89, STM8AL3L8A STM8AL3xE8x STM8AL31E88, STM8AL31E89, STM8AL31E8A, STM8AL3LE88, STM8AL3LE89, STM8AL3LE8A ES0131 Rev 8 1/20 www.st.com 1 Contents STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Contents 1 Silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 1.3 2 2/20 Core limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 Interrupt service routine (ISR) executed with priority of main process . . 6 1.1.2 Main CPU execution is not resumed after an ISR resets the AL bit . . . . . 6 1.1.3 Unexpected DIV/DIVW instruction result in ISR . . . . . . . . . . . . . . . . . . . 6 1.1.4 Incorrect code execution when WFE execution is interrupted by ISR or event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 Core kept in stall mode when DMA transfer occurs during program/ erase operation to EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.6 Incorrect code execution when FLASH/EEPROM memory wakes up from power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1.7 Stack roll-over limit not implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.1 Default DAC output level when output buffer is enabled . . . . . . . . . . . . 12 1.2.2 32.768 kHz LSE crystal accuracy may be disturbed by the use of adjacent I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2.3 RTC LSE failure can be detected just once after power-on reset . . . . . 12 Peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3.1 SPI2 peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3.2 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3.3 USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3.4 Timer limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.5 LCD / GPIO limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Possible combinations when PF_IDRx bit value is forced to “0”. . . . . . . . . . . . . . . . . . . . . 18 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ES0131 Rev 8 3/20 3 Silicon limitations 1 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations Table 3 gives a summary of the fix status. Legend for Table 3: A = workaround available; N = no workaround available; P = partial workaround available; N/A: not applicable; ‘-’ and grayed = fixed. Table 3. Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon limitations Section Limitation Section 1.1.1: Interrupt service routine (ISR) executed with priority of main process N N Section 1.1.2: Main CPU execution is not resumed after an ISR resets the AL bit A A Section 1.1.3: Unexpected DIV/DIVW instruction result in ISR A A A A A A Section 1.1.6: Incorrect code execution when FLASH/EEPROM memory wakes up from power down mode A A Section 1.1.7: Stack roll-over limit not implemented N N Section 1.2.1: Default DAC output level when output buffer is enabled N N/A Section 1.2.2: 32.768 kHz LSE crystal accuracy may be disturbed by the use of adjacent I/Os N N Section 1.2.3: RTC LSE failure can be detected just once after power-on reset N N Section 1.1.4: Incorrect code execution when WFE Section 1.1: Core execution is interrupted by ISR or event limitations Section 1.1.5: Core kept in stall mode when DMA transfer occurs during program/ erase operation to EEPROM Section 1.2: System limitations 4/20 STM8L15xM8/R8/C8/R6 STM8L162x8, STM8AL318x, STM8L052R8 STM8AL3L8x, rev. Z STM8AL3xE8x rev. Z ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations Table 3. Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon limitations (continued) Section STM8L15xM8/R8/C8/R6 STM8L162x8, STM8AL318x, STM8L052R8 STM8AL3L8x, rev. Z STM8AL3xE8x rev. Z Limitation Section 1.3.1: SPI2 peripheral limitations SPI2_MOSI cannot be configured as pseudo open-drain on 48-pin packages N N I2C event management A A A A Wrong behavior of the I2C peripheral in Master mode after misplaced STOP A A Violation of I2C “setup time for repeated START condition” parameter A A In I2C slave “NOSTRETCH” mode, underrun errors may not be detected and may generate bus errors A A SMBus standard not fully supported in I2C peripherals A A USART IDLE frame detection not supported in the case of a clock deviation N N PE flag can be cleared in USART Duplex mode by writing to the data register A A PE flag is not set in USART Mute mode using address mark detection N N IDLE flag is not set using address mark detection in the USART peripheral N N N N N N Corrupted last received data in I Master Receiver mode Section 1.3.2: I2C peripheral limitations Section 1.3: Peripheral limitations Section 1.3.3: USART peripheral limitations 2C Section 1.3.4: TIM1 advanced timer: Bad Timer limitations regulation for 100% PWM Section 1.3.5: LCD / GPIO limitations PF_IDRx bit value forced to “0” on PortF GPIOs depending on DUTY8 bit value, LCD_PM5 register content and package ES0131 Rev 8 5/20 19 Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8 1.1 Core limitations 1.1.1 Interrupt service routine (ISR) executed with priority of main process Description If an interrupt is cleared or masked when the context saving has already started, the corresponding ISR is executed with the priority of the main process. Workaround None. No fix is planned for this limitation. 1.1.2 Main CPU execution is not resumed after an ISR resets the AL bit Description If the CPU is in wait for interrupt state and the AL bit is set, the CPU returns to wait for interrupt state after executing an ISR. To continue executing the main program, the AL bit must be reset by the ISR. When AL is reset just before exiting the ISR, the CPU may remain stalled. Workaround Reset the AL bit at least two instructions before the IRET instruction. No fix is planned for this limitation. 1.1.3 Unexpected DIV/DIVW instruction result in ISR Description In very specific conditions, a DIV/DIVW instruction may return a false result when executed inside an interrupt service routine (ISR). This error occurs when the DIV/DIVW instruction is interrupted and a second interrupt is generated during the execution of the IRET instruction of the first ISR. Under these conditions, the DIV/DIVW instruction executed inside the second ISR, including function calls, may return an unexpected result. The applications that do not use the DIV/DIVW instruction within ISRs are not impacted. Workaround 1 If an ISR or a function called by this routine contains a division operation, the following assembly code should be added inside the ISR before the DIV/DIVW instruction: push cc pop a and a,#$BF push a pop cc This sequence should be placed by C compilers at the beginning of the ISR using DIV/DIVW. Refer to your compiler documentation for details on the implementation and control of automatic or manual code insertion. 6/20 ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations Workaround 2 To optimize the number of cycles added by workaround 1, you can use this workaround instead. Workaround 2 can be used in applications with fixed interrupt priorities, identified at the program compilation phase: push #value pop cc where bits 5 and 3 of #value have to be configured according to interrupt priority given by I1 and I0, and bit 6 kept cleared. In this case, compiler workaround 1 has to be disabled by using compiler directives. No fix is planned for this limitation. 1.1.4 Incorrect code execution when WFE execution is interrupted by ISR or event Description Two types of failures can occur: Case 1: In case WFE instruction is placed in the two MSB of the 32-bit word within the memory, an event which occurs during the WFE execution cycle or re-execution cycle (when returning from ISR handler) will cause an incorrect code execution. Case 2: An interrupt request, which occurs during the WFE execution cycle will lead to incorrect code execution. This is also valid for the WFE re-execution cycle, while returning from an ISR handler. The above failures have no impact on the core behavior when the ISR request or events occur in Wait for Event mode itself, out of the critical single cycle of WFE instruction execution. Workaround General solution is to ensure no interrupt request or event occurs during WFE instruction execution or re-execution cycle by proper application timing. Dedicated workarounds: Case 1: Replace the WFE instruction with WFE JRA next next: ES0131 Rev 8 7/20 19 Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Case 2: It is recommended to avoid any interrupts before WFE mode is entered. This can be done by disabling all interrupts before the device enters Wait for event mode. SIM WFE RIM This workaround also prevents WFE re-execution in case 1. No fix is planned for this limitation. 1.1.5 Core kept in stall mode when DMA transfer occurs during program/ erase operation to EEPROM Description When the MCU performs EEPROM program/erase operation, the core is stalled during data transfer to the memory controller, which occurs at the beginning of the program/erase operation. If a DMA request servicing starts while the core is stalled, the core does not return from stall mode to program execution. The core is stalled for 11 cycles during byte program/erase, 8 cycles during word program/erase and 3 cycles during each word transfer in block programming mode. For block erase, the core is stalled for 127 cycles. When a DMA request arises, it is only served if the DMA priority is higher than the core access priority. If the current DMA priority is lower than the core one, the DMA service is delayed until the core access becomes idle. The DMA also includes a programmable timeout function, configurable by DMA_GCSR register. If the core does not release the bus during this timeout, the DMA automatically increases its own priority and forces the core to release the bus for DMA service. No fix is planned for this limitation. Several workarounds are available for this limitation. Workaround 1 Disable all DMA requests during data transfer to the EEPROM. This workaround is applicable for all program/erase operations. Workaround 2 Configure DMA programmable timeout in the DMA_GCSR register to exceed the number of stall cycles required during the transfer. DMA priority must never be configured to a very high level. This workaround is applicable for all program/erase operations except block erase. In order to apply this workaround to block erase, use block programming to 0x00 instead of block erase. This takes ~6 ms instead of ~3 ms. 8/20 ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations Workaround 3 This workaround can be used if block erase cannot be replaced by block programming. In this workaround, DMA is used to transfer data to the EEPROM instead of the core. All other DMA transfers are delayed once the core is stalled due to data transfer to memory controller. /* start of the workaround in user code, using FW Library */ #ifdef USE_EVENT_MODE DMA1_Channel3->CCR= DMA_CCR_MEM | DMA_CCR_IDM | DMA_CCR_TCIE; /* Config DMA Chn3 Mem, incr, disable, interrupt) */ #else DMA1_Channel3->CCR= DMA_CCR_MEM | DMA_CCR_IDM; /* Config DMA Chn3 (Mem, incr,disable) */ #endif DMA1_Channel3->CM0ARH= (uint8_t)0; /* Source address */ DMA1_Channel3->CM0ARL= (uint8_t)0; DMA1_Channel3->CPARH= (uint8_t)(addr_begin >> 8); /* Destination address */ DMA1_Channel3->CPARL= (uint8_t)(addr_begin); DMA1_Channel3->CNBTR= 2; /* Number of data to be transferred */ DMA1_Channel3->CSPR= 8; /* Low priority, 16 bit mode */ DMA1_Channel3->CSPR &= ~DMA_CSPR_TCIF;/* Clear TCIF */ DMA1->GCSR|= 1; /* Global DMA enable */ #ifdef USE_EVENT_MODE WFE->CR3 = WFE_CR3_DMA1CH23_EV; /* Enable event generation on DMA */ #endif FLASH->DUKR = 0xAE; /* Unprotect data memory */ FLASH->DUKR = 0x56; while((FLASH->IAPSR & FLASH_IAPSR_DUL) == 0) {} /* Polling DUL */ FLASH_Block_Load(); /* end of the workaround in user code */ /* following routine has to be placed in the RAM */ void FLASH_Block_Load(){ __asm("sim\n"); /* Disable interrupts */ FLASH->CR2 |= FLASH_CR2_ERASE; /* Enable erase DMA1_Channel3->CCR|= DMA_CCR_CE; /* Enable DMA #ifdef USE_EVENT_MODE __asm("wfe"); /* Wait for end of DMA operation #else while((DMA1_Channel3->CSPR & DMA_CSPR_TCIF) == {} /* Polling for end of DMA operation */ #endif block mode */ MEM transfer */ */ 0) __asm("rim\n"); /* Enable interrupts */ } ES0131 Rev 8 9/20 19 Silicon limitations 1.1.6 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Incorrect code execution when FLASH/EEPROM memory wakes up from power down mode Description In case FLASH/EEPROM memory is put in power down mode (IDDQ), first read after wakeup could return an incorrect content when FCPU is above 8 MHz + 5%. FLASH/EEPROM memory is put in IDDQ mode by default during Halt mode and could be forced to IDDQ mode by software for wait mode and during RAM execution. As a consequence, following behavior may be seen on some devices: • After wakeup from Low power mode with FLASH memory in IDDQ mode, program execution gets lost due to incorrect read of vector table. • Code running from RAM read an incorrect value from FLASH/EEPROM memory, when forced in IDDQ mode. • Program execution gets corrupted when returning from RAM execution to FLASH memory execution in case FLASH memory is forced in IDDQ mode. Workaround Slow down FSYSCLK before entering Low power mode to ensure correct FLASH memory wakeup. This could be done using clock divider (CLK_CKDIVR) or by activation of fast wakeup feature by setting FHWU bit in CLK_ICKCR register. Original clock setting can be reconfigured back by software after wakeup. Code example, assuming no divider is used in application by default. CLK_CKDIVR = 0x01; _asm(“HALT”); CLK_CKDIVR = 0x00; The interrupt service routine executed after wakeup could either stay at slower clock speed, or reconfigure clock setting. Care has to be taken to restore previous clock divider at the end of interrupt routines when modifying clock divider. No fix planned for this limitation. 1.1.7 Stack roll-over limit not implemented The dedicated stack address space is normally restricted by hardware to a range between a specific roll-over address and the highest RAM address 0x0FFF. However, there is no such restriction implemented on the device. As a consequence, the stack overflow with stack pointer roll-over to 0x0FFF occurs when it reaches 0x0000, and the stack underflow at 0x0FFF rolls the stack pointer over to 0x0000. Note: 10/20 Note: Even with the stack dedicated space restriction duly implemented, the software must manage the program flow such as to prevent any stack underflow or overflow, as it would lead to the program flow corruption. This is not much different from the situation where the stack pointer space is not restricted and the software must manage the program flow such as to prevent the stack pointer collision with data. In both cases, the software management of the program flow is necessary. ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations Workaround None. No fix planned for this limitation. ES0131 Rev 8 11/20 19 Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8 1.2 System limitations 1.2.1 Default DAC output level when output buffer is enabled Description When the DAC is enabled in buffered mode configuration, the output is set to a voltage which corresponds to the code 0xFFF, whatever the data output register value. The output recovers the correct voltage as soon as a new data is written into the data holding register. Workaround None. The following software sequence must be executed at the highest speed to limit the duration of this transient behavior: DAC->CR1=01; //Enable DAC DAC->DHR8 = 0x0; //Update the data holding register with 0 (as an example), or with any other data. Note: The DAC in unbuffered mode is not affected by this limitation. 1.2.2 32.768 kHz LSE crystal accuracy may be disturbed by the use of adjacent I/Os Description The activity on the PC4 and PC7 I/Os (input or output) can lead to missing pulses on the low speed external oscillator (32.768 kHz external crystal). Workaround None. If a high LSE accuracy is required, PC4 and PC7 must be tied to VDD or VSS. No fix planned for this limitation. 1.2.3 RTC LSE failure can be detected just once after power-on reset Description When the CSS on LSE is enabled (CSSEN=1 in CSSLSE_CSR), the CSS on LSE Flag (CSSF) can be set only once after power-on reset. Consequently, in case of several LSE perturbations in the application, only the first one can be detected and set the CSSF flag. Workaround None. No fix planned for this limitation. 12/20 ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations 1.3 Peripheral limitations 1.3.1 SPI2 peripheral limitations SPI2_MOSI cannot be configured as pseudo open-drain on 48-pin packages Description On UFQFPN48 and LQFP48 packages, when the SPI2 peripheral is enabled and SPI2_MOSI/PD5 is configured as pseudo open-drain output in the GPIO Port D control register 1 (PD_CR1), PD5 remains in push-pull mode. SPI2_MOSI can be configured as pseudo open-drain output on LQFP80 and LQFP64 packages. Workaround None. However, as SPI2_MOSI is usually configured as push-pull output, this limitation should not have any impact. No fix planned for this limitation. 1.3.2 I2C peripheral limitations I2C event management Description As described in the I2C section of the STM8L05x/15x microcontroller family reference manual (RM0031), the application firmware has to manage several software events before the current byte is transferred. If the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8 and EV3 events are not managed before the current byte is transferred, problems may occur such as receiving an extra byte, reading the same data twice or missing data. Workarounds When the EV7, EV7_1, EV6_1, EV6_3, EV2, EV8, and EV3 events cannot be managed before the current byte transfer and before the acknowledge pulse when the ACK control bit changes, it is recommended to: 1. Use the I2C with DMA in general, except when the Master is receiving a single byte. 2. Use I2C interrupts in nested mode and boost their priorities to the highest one in the application to make them uninterruptible. No fix planned for this limitation. ES0131 Rev 8 13/20 19 Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Corrupted last received data in I2C Master Receiver mode Conditions In Master Receiver mode, when the communication is closed using method 2, the content of the last read data may be corrupted. The following two sequences are concerned by the limitation: • • Sequence 1: transfer sequence for master receiver when N = 2 a) BTF = 1 (Data N-1 in DR and Data N in shift register) b) Program STOP = 1 c) Read DR twice (Read Data N-1 and Data N) just after programming the STOP bit. Sequence 2: transfer sequence for master receiver when N > 2 a) BTF = 1 (Data N-2 in DR and Data N-1 in shift register) b) Program ACK = 0 c) Read Data N-2 in DR d) Program STOP bit to 1 e) Read Data N-1. Description The content of the shift register (data N) is corrupted (data N is shifted 1 bit to the left) if the user software is not able to read the data N-1 before the STOP condition is generated on the bus. In this case, reading data N returns a wrong value. Workaround 1 – Sequence 1 When sequence 1 is used to close communication using method 2, mask all active interrupts between STOP bit programming and Read data N-1. – Sequence 2 When sequence 2 is used to close communication using method 2, mask all active interrupts between Read data N-2, STOP bit programming and Read data N-1. Workaround 2 Manage I2C RxNE and TxE events with DMA or interrupts of the highest priority level, so that the condition BTF = 1 never occurs. Wrong behavior of the I2C peripheral in Master mode after misplaced STOP Description The I2C peripheral does not enter Master mode properly if a misplaced STOP is generated on the bus. This can happen in the following conditions: 14/20 • If a void message is received (START condition immediately followed by a STOP): the BERR (bus error) flag is not set, and the I2C peripheral is not able to send a START condition on the bus after writing to the START bit in the I2C_CR2 register. • In the other cases of a misplaced STOP, the BERR flag is set in the IC2_CR2 register. If the START bit is already set in I2C_CR2, the START condition is not correctly generated on the bus and can create bus errors. ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations Workaround In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits + acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it, but they are not supported by the I²C peripheral. In case of noisy environment in which unwanted bus errors can occur, it is recommended to implement a timeout to ensure that the SB (start bit) flag is set after the START control bit is set. In case the timeout has elapsed, the peripheral must be reset by setting the SWRST bit in the I2C_CR2 control register. The I2C peripheral should be reset in the same way if a BERR is detected while the START bit is set in I2C_CR2. No fix is planned for this limitation. Violation of I2C “setup time for repeated START condition” parameter Description In case of a repeated Start, the “setup time for repeated START condition” parameter (named tSU(STA) in the datasheet and Tsu:sta in the I2C specifications) may be slightly violated when the I2C operates in Master Standard mode at a frequency ranging from 88 to 100 kHz. tSU(STA) minimum value may be 4 µs instead of 4.7 µs. The issue occurs under the following conditions: 1. The I2C peripheral operates in Master Standard mode at a frequency ranging from 88 to 100 kHz (no issue in Fast mode) 2. and the SCL rise time meets one of the following conditions: – The slave does not stretch the clock and the SCL rise time is more than 300 ns (the issue cannot occur when the SCL rise time is less than 300 ns). – or the slave stretches the clock. Workaround Reduce the frequency down to 88 kHz or use the I2C Fast mode if it is supported by the slave. In I2C slave “NOSTRETCH” mode, underrun errors may not be detected and may generate bus errors Description The data valid time (tVD;DAT, tVD;ACK) described by the I2C specifications may be violated as well as the maximum current data hold time (tHD;DAT) under the conditions described below. In addition, if the data register is written too late and close to the SCL rising edge, an error may be generated on the bus: SDA toggles while SCL is high. These violations cannot be detected because the OVR flag is not set (no transmit buffer underrun is detected). This issue occurs under the following conditions: 1. The I2C peripheral operates In Slave transmit mode with clock stretching disabled (NOSTRETCH=1) 2. and the application is late to write the DR data register, but not late enough to set the OVR flag (the data register is written before the SCL rising edge). ES0131 Rev 8 15/20 19 Silicon limitations STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Workaround If the master device supports it, use the clock stretching mechanism by programming the bit NOSTRETCH=0 in the I2C_CR1 register. If the master device does not support it, ensure that the write operation to the data register is performed just after TXE or ADDR events. You can use an interrupt on the TXE or ADDR flag and boost its priority to the higher level or use DMA. Using the “NOSTRETCH” mode with a slow I2C bus speed can prevent the application from being late to write the DR register (second condition). Note: The first data to be transmitted must be written into the data register after the ADDR flag is cleared, and before the next SCL rising edge, so that the time window to write the first data into the data register is less than tLOW. If this is not possible, a possible workaround can be the following: 1. Clear the ADDR flag 2. Wait for the OVR flag to be set 3. Clear OVR and write the first data. The time window for writing the next data is then the time to transfer one byte. In that case, the master must discard the first received data. SMBus standard not fully supported in I2C peripherals Description The I2C peripheral is not fully compliant with the SMBus v2.0 standard since it does not support the capability to NACK an invalid byte/command. Workarounds A higher-level mechanism should be used to verify that a write operation is being performed correctly at the target device, such as: 1.3.3 • The use of the SMBA pin if supported by the host • The alert response address (ARA) protocol • The Host notify protocol. USART peripheral limitations USART IDLE frame detection not supported in the case of a clock deviation Description An idle frame cannot be detected if the receiver clock is deviated. If a valid idle frame of a minimum length (depending on the M and Stop bit numbers) is followed without any delay by a start bit, the IDLE flag is not set if the receiver clock is deviated from the RX line (only if the RX line switches before the receiver clock). Consequently, the IDLE flag is not set even if a valid idle frame occurred. Workaround None. No fix planned for this limitation. 16/20 ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 Silicon limitations PE flag can be cleared in USART Duplex mode by writing to the data register Description The PE flag can be cleared by a read to the USART_SR register followed by a read or a write to the USART_DR register. When working in duplex mode, the following event can occur: the PE flag set by the receiver at the end of a reception is cleared by the software transmitter reading the USART_SR (to check TXE or TC flags) and writing a new data into the USART_DR. The software receiver can also read a PE flag at ‘0’ if a parity error occurred. Workaround The PE flag should be checked before writing to the USART_DR. PE flag is not set in USART Mute mode using address mark detection Description If, when using address mark detection, the receiver recognizes in Mute mode a valid address frame but the parity check fails, it exits from the Mute mode without setting the PE flag. Workaround None. IDLE flag is not set using address mark detection in the USART peripheral Description The IDLE flag is not set when the address mark detection is enabled, even when the USART is in Run mode (not only in Mute mode). Workaround None. 1.3.4 Timer limitations TIM1 advanced timer: Bad regulation for 100% PWM Description When the OCREFCLR functionality is activated, the OCxREF signal becomes deasserted (and consequently OCx is deasserted / OCxN is asserted) when a high level is applied on the OCREF_CLR signal. Then, the PWM restarts (output re-enabled) at the next counter overflow. But if the PWM is configured at 100% (CCxR->ARR), then it does not restart and OCxREF remains de-asserted. Consequently, current feedbacks cannot be generated without programming a minimum offtime (there cannot be a 100% PWM for this usage). Workaround None. No fix planned for this limitation. ES0131 Rev 8 17/20 19 Silicon limitations 1.3.5 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 LCD / GPIO limitations PF_IDRx bit value forced to “0” on PortF GPIOs depending on DUTY8 bit value, LCD_PM5 register content and package Description On 80-pin packages, when DUTY8 bit of LCD_CR4 register is set to “0” and when corresponding bit in LCD_PM5 register is set to “1”, SEG40, SEG41, SEG42 and SEG43 are mapped respectively on ports PF4, PF5, PF6 and PF7. In that case, when a LCD segment is mapped on a IO port, the associated PF_IDR bit is forced to “0” by the AF mechanism. Due to internal constraints, in this conditions, the AF mechanism is paired two by two in the following way at the PortF GPIOs: • PF4 is paired with PF7 • PF5 is paired with PF6 As a result, if LCD_PM5 register is set for example to 0x8 (SEG43 mapped on PF7), both PF_IDR7 and PF_IDR4 bit values are forced to “0”. In this case, the AF-paired PF4 bit cannot be used as GPIO even if it is not used to drive the LCD. Table 4 shows all the possible combinations when the PF_IDRx bit value is forced to “0”. Table 4. Possible combinations when PF_IDRx bit value is forced to “0” LCD_PM5 register Bit name Bit value Bit name Bit value SEG40 bit SEG43 bit PF_IDR4 PF_IDR7 0 0 PF4 dig. level PF7 dig. level X 1 1 X “0” “0” SEG41 bit SEG42 bit PF_IDR5 PF_IDR6 0 0 PF5 dig. level PF6 dig. level X 1 1 X “0” “0” Workaround None. 18/20 PF_IDRx bit ES0131 Rev 8 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 2 Revision history Revision history Table 5. Document revision history Date Revision 09-Sep-2010 1 Initial release. 18-Jan-2011 2 Updated for rev Z devices. 3 Added Section 1.1.4: Incorrect code execution when WFE execution is interrupted by ISR or event and Section 1.1.5: Core kept in stall mode when DMA transfer occurs during program/ erase operation to EEPROM. Updated format of Table 3: Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon limitations. 18-Feb-2013 4 Added STM8L052R8 part number. Updated Section 1.1.4: Incorrect code execution when WFE execution is interrupted by ISR or event. Updated cover page. 20-Jun-2013 5 Added Section 1.1.6: Incorrect code execution when FLASH/EEPROM memory wakes up from power down mode. 11-Sep-2015 6 Removed the Appendix: Revision code on device marking. Extended the applicability to STM8AL3xxxx devices. Updated: – Table 1: Device identification, – Table 2: Device summary, – the heading of Table 3: Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon limitations. 17-May-2017 7 Added Section 1.3.5: LCD / GPIO limitations and updated Table 3: Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon limitations 2-Jul-2021 8 Added Section 1.1.7: Stack roll-over limit not implemented. 01-Aug-2011 Changes ES0131 Rev 8 19/20 19 STM8AL3xxx STM8L052R8 STM8L1xxx6/8 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. 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