STP1612PW05
16-channel LED driver with 16-bit PWM,
8-bit gain and full LED error detection
Preliminary data
Features
■
16 constant current output channels
■
Supply voltage: 3.3 V or 5 V
■
Two PWM selectable counters 12/16-bit of
grayscale
■
Selectable enhanced PWM for ghost effect
reduction
■
Open and short LED detection
■
8-bit current gain control by means of 256
steps in two selectable ranges
■
Single resistor to set the current from 3 mA to
60 mA
■
Programmable progressive output delay
■
Thermal protection and thermal flag
■
UVLO
■
Schmitt trigger input
■
Selectable 16-bit or 256-bit serial data-in
format
■
Max clock frequency: 30 MHz
■
ESD protection 2.5 kV HBM, 200 V MM
■
Drop-in compatible with STP16CP\S\DP05
series
■
Available in high thermal efficiency TSSOP
exposed pad
Applications
■
Video display LED panels
■
RGB backlighting
■
Special lighting
Table 1.
Device summary
QFN-24
SO-24
TSSOP24
TSSOP24
exposed pad
Description
The STP1612PW05 is a 16-channel constant
current sink LED driver. The maximum output
current value for all the 16 channels is set by a
single resistor from 3 mA to 60 mA. The device
features 8-bit gain (256 steps) for global LED
brightness adjustment with two selectable ranges.
This function is accessible via a serial interface.
The device has an individual adjustable PWM
brightness control for each output channel. The
PWM counters are selectable via a serial
interface with 4096 or 65536 steps (12 or 16 bit).
The STP1612PW05 also provides enhanced
pulse-width modulation counting algorithms called
e-PWM to reduce flickering effects (ghost visual
effects) improving the overall image quality. The
device has a dual size 16-bit or 256-bit shift
register. All the control and the shift register read
back data are accessible via serial interface. The
STP1612PW05 has the capability to detect open
and short LED failure and overtemperature,
reporting the status through SPI line. The device
guarantees a 20 V output driving capability,
allowing the user to connect more LEDs in series.
Order code
Package
Packaging
STP1612PW05QTR
QFN-24
4000 parts per reel
STP1612PW05MTR
SO-24
1000 parts per reel
STP1612PW05TTR
TSSOP24
2500 parts per reel
STP1612PW05XTTR
TSSOP24 exposed pad
2500 parts per reel
February 2011
Doc ID 15819 Rev 5
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/41
www.st.com
41
Contents
STP1612PW05
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
Grey scales data loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Setting the PWM gray scale counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9.1
PWM data synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9.2
Synchronization for PWM counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10
Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11
Setting output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12
Constant current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13
Current gain adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
14
Delay time of staggered output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
15
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/41
Doc ID 15819 Rev 5
STP1612PW05
Contents
16
Time-out alert of GCLK disconnection . . . . . . . . . . . . . . . . . . . . . . . . . 26
17
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17.1
LED supply voltage (VLED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17.2
Setting grayscale brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.3
Multi device application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Doc ID 15819 Rev 5
3/41
Block diagram
Block diagram
Block diagram
GND
SDI
CLK
LE
SDO
VDD
UVLO & POR
Serial interface
CTRL command
and
CTRL logic
16-bit
Configuration
Register
R-EXT
Dual range gain
7-bit DAC
Gradual outputs
delay
TSD
Shift register
dual size mode
(16 or 256 bit)
PWM data buffer
(16x16 bit)
Open/short
error detection
PWM and e-PWM
12/16 bit counter
and SYNC control
PWCLK
4/41
Doc ID 15819 Rev 5
1----------16
Figure 1.
Constant current output channels
1
STP1612PW05
STP1612PW05
2
Summary description
Summary description
Table 2.
Typical current accuracy at 5 V
Output voltage
Current
accuracy
Output current
VDD
temp.
5V
25 °C
VDD
temp.
3.3 V
25 °C
Between ICs
≥ 1.0
± 6%
15 to 60
≥ 0,2
± 6%
3 to 15
Table 3.
Typical current accuracy at 3.3 V
Output voltage
Current
accuracy
Output current
Between ICs
≥ 1.0
± 6%
15 to 60
≥ 0,3
± 6%
3 to 15
Doc ID 15819 Rev 5
5/41
Summary description
Pin connection and description
OUT1
OUT13
OUT2
OUT3
OUT12
OUT11
OUT10
OUT4
OUT5
Note:
OUT6
OUT9
OUT7
OUT8
SDO
PWCLK
OUT0
OUT14
OUT1
OUT13
OUT2
OUT12
OUT3
OUT11
OUT4
OUT10
The exposed pad should be electrically connected to a metal land electrically isolated or
connected to ground
Table 4.
6/41
OUT15
OUT9
PWCLK
OUT15
OUT14
LE
OUT8
LE
OUT0
R-EXT
SDO
VDD
CLK
GND
VDD
R-EXT
OUT7
SDI
SDI
GND
CLK
Pin connection
OUT6
Figure 2.
OUT5
2.1
STP1612PW05
Pin description
Pin n°
Symbol
Name and function
1
GND
Ground terminal
2
SDI
Serial data input terminal
3
CLK
Clock input terminal used to shift data on rising edge and carries
command information when LE is asserted.
4
LE
5-20
OUT 0-15
21
PWCLK
22
SDO
23
R-EXT
24
VDD
Data strobe terminal and controlling command with CLK
Output terminals
Gray scale clock terminal.
Reference clock for grey scale PWM counter.
Serial data out terminal
Input terminal of an external resistor for constant current programing
Supply voltage terminal
Doc ID 15819 Rev 5
STP1612PW05
Electrical ratings
3
Electrical ratings
3.1
Absolute maximum ratings
Stressing the device above the rating listed in the Table 5 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 5.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD
Supply voltage
0 to 7
V
VO
Output voltage
-0.5 to 20
V
IO
Output current
60
mA
VI
Input voltage
-0.4 to VDD
V
1300
mA
50
MHz
-40 to + 170
°C
Value
Unit
Operating free-air temperature range
-40 to +125
°C
Operating thermal junction temperature range
-40 to +150
°C
Storage temperature range
-55 to +150
°C
SO-24
42.7
°C/W
TSSOP24
55
°C/W
37.5
°C/W
55
°C/W
IGND
GND terminal current
fCLK
Clock frequency
TJ
Junction temperature range (1)
1. Such absolute value is based on the thermal shutdown protection.
3.2
Thermal data
Table 6.
Symbol
TA
TJ-OPR
TSTG
RthJA
Thermal data
Parameter
Thermal resistance junctionambient (1)
TSSOP24(2)
Exposed pad
QFN-24
1. According to Jedec standard 51-7B
2. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
Doc ID 15819 Rev 5
7/41
Electrical ratings
3.3
STP1612PW05
Recommended operating conditions
Table 7.
Symbol
Recommended operating conditions at 25 °C
Parameter
Test conditions
Min.
Typ.
Max.
Unit
3.0
-
5.5
V
-
20
V
-
60
mA
VDD
Supply voltage
VO
Output voltage
IO
Output current, OUTn
IOH,SDO
Output current, SDO
-
+1
mA
IOL,SDO
Output current, SDO
-
-1
mA
3
VIH
Input voltage
0.7 VDD
-
VDD
V
VIL
Input voltage
GND
-
0.3 VDD
V
twLAT
LE pulse width
20
-
ns
twCLK
CLK pulse width
10
-
ns
twEN
PWCLK pulse width
20
-
ns
5
-
ns
5
-
ns
5
-
ns
tSETUP(D) Setup time for DATA
VDD = 3.3 V to 5.0 V
tHOLD(D) Hold time for DATA
tSETUP(L) Setup time for LATCH
fCLK
Clock frequency
Cascade operation
(1)
-
30
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please
considered the timings carefully.
8/41
Doc ID 15819 Rev 5
STP1612PW05
4
Electrical characteristics
Electrical characteristics
VDD = 3.3 V ± 10%, VDD = 5 V ± 10%, TA = 25 °C unless otherwise specified
Table 8.
Electrical characteristics
Symbol
VO
Characteristics
Maximum output voltage
OUT0~OUT115
IOUT
IOH,SDO
IOL,SDO
Output
current
Test conditions
Min.
Typ.
OUT0 ~ OUT15
VO = 2V
3
Max.
Unit
20
V
60
SDO
-8
SDO
8
mA
VIH
Input voltage “H” level
0.7 * VDD
VDD
V
VIL
Input voltage “L” level
GND
0.3 * VDD
V
IOH
Output leakage current
1
µA
0.4
V
VOL
Output voltage SDO
VO = 20 V
IOL = +8 mA
IOH = -8 mA
VOH
dIOUT1
Current skew (channel)
IOUT = 3mA, VO = 0.3V,
REXT = 238.2kΩ
dIOUT1
IOUT = 20mA, VO = 1V,
REXT = 34.7kΩ
dIOUT2
IOUT = 3mA, VO = 0.3V,
REXT = 238.2kΩ
Current skew (IC)
VDD - 0.4
V
±1.5
±3
%
±3
±6
%
IOUT = 20mA, VO = 1V,
REXT = 34.7kΩ
dIOUT2
%/dVO
Output current vs. output voltage
regulation
VO within 1.0 V and 3.0 V,
Rext = 34.7 kΩ @ 20 mA
± 0.1
± 0.5
%/V
%/dVDD
Output current vs. supply voltage
regulation
VDD within 4.5 V and 5.5 V
± 1.0
± 5.0
%/V
RIN(down)
Pull-down resistor
LE
200
250
kΩ
8
11
IO = 3 mA,
OUT0 ~ OUT15 = Off
8.5
11
IDD(off) 3
IO = 60 mA,
OUT0 ~ OUT15 = Off
11
15
IDD(on) 1
IO = 3 mA,
OUT0 ~ OUT15 = On
8
11.5
IO = 60 mA,
OUT0 ~ OUT15 = On
11.5
15
Rext = Open,
IDD(off) 1
IDD(off) 2
OUT0 ~ OUT15 = Off
Supply current “Off”
150
mA
Supply current “On”
IDD(on) 2
Doc ID 15819 Rev 5
9/41
Electrical characteristics
Figure 3.
STP1612PW05
Test circuit for electrical characteristics
IDD
VDD
IOUT
VIH,VIL
Function
Generator
V DD
..
.
OUT0
SDI
CLK
LE
OUT15
IOL
PWCLK
R - EXT GND
I OH
Logic input
waveform
VIH=VDD
R ext
V IL=GND
10/41
SDO
Doc ID 15819 Rev 5
STP1612PW05
Electrical characteristics
Table 9.
Symbol
Switching characteristics (VDD = 5.0 V) TA = -40 ~ 125 ° C
Characteristics
tSU0
tSU1
Setup time
tSU2
tH0
Hold time
tH1
tPD0
tPD1
Stagger delay
time
tDL3
tw( CLK)
Pulse width
tw(PWCLK)
Unit
LE ↑ – DCLK ↑
1
ns
LE ↓ – DCLK ↑
5
ns
CLK ↑ - SDI
3
ns
CLK ↑ - LE ↓
7
ns
PWCLK-OUTn4
(1)
OUTn4 + 1
(1)
OUTn4 + 2
(1)
OUTn4 +3
(1)
VDD = 5.0 V
VIH = VDD
VIL = GND
Rext = 460 Ω
VLED = 4.5 V
RL = 152 Ω
CL = 10 pF
C1 = 100 nF
C2 = 10 µF
IO = 20 mA
30
40
100
30
ns
ns
40
ns
40
ns
80
ns
120
ns
5
ns
CLK
20
ns
PWCLK
20
ns
tON
Output rise time of output ports
tOFF
Output fall time of output ports
tEDD
Max.
ns
LE
tw(L)
Typ.
1
LE – SDO(2)
tDL1
Min.
SDI - CLK ↑
CLK - SDO
Propagation
delay time
tPD2
tDL2
Conditions
Error detection minimum duration
(3)
10
ns
6
ns
1
µs
1. Refer to the timing waveform, where n = 0, 1, 2, 3.
2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after
the falling edge of LE.
3. Refer to Figure 5 on page 13.
Doc ID 15819 Rev 5
11/41
Electrical characteristics
Table 10.
Symbol
STP1612PW05
Switching characteristics (VDD = 3.3 V)
Characteristics
Conditions
Setup time
tSU2
tH0
tPD1
tPD2
tDL1
tDL2
tDL3
tw(L)
tw(CLK)
Max.
Unit
1
ns
LE ↑ – DCLK ↑
1
ns
LE ↓ – DCLK ↑
5
ns
CLK ↑ - SDI
3
ns
CLK ↑ - LE ↓
7
ns
Hold time
tH1
tPD0
Typ.
SDI - DCLK ↑
tSU0
tSU1
Min.
CLK - SDO
VDD = 3.3 V
Propagation delay
PWCLK-OUTn4(1) VIH = VDD
time
VIL = GND
LE – SDO(2)
Rext = 460 Ω
VLED = 4.5 V
OUTn4 + 1 (1)
RL = 152 Ω
Stagger delay
OUTn4 + 2 (1)
time
CL = 10 pF
OUTn4 +3 (1)
C1 = 100 nF
C2 = 10 µF
LE
5
ns
Pulse width
CLK
20
ns
PWCLK
20
ns
tw(PWCLK)
45
40
120
45
ns
ns
40
ns
40
ns
80
ns
120
ns
tON
Output rise time of output ports
11.6
ns
tOFF
Output fall time of output ports
7
ns
tDEC
Error detection duration
0.5
1
µs
1. Refer to the timing waveform Figure 4, where n = 0, 1, 2, 3.
2. In timing of “read configuration” and “read error status code”, the next CLK rising edge should be tPD2 after
the falling edge of LE.
Figure 4.
Test circuit for switching characteristics
V DD
IDD
C1
I OUT
VIH,VIL
Function
Generator
VDD
..
.
O UT0
SDI
CLK
LE
RL
CL
O UT 15
RL
P W CLK
R - E XT GND
SDO
CL
Logic input
VL ED
waveform
VIH=VDD
Rext
VIL=G ND
12/41
Doc ID 15819 Rev 5
CL
C2
STP1612PW05
5
Timing waveform
Timing waveform
Figure 5.
Timing waveform
PWCLK
PWCLK
PWCLK
Doc ID 15819 Rev 5
13/41
Principle of operation
6
STP1612PW05
Principle of operation
Table 11.
Control command
Signals combination
14/41
Description
Command name
LE
Number of CLK
rising edge when
LE is asserted
Data latch
High
1
Global latch
High
2 or 3
Buffer data are transferred to the comparators
Read configuration
High
4 or 5
Move out “configuration register” to the shift
register
Enable “error
detection”
High
6 or 7
Detect the status of each output’s LED
Read “error status
code”
High
8 or 9
Move out “error status code” of 16 outputs to
the shift registers
Write configuration
High
10 or 11
Serial data are transferred to the
“configuration register”
Reset to 16-bit shift
register length
High
12 or 13
Set to 16-bit the shift register length
Doc ID 15819 Rev 5
The action after a falling edge of LE
Serial data are transferred to the buffers
STP1612PW05
Figure 6.
Principle of operation
Timing diagram
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Configuration register
STP1612PW05
7
Configuration register
Table 12.
Configuration register
Bit
Attribute
Definition
Value
16 bit shift register
Read/Write
Shift register
length
0
15
1
256 bit shift register
Thermal error
flag
0
Temperature OK
1
Over temperature (>150°C typ.)
PWM counter
(12/16 bit)
0
12 bit Grayscale PWM counter
1
16 bit Grayscale PWM counter
00
64 times of MSB(1) 6-bit PWM counting plus once
of LSB(1) 6-bit PWM
01
16 times of MSB 6-bit PWM counting by 1/4
PWCLK plus once of LSB 6-bit PWM counting
14
13
Read
Read/Write
PWM counting
12-11 Read/Write
mode
selection
10
PWM data
Read/Write synchronizatio
n mode
9-2
Read/Write
Current gain
adjustment
1
Read/Write
Thermal
Shutdown
function
0
Time-out alert
Read/Write for PWCLK
disconnection
Function
0
0
0
10
4 times of MSB 6-bit PWM counting by 1/16
PWCLK plus once of LSB 6-bit PWM counting
11
PWM counting
0
Auto-synchronization
1
Manual synchronization
11
1
00000000
Adjust the current value set by R-EXT over 256
~
steps
11111111
0
Disable
1
Enable (2) (output channels OFF if temperature
overcomes 150°C)
0
Enable (3)
1
Disable
8b 10101011
0
0
1. Please refer to “setting the PWM counting mode” section.
2. Please refer to “TSD” thermal error flag and thermal shutdown “section.
3. Please refer to “time-out alert of PWCLK disconnection” section.
16/41
Default
value
Doc ID 15819 Rev 5
STP1612PW05
8
Grey scales data loading
Grey scales data loading
The STP1612PW05 is able to manage a gray-scale depth of 12 or 16 bits for each output,
exploiting an e-PWM algorithm.
The bit D of the configuration register is used to select the grey-scale loading. Its value can
be set to “0” for 12 bits or “1” for 16 bits. By default, D is set to “0”.
Loading of the data is performed through the serial input on a dedicated buffer and two
different methods can be used.
With both methods, the first incoming data packet is relative to the output 15; the following
packet is relative to the output 14 and so on up to the output 0.
If F=”0”, when a data packet has been loaded, the latch signal (LE) must become active for
one CLK cycle (data latch). When the last data packet, relative to the output 0, has been
loaded, the latch signal must be active for two CLK cycles (global latch) and all the data will
be transferred to the e-PWM registers starting from the MSB.
If F=”1” all data packets (12 or 16 bits x16) are loaded and then the global latch signal must
be active and all the data will be transferred to the e-PWM registers starting from the MSB.
Figure 7.
Full timing for data loading
Doc ID 15819 Rev 5
17/41
Setting the PWM gray scale counter
9
STP1612PW05
Setting the PWM gray scale counter
STP1612PW05 provides a 12-bit or 16-bit PWM color depth. Each serial data input will be
implemented according to the e-PWM algorithm.
9.1
PWM data synchronization
STP1612PW05 defines the different counting algorithms that support e-PWM, technology,
(scrambled PWM). With e-PWM, the total PWM cycles can be broken down into MSB (most
significant bits) and LSB (least significant bits) of gray scale cycles, and the MSB
information can be dithered across many refresh cycles to achieve overall same high bit
resolution. STP1612PW05 also allows changing different counting algorithms and provides
the best output linearity when there are fewer transitions of output.
Figure 8.
12-bit e-PWM operation example
PWCLK
PWCLK
PWCLK
PWCLK
PWCLK
18/41
Doc ID 15819 Rev 5
STP1612PW05
9.2
Setting the PWM gray scale counter
Synchronization for PWM counting
The data synchronization between the incoming data flow and the output channels is
managed through the bit A within the configuration register.
If the bit A is set to “0” the device performs itself the data synchronization: when all the new
data are loaded with a “global latch”, the device wait until all the PWM counter completes
the counting cycle before updating them with the new data, at the next CLK rising edge.
Conversely, if bit A is set to “1” (default), the data synchronization is not performed by the
device and is managed by the microcontroller, which has to take care of the data and
signals. If this is not done, there might be artefacts on the output image.
Figure 9.
Synchronization for PWM counting
CLK
PWCLK
Figure 10. Without synchronization for PWM counting
CLK
PWCLK
Doc ID 15819 Rev 5
19/41
Error detection conditions
10
STP1612PW05
Error detection conditions
The STP1612PW05 can detect open channels (OD) and LED short-circuits (SD).
The detection circuitry performs open- and short-circuit detection simultaneously and needs
that all channels must be on. However the short test duration (0.5 µs typ) does not impact
the image quality.
According to Table 11, the command “Enable Error Detection” starts the diagnostic process.
After 0.5 µs (typ) the faults detection has already been carried out and, through the
command “Read Error Status Code”, the status is available on the serial output (SDO).
A bit set to "1" in the Error Status Code represents a channel considered good, whereas a
"0" represents a failed output (open/short).
Figure 11 describes the error detection process.
Figure 11. Error detection process
“Read Error Status Code”
command
“Enable Error Detection”
command
CLK
LE
from SDI
SDO
don’t care
don’t care
ERROR STATUS CODE
detection of faulty
channels (typ 0.5µs)
The Table 13 and Figure 12 explains the fault conditions detected by the diagnostic circuitry
and how the detection is performed.
Table 13.
Note:
20/41
Detection conditions (VDD = 3.3 to 5 V temp. range -40 to 125 °C)
SW-1 or
SW-3b
Open line or output short to GND
detected
==> IODEC ≤0.5 x IO
SW-2 or
SW-3a
Short on LED or short to V-LED
detected
==> VO ≥ 2.3 V
Where: IO = the output current programmed by the REXT, IODEC = the detected output
current in detection mode
Doc ID 15819 Rev 5
STP1612PW05
Error detection conditions
Figure 12. Detection circuit
16
STP1612PW05
Doc ID 15819 Rev 5
21/41
Setting output current
11
STP1612PW05
Setting output current
The output current (IOUT) is set by an external resistor, Rext.
It is calculated from the equation:
VR-EXT = 1.24 x G; IOUT = (VR-EXT/Rext) x 560
Whereas Rext is the resistance of the external resistor connected to R-EXT terminal
and VR-EXT is its voltage. G is the digital current gain, which is set by the bit9 – bit2 of the
configuration register. The default value of G is 1. For your information, the output current is
about 20 mA when Rext = 34.70 kΩ and 10 mA when Rext = 69.6 kΩ if G is set to
default value 1. The formula and setting for G are described in next section.
Rext (kOhm)
Figure 13. Rext vs output current
275
250
225
200
175
150
125
100
75
50
25
0
3
5
10
20
30
50
60
Iout (mA)
Table 14.
Rext vs output current (1)
Iout (mA)
Rext (kΩ)
3
238.2
5
142.2
10
69.6
20
34.70
30
22.94
50
13.72
60
11.40
80
8.63
1. TA = 25 °C, Vdd = 3.3 V; 5.0 V, VLed = 3.0 V, Vdrop = 1.5 V, HC = 0101011 (default)
22/41
Doc ID 15819 Rev 5
80
STP1612PW05
12
Constant current
Constant current
The STP1612PW05 assures nearly no variation in current both from channel to channel and
from IC to IC.
The typical variation of the current between channels of the same IC is ±1.5%, whereas the
variation between ICs is around ±3%.
Moreover the current characteristic of the output stage is flat (see Figure 14 and Figure 15).
This contributes to keep the current constant regardless of the variation of the LEDs forward
voltage (VF) and consequently guarantees uniformity of brightness.
Figure 14. IOUTvs voltage drop across current generators (3.3 V supply voltage)
Figure 15. IOUT vs voltage drop across current generators (5 V supply voltage)
The typical characteristics in Figure 14 and Figure 15 also show the minimum voltage drop
required to assure that the current generators regulate the desired current.
This must be taken into account when choosing the suitable value of the LED supply voltage
(see dedicated section).
Doc ID 15819 Rev 5
23/41
Current gain adjustment
13
STP1612PW05
Current gain adjustment
Figure 16. Gain vs DA6 - DA0
The bit 9 to bit 2 of the configuration register set the gain of output current, i.e., G. Being 8bit in total, ranging from 8’b00000000 to 8’b11111111, these bits allow the user to set the
output current gain up to 256 levels. These bits can be further defined in the configuration
register as follows:
Configuration register
MSB
LSB
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
HC
DA6
DA5
DA4
DA3
DA2
DA1
DA0
-
-
1.
Bit 9 is HC bit. The setting is in the low current range when HC=0, and in the high
current range when HC=1.
2.
Bit 8 to bit 2 are DA6 ~ DA0.
The relationship between these bits and current gain G is:
HC = 1, D = (256G-128)/3
HC = 0, D = (1024G-128)/3
and D in the above decimal numeration can be converted to its equivalent in binary form by
the following equation:
D = DA6x26 + DA5x25 + DA4x24 + DA3x23 + DA2x22 + DA1x21 + DA0x20
In other words, these bits can be looked as a floating number with 1-bit exponent HC and 7bit mantissa DA6~DA0.
24/41
Doc ID 15819 Rev 5
STP1612PW05
Delay time of staggered output
For example,
HC = 1, G = 1.25, D = (256x1.25-128)/3 = 64
the D in binary form would be:
D = 64 = 1x26+0x25+0x24+0x23+0x22+0x21+0x20
The bit 9 to bit 2 of the configuration register are set to 8’b1100,0000.
14
Delay time of staggered output
This feature prevents large inrush current from the power line and reduces the bypass
capacitors.
The outputs are organized in four groups OUT4n, OUT4n+1, OUTn4+2, OUT4n+3 and each
group has 40 ns delay between the previous one.
E.g.: OUT4n has no delay, OUTn4+1 has 40ns delay, OUTn4+2 has 80ns delay, OUTn4+3
has 120 ns delay.
15
Thermal protection
Thermal flag provides an indication about the status of the junction temperature. When the
junction temperature reaches 150 °C the bit E of the configuration register is set to “1”,
signaling dangerous operating condition. This flag is useful when thermal shutdown function
is disabled.
The thermal shutdown function, if activated by configuration register (bit “1” set to 1), turnsoff all output channels if the junction exceeds 150 °C. As soon as the junction temperature is
below 140 °C the outputs channels will be turned ON. In thermal shutdown mode, the digital
core is active and data flow is guaranteed.
Doc ID 15819 Rev 5
25/41
Time-out alert of GCLK disconnection
16
STP1612PW05
Time-out alert of GCLK disconnection
When the PWCLK signal is disconnected for around 1 second, all output ports will be turned
off automatically. This function will protect the LED display system from staying ON
indefinitely and prevent excessive current from damaging the power system. The default is
set to ‘enable” when bit “0” of the Configuration Register is 0. When the PWCLK is active
again and new serial data are moved in, the driver resumes to work after resetting the
internal counters and comparators.
Figure 17. Time-out alert application scheme
PWCLK
500K
STP1612PW05
26/41
STP1612PW05
Doc ID 15819 Rev 5
STP1612PW05
STP1612PW05
STP1612PW05
Application information
17
Application information
17.1
LED supply voltage (VLED)
The choice of the LED supply voltage (VLED) must be carried out considering several
parameters:
●
The voltage drop across current generators (VO), which must be enough to guarantee
the desired current (see Figure 14 and Figure 15)
●
The maximum LED forward voltage (VF,max)
●
The maximum power that can be dissipated by the package under the application
ambient conditions
●
The accuracy of the supply voltage itself (VLED can vary in a range and the minimum
value should be considered)
Therefore the minimum LED supply voltage can be calculated as:
VLED,min = VO,typ + VF,max
The LED supply voltage should be higher than VLED,min (to consider any fluctuation of the
involved parameters) but not too high in order to keep low the power dissipation:
16
PD = VDD ⋅ IDD +
∑V
O,i
⋅ ICHi ⋅ Di
i =1
where Di is the duty cycle of the channel i.
In particular the power dissipation should be kept below the maximum power dissipation,
defined as:
PD,max =
(Tj − Ta )
θ ja
To summarize, the choice of the proper power supply must be a trade-off between the
correct value that assures the desired LED current and low power dissipation.
In RGB application, there can be a significant variability of the LEDs forward voltage (e.g.
red LEDs have a lower forward voltage compared to green and blue ones).
In this case the supply voltage must be chosen high enough to correctly switch on the LEDs
with the highest forward voltage (green or blue). However this supply voltage is higher than
the voltage required by red LEDs. Thus, the excess of voltage in the lines with red LEDs
drops on the current generators, bringing to an increase of the power dissipation and loss of
efficiency.
Moreover the extra-voltage across the red LEDs driving generators could cause an
erroneous shorted LED condition detection.
Doc ID 15819 Rev 5
27/41
Application information
STP1612PW05
To avoid these drawbacks, two different approaches are possible:
●
Figure 18 shows an application with only one voltage rail (VLED). A resistor in series to
each red LEDs is added. In this way, the voltage excess drops across the resistor
instead of dropping across the current generators. This solution implies a significant
reduction of the power dissipated by the chip. However the total power dissipation does
not change and a remarkable part of the power is still wasted on the series resistor.
This not only affects the efficiency, but also raises the cost of the system due to the need to
dissipate the generated heat.
Figure 18. Solution with single supply voltage
VRred
VLED
5V
Rred
……
VF,green
OUT15
OUT0
VO,red
OUT15
VO,green
VO,blue
SDO
STP1612PW05
……
to SDI of
the next
device
……
VRred
STP1612PW05
to SDI of
the next
device
……
to SDI of
the next
device
OUT15
OUT0
SDO
STP1612PW05
Rred
……
VF,green
OUT15
OUT0
……
……
VF,red
VF,blue
OUT15
OUT0
VO,red
from SDO of
the previous
device
VF,blue
OUT0
SDO
SDI
……
……
VF,red
VO,green
SDI
STP1612PW05
OUT15
OUT0
VO,blue
SDI
STP1612PW05
from SDO of
the previous
device
STP1612PW05
from SDO of
the previous
device
VLED
VO,green
VO,blue
VF,green
VF,blue
VO,red + VRred
VF,red
●
28/41
Figure 19 shows a solution with two separate voltage rails: one for blue and green
LEDs (VLED) and one for red LEDs (VLED_RED), which can be derived from the
former (e.g. simply using a voltage regulator). This solution is by far the most
advantageous in terms of power dissipation. Voltage rails are tailored to the type of
LEDs they drive and the wasted power is significantly reduced as well as the heat
produced.
Doc ID 15819 Rev 5
STP1612PW05
Application information
Figure 19. Solution with separated supply voltage for red LEDs
VLED_RED = 3.3V
VLED = 5V
……
VF,green
OUT15
O UT0
VF,b lue
OUT15
O UT0
VO,red
VO, blue
SDO
SDO
STP1612PW05
STP1612PW05
……
……
V F,red
VF,green
OUT15
O UT0
……
……
STP1612PW05
to SDI of
the next
device
……
to SDI of
the next
device
……
to SDI of
the next
device
VF,b lue
OUT15
O UT0
VO,red
OUT0
VO,green
SDI
SDI
STP1612PW05
from SDO of
the previous
device
OUT15
VO, blue
SDI
STP1612PW05
from SDO of
the previous
device
STP1612PW05
from SDO of
the previous
device
VLED
V O,green
V F,green
V F,blue
VLED_RED
V F,red
17.2
OUT15
OUT0
VO,green
SDO
V O,blue
……
……
V F,red
VLED
5V
V O,red
voltage
regulator
VLED_RED
3.3V
Setting grayscale brightness
As explained in section 8, the brightness of each channel can be adjusted using 12 or 16 bit
per channel PWM control scheme, resulting in respectively 4095 or 65535 steps, from 0% to
100% brightness.
The brightness level of each output can be calculated as:
Brightness % =
GS value,n
GS max
⋅ 100
Where GSvalue,n is the programmed grayscale value for OUTn (n from 0 to 15), which can be
up to 4095 or 65535, whereas GSmax is the maximum grayscale value programmable: 4095
(12bit) or 65535 (16bit).
So, once the brightness level for the channel n is defined, according to the bit “D” of the
configuration register (see section 8), the GSvalue,n can be calculated. Then, converting this
value into a binary word, the correct string to load into the register is achieved (see
Figure 20).
Doc ID 15819 Rev 5
29/41
Application information
STP1612PW05
Figure 20. Example of brightness setting
GSm ax = 65535
GSvalue, n = 45875
Word = 1011 0011 0011 0010
Brightness%
70%
17.3
GS word
channel 15
GS word
channel 14
…….
GS word
channel n
…….
GS word
channel 1
GS word
channel 0
100%
Multi device application
In a typical application several devices are used to drive the LEDs.
In this case more STP1612PW05 can be connected together in a daisy chain configuration
as shown in Figure 21.
Figure 21. STP1612PW05 in daisy chain configuration
VLED
….
….
OUT0
OUT15
OUT0
SDO
SDI
µC
….
R-EXT
OUT15
SDI
….
R-EXT
CLK
CLK
LE
PWCLK
LE
PWCLK
GND
STP1612PW05
IC#1
3
30/41
GND
VDD
VDD
Doc ID 15819 Rev 5
STP1612PW05
IC#n
STP1612PW05
18
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 15.
TSSOP24 mechanical data
mm.
inch
Dim.
Min.
Typ
A
A1
Max.
Min.
Typ.
1.1
0.05
A2
0.15
Max.
0.043
0.002
0.9
0.006
0.035
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
7.7
7.9
0.303
0.311
E
4.3
4.5
0.169
0.177
e
0.65 BSC
0.0256 BSC
H
6.25
6.5
0.246
0.256
K
0°
8°
0°
8°
L
0.50
0.70
0.020
0.028
Figure 22. TSSOP24 package dimensions
Doc ID 15819 Rev 5
31/41
Package mechanical data
Table 16.
STP1612PW05
TSSOP24 tape and reel
mm.
inch
Dim.
Min.
A
Typ
Max.
-
330
13.2
Typ.
Max.
-
12.992
0.504
-
0.519
C
12.8
-
D
20.2
-
0.795
-
N
60
-
2.362
-
T
-
22.4
-
0.882
Ao
6.8
-
7
0.268
-
0.276
Bo
8.2
-
8.4
0.323
-
0.331
Ko
1.7
-
1.9
0.067
-
0.075
Po
3.9
-
4.1
0.153
-
0.161
P
11.9
-
12.1
0.468
-
0.476
Figure 23. TSSOP24 reel dimensions
32/41
Min.
Doc ID 15819 Rev 5
STP1612PW05
Package mechanical data
Table 17.
SO-24 mechanical data
mm.
inch
Dim.
Min.
Typ
Max.
Min.
Typ.
Max.
A
2.35
2.65
2.36
A1
0.1
0.3
0.12
0.15
0.18
B
0.33
0.51
0.375
0.4
0.425
C
0.23
0.32
D (1)
15.2
15.6
15.43
15.46
15.49
E
7.4
7.6
7.52
7.55
7.58
e
0.292
1.27
1.27
H
10
10.65
h
0.25
0.75
L
0.4
1.27
0.6
k
0
8
2
ddd
2.5
0.1
10.2
10.3
10.4
0.35
0.75
4
6
0.06
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
Doc ID 15819 Rev 5
33/41
Package mechanical data
STP1612PW05
Figure 24. SO-24 package dimensions
34/41
Doc ID 15819 Rev 5
STP1612PW05
Package mechanical data
Table 18.
SO-24 tape and reel
mm.
inch
Dim.
Min.
A
Typ
Max.
-
330
13.2
Min.
Typ.
Max.
-
12.992
0.504
-
0.519
C
12.8
-
D
20.2
-
0.795
-
N
60
-
2.362
-
T
-
30.4
-
1.197
Ao
10.8
-
11.0
0.425
-
0.433
Bo
15.7
-
15.9
0.618
-
0.626
Ko
2.9
-
3.1
0.114
-
0.122
Po
3.9
-
4.1
0.153
-
0.161
P
11.9
-
12.1
0.468
-
0.476
Figure 25. SO-24 reel dimensions
Doc ID 15819 Rev 5
35/41
Package mechanical data
Table 19.
STP1612PW05
TSSOP24 exposed pad
mm
inch
Dim.
Min.
Typ.
Max.
A
1.2
A1
0.15
A2
0.8
b
Max.
0.047
0.004
0.006
0.039
0.041
0.031
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
7.7
7.8
7.9
0.303
0.307
0.311
D1
4.7
5.0
5.3
0.185
0.197
0.209
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.5
0.169
0.173
0.177
E2
2.9
3.2
3.5
0.114
0.126
0.138
0.65
K
0°
L
0.45
0.60
0.0256
8°
0°
0.75
0.018
Figure 26. TSSOP24 package dimensions
36/41
Typ.
1.05
e
1
Min.
Doc ID 15819 Rev 5
8°
0.024
0.030
STP1612PW05
Package mechanical data
Table 20.
QFN24 (4x4) mechanical data
mm.
mils
Dim.
Min.
Typ
A
Max.
Min.
Typ.
1.00
Max.
39.4
A1
0.00
0.05
0.0
2.0
b
0.18
0.30
7.1
11.8
D
3.9
4.1
153.5
161.4
D2
2.6
2.8
76.8
88.6
E
3.9
4.1
153.5
161.4
E2
2.6
2.8
76.8
88.6
e
L
0.50
0.40
19.7
0.60
Doc ID 15819 Rev 5
15.7
23.6
37/41
Package mechanical data
STP1612PW05
Figure 27. QFN24 (4x4) mechanical drawing
38/41
Doc ID 15819 Rev 5
STP1612PW05
Package mechanical data
Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
330
C
12.8
D
20.2
N
99
13.2
MAX.
12.992
0.504
0.519
0.795
101
T
3.898
3.976
14.4
0.567
Ao
4.35
0.171
Bo
4.35
0.171
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
Doc ID 15819 Rev 5
39/41
Revision history
19
STP1612PW05
Revision history
Table 21.
40/41
Document revision history
Date
Revision
Changes
17-Jun-2009
1
Initial release.
10-Aug-2009
2
Updated Section 9.2 on page 19 and Table 11 on page 14
29-Oct-2009
3
Updated: Figure 2 on page 6 and Table 20 on page 37
Added: Figure 17 on page 26
18-Dec-2009
4
Updated Section 11 on page 22
08-Feb-2011
5
Updated Table 17 on page 33 and Figure 24 on page 34
Doc ID 15819 Rev 5
STP1612PW05
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Doc ID 15819 Rev 5
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