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STP8NS25

STP8NS25

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    SOT78

  • 描述:

    MOSFET N-CH 250V 8A TO-220

  • 数据手册
  • 价格&库存
STP8NS25 数据手册
N-CHANNEL 250V - 0.38Ω - 8A TO-220/TO-220FP MESH OVERLAY™ MOSFET TYPE STP8NS25 STP8NS25FP s s s STP8NS25 STP8NS25FP VDSS 250 V 250 V RDS(on) < 0.45 Ω < 0.45 Ω ID 8A 8A TYPICAL RDS(on) = 0.38 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED 3 1 2 1 2 3 DESCRIPTION Using the latest high voltage MESH OVERLAY ™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for lighting applications. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITH MODE POWER SUPPLIES (SMPS) s DC-DC CONVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT TO-220 TO-220FP INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (q) PTOT dv/dt (1) VISO Tstg Tj Parameter STP8NS25 Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Insulation Withstand Voltage (DC) Storage Temperature Max. Operating Junction Temperature –65 to 150 150 (1) ISD≤ 8A, di/dt≤300 A/µs, VDD≤ V (BR)DSS, Tj ≤TjMAX (*)Limited only by maximum temperature allowed Value STP8NS25FP 250 250 ± 20 8 5 32 80 0.64 5 2000 8(*) 5(*) 32(*) 30 0.24 Unit V V V A A A W W/°C V/ns V °C °C (•)Pulse width limited by safe operating area April 2001 1/9 STP8NS25/STP8NS25FP THERMAL DATA TO-220 Rthj-case Rthj-amb Rthc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose 1.56 62.5 0.5 300 TO-220FP 4.11 °C/W °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 µA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 °C VGS = ±20V Min. 250 1 10 ±100 Typ. Max. Unit V µA µA nA ON (1) Symbol VGS(th) RDS(on) ID(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance On State Drain Current Test Conditions VDS = VGS, ID = 250µA VGS = 10V, ID = 4 A VDS > ID(on) x RDS(on)max, VGS = 10V Min. 2 Typ. 3 0.38 8 Max. 4 0.45 Unit V Ω A DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS > ID(on) x RDS(on)max, ID = 4A VDS = 25V, f = 1 MHz, VGS = 0 Min. 7 Typ. 8 770 118 48 Max. Unit S pF pF pF 2/9 STP8NS25/STP8NS25FP ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 125 V, ID = 4 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) VDD = 200V, ID = 8 A, VGS = 10V Min. Typ. 13 18 37 5.2 14.8 51.8 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol td(Voff) tf tr(Voff) tf tc Parameter Turn-off- Delay Time Fall Time Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 125V, ID = 4 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 3) Vclamp = 200V, ID = 8 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Min. Typ. 51 16 12.5 12.5 28 Max. Unit ns ns ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 8 A, VGS = 0 ISD = 8 A, di/dt = 100A/µs VDD = 30V, Tj = 150°C (see test circuit, Figure 5) 198 1.1 11.3 Test Conditions Min. Typ. Max. 8 32 1.7 Unit A A V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP8NS25/STP8NS25FP Thermal Impedence for TO-220 Thermal Impedence for TO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP8NS25/STP8NS25FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP8NS25/STP8NS25FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP8NS25/STP8NS25FP TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 D F1 G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/9 STP8NS25/STP8NS25FP TO-220FP MECHANICAL DATA DIM. MIN. A B D E F F1 F2 G G1 H L2 L3 L4 L6 L7 Ø 28.6 9.8 15.9 9 3 4.4 2.5 2.5 0.45 0.75 1.15 1.15 4.95 2.4 10 16 30.6 10.6 16.4 9.3 3.2 1.126 0.385 0.626 0.354 0.118 mm TYP. MAX. 4.6 2.7 2.75 0.7 1 1.7 1.7 5.2 2.7 10.4 MIN. 0.173 0.098 0.098 0.017 0.030 0.045 0.045 0.195 0.094 0.393 0.630 1.204 0.417 0.645 0.366 0.126 inch TYP. MAX. 0.181 0.106 0.108 0.027 0.039 0.067 0.067 0.204 0.106 0.409 A B L3 L6 L7 F1 D ¯ F G1 E H F2 123 L2 L4 8/9 G STP8NS25/STP8NS25FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2001 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9
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