STS5DPF20L

STS5DPF20L P-CHANNEL 20V - 0.045Ω - 5A SO-8 STripFET™ II MOSFET Figure 1: Package Table 1: General Features TYPE STS5DPF20L ■ ■ ■ ■ ■ VDSS RDS(on) ID 20 V < 0.055 Ω 5A TYPICAL RDS(on) = 0.045 Ω CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DRIVE STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY DESCRIPTION This MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS ■ DC/DC CONVERTERS ■ BATTERY MANAGEMENT IN NOMADIC EQUIPMENT ■ POWER MANAGEMENT IN CELLULAR PHONES ■ DC MOTOR DRIVE ) s ( ct c u d SO-8 e t le ) s t( o r P Figure 2: Internal Schematic Diagram o s b O - u d o r P e t e l o s b O Table 2: Order Codes PART NUMBER MARKING PACKAGE PACKAGING STS5DPF20L S5DPF20L SO-8 TAPE & REEL Rev. 2 September 2004 1/9 STS5DPF20L Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS Value Unit Drain-source Voltage (VGS = 0) Parameter 20 V Drain-gate Voltage (RGS = 20 kΩ) 20 V ± 16 V ID Drain Current (continuous) at TC = 25°C Single Operating 5 A ID Drain Current (continuous) at TC = 100°C Single Operating 4 A Drain Current (pulsed) 20 A Total Dissipation at TC = 25°C Dual Operating Total Dissipation at TC = 25°C Single Operating 1.6 2 W W 150 -55 to 150 °C °C IDM (
) PTOT Tj Tstg Gate- source Voltage Operating Junction Temperature Storage Temperature (
) Pulse width limited by safe operating area Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed Table 4: Thermal Data Rthj-case Thermal Resistance Junction-case Single Operating Dual Operating 62.5 78 Maximum Lead Temperature For Soldering Purpose 300 Tl r P e t le uc ) s t( od °C/W °C/W °C ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol Parameter Test Conditions so Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS= Max Rating VDS= Max Rating, TC= 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS= ± 16V V(BR)DSS VGS(th) Gate Threshold Voltage RDS(on) Static Drain-source On Resistance t c u od r P e (s) b O - VDS = VGS, ID= 250 µA Min. Typ. Max 20 1 VGS= 10 V, ID= 2.5 A VGS= 4.5 V, ID= 2.5 A Unit V 1 10 µA µA ±100 nA 1.6 2.5 V 0.045 0.070 0.055 0.075 Ω Ω Typ. Max. Unit Table 6: Dynamic t e l o Symbol gfs (1) s b O Ciss Coss Crss Parameter Test Conditions Forward Transconductance VDS = 15 V, ID= 2.5 A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 16V, f = 1 MHz, VGS = 0 (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 2/9 Min. 10 1350 490 130 S pF pF pF STS5DPF20L ELECTRICAL CHARACTERISTICS(CONTINUED) Table 7: Switching On Symbol Parameter Test Conditions td(on) tr Turn-on Delay Time Rise Time VDD = 15 V, ID = 2 A, RG= 4.7 Ω, VGS = 4.5 V (see Figure 15)) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 24 V, ID = 4 A, VGS = 5 V (see, Figure 18) Min. Typ. Max. 25 35 Unit ns ns 12.5 5 3 16 nC nC nC Typ. Max. Unit Table 8: Switching Off Symbol td(off) tf Parameter Test Conditions Turn-off Delay Time Fall Time Min. 125 35 VDD = 15 V, ID = 2.5 A, RG= 4.7 Ω, VGS = 4.5 V (see, Figure 15) ns ns Table 9: Source-Drain Diodef Symbol ISD Parameter Test Conditions Min. Typ. ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 5 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5 A, di/dt = 100 A/µs VDD = 15V, Tj = 150°C (see, Figure 16) trr Qrr IRRM (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area. ) s ( ct e t le Pr od 45 36 1.6 Unit 5 A 20 A 1.2 V uc Source-drain Current ) s t( Max. ns nC A o s b O - u d o r P e t e l o s b O 3/9 STS5DPF20L Figure 3: Safe Operating Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics c u d e t le Figure 5: Transconductance u d o ) s ( ct r P e t e l o s b O 4/9 ) s t( o r P o s b O - Figure 8: Static Drain-Source On Resistance STS5DPF20L Figure 9: Gate Charge vs Gate-Source Voltage Figure 12: Capacitances Variations Figure 10: Normalized Gate Thereshlod Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature c u d e t le ) s ( ct ) s t( o r P o s b O - Figure 11: Source-Drain Diode Forward Characteristics u d o r P e t e l o s b O 5/9 STS5DPF20L Figure 14: Unclamped Inductive Load Test Circuit Figure 17: Unclamped Inductive Wafeform Figure 15: Switching Times Test Circuit For Resistive Load Figure 18: Gate Charge Test Circuit c u d e t le ) s ( ct u d o r P e o s b O - Figure 16: Test Circuit For Inductive Load Switching and Diode Recovery Times t e l o s b O 6/9 o r P ) s t( STS5DPF20L SO-8 MECHANICAL DATA mm. DIM. MIN. TYP A inch MAX. MIN. TYP. MAX. a1 1.75 0.1 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 c1 45 (typ.) 1.27 e e3 3.81 0.150 F 3.8 4.0 0.14 L 0.4 1.27 0.015 M 0.244 0.050 0.157 c u d 0.050 0.6 S 0.023 8 (max.) e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 7/9 STS5DPF20L Table 10: Revision History Date Revision 10-Sep-2004 2 Description of Changes Complete Version c u d e t le ) s ( ct u d o r P e t e l o s b O 8/9 o s b O - o r P ) s t( STS5DPF20L c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. t e l o s b O The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 9/9