T835T-8G

T835T-8G Datasheet 8 A 800 V D2PAK Snubberless™ Triac Features A2 G • • • • • High static dV/dt High dynamic turn-off commutation (dl/dt)c 150 °C maximum junction temperature Three quadrants Surge capability VDSM, VRSM = 900 V D²PAK • Benefits: – High immunity to false turn-on thanks to high static dV/dt – Better turn-off in high temperature environments thanks to (dI/dt)c – Increase of thermal margin due to extended working Tj up to 150 °C A2 A1 A2 A2: Anode2 – A1: Anode1 G: Gate G A1 Good thermal resistance due to non-insulated tab. Applications • • • • • • • General purpose AC line load switching Motor control circuits Home appliances Heating Lighting Inrush current limiting circuits Overvoltage crowbar protection Product status link Description T835T-8G IT(RMS) 8A VDRM/VRRM 800 V Available in SMD, the T835T-8G Triac can be used for the on/off or phase angle control function in general purpose AC switching where high commutation capability is required. The T835T-8G can be used without a snubber RC circuit when the limits defined are respected. VDSM/VRSM 900 V D2PAK package is UL-94,V0 flammability resin compliance. IGT 35 mA Package environmentally friendly Ecopack®2 graded (RoHS and Halogen Free compliance). Product summary Snubberless™ is a trademark of STMicroelectronics. DS12531 - Rev 3 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com T835T-8G Characteristics 1 Characteristics Table 1. Absolute maximum ratings (limiting values) Symbol IT(RMS) ITSM I2t dl/dt Parameter 8 Non repetitive surge peak on-state current (full cycle, Tj initial = 25 °C t = 16.7 ms 63 t = 20 ms 60 I2t value for fusing tp = 10 ms 24 A2s Critical rate of rise of on-state current, IG = 2 x IGT, tr ≤ 100 ns Tj initial = 150 °C, f = 100 Hz 100 A/µs Tj = 125 °C 800 V Tj = 150 °C 600 V tp = 10 ms, Tj = 25 °C 900 V 4 A 5 V 1 W Storage junction temperature range -40 to +150 °C Operating junction temperature range -40 to +150 °C IGM Peak gate current VGM Peak Gate Voltage Tj A Tc = 128 °C VDSM/VRSM Non Repetitive peak off-state voltage Tstg Unit RMS on-state current (full sine wave) VDRM/VRRM Repetitive peak off-state voltage (50-60 Hz) PG(AV) Value tp = 20 µs, Tj = 150 °C Tj = 150 °C Average gate power dissipation A Table 2. Electrical characteristics (Tj = 25 °C, unless otherwise specified) Symbol Quadrants; Tj Test conditions Value Unit VD = 12 V, RL = 30 Ω I - II - III Min. 1.75 mA VD = 12 V, RL = 30 Ω I - II - III Max. 35 mA VGT VD = 12 V, RL = 33 Ω I - II - III Max. 1.3 V VGD VD = 600 V, RL = 3.3 kΩ I - II - III Min. 0.2 V IG = 1.2 x IGT I - III Max. 60 mA IG = 1.2 x IGT II Max. 70 mA Max. 40 mA IGT IL IH (1) dV/dt (1) (dl/dt)c (1) Tj = 150 °C IT = 500 mA, gate open VD = 536 V, gate open Tj = 125 °C Min. 2000 V/µs VD = 402 V, gate open Tj = 150 °C Min. 1000 V/µs Tj = 125 °C Min. 8 A/ms Tj = 150 °C Min. 4 A/ms Without snubber, (dV/dt)c > 20 V/µs 1. For both polarities of A2 referenced to A1. DS12531 - Rev 3 page 2/11 T835T-8G Characteristics Table 3. Static characteristics Symbol (1) Tj Test conditions Value Unit IT = 11.3 A, tp = 380 µs 25 °C Max. 1.6 V VTO(1) Threshold on-state voltage 150 °C Max. 0.87 V RD(1) Dynamic resistance 150 °C Max. 80 mΩ 5 µA 1.0 mA 2.5 mA VTM IDRM/IRRM 25 °C VDRM = VRRM = 800 V Max. 125°C VDRM = VRRM = 600 V 150 °C Max. 1. For both polarities of A2 referenced to A1. Table 4. Thermal resistance Symbol Rth(j-c) DS12531 - Rev 3 Parameter Junction to case (AC) D²PAK Max. Value Unit 1.9 °C/W page 3/11 T835T-8G Characteristics (curves) 1.2 Characteristics (curves) Figure 1. Maximum power dissipation versus on-state RMS current Figure 2. On-state RMS current versus case temperature IT(RMS)(A) P(W) 9 12 8 α = 180° α = 180° 7 10 6 8 5 4 6 3 2 4 0 IT(RMS)(A) 0 0 0 1 2 3 4 Tc(°C) 1 180° 2 5 6 7 25 50 75 100 125 150 8 Figure 3. On-state RMS current versus ambient temperature (free air convection) Figure 4. Relative variation of thermal impedance versus pulse duration IT(RMS)(A) K = [Zth/Rth] 1.0E+00 3.5 α = 180° Zth(j-c) 3.0 2.5 2.0 1.5 1.0 0.5 Ta(°C) tp(s) 0.0 0 25 50 75 100 125 150 1.0E-01 1.0E-03 Figure 5. Relative variation of gate trigger voltage and current versus junction temperature (typical values) 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 Figure 6. Relative variation of holding current and latching current versus junction temperature (typical values) IGT,VGT[Tj] / IGT,VGT[Tj = 25 °C] IH,IL [Tj] / IH,IL [Tj = 25 °C] 3.0 2.0 2.5 IGT Q3 1.5 2.0 IGT Q1-Q2 1.5 1.0 1.0 IL VGT Q1-Q2-Q3 0.5 0.5 Tj (°C) -50 -25 0 25 50 75 100 125 150 0.0 -50 DS12531 - Rev 3 IH Tj (°C) 0.0 -25 0 25 50 75 100 125 150 page 4/11 T835T-8G Characteristics (curves) Figure 7. Surge peak on-state current versus number of cycles Figure 8. Non repetitive surge peak on-state current for a sinusoidal pulse with width tp < 10 ms ITSM(A) ITSM(A) 1000 70 Tj initial=25°C 60 t=20ms 50 dI/dt limitation: 100A/µs One cy cle Non repetitive Tj initial = 25 °C 40 ITSM 100 30 Repetitive Tc = 128°C 20 10 t p (ms) Number of cycles 0 1 10 10 100 1000 Figure 9. On-state characteristics (maximum values) 0.01 0.10 1.00 10.00 Figure 10. Relative variation of critical rate of decrease of main current versus junction temperature ITM(A) 100 (dl/dt)c [Tj] / (dl/dt)c [Tj = 150 °C] Tj max. Vto = 0.87 V Rd = 80 mΩ Tj = 25 °C 10 Tj = 150 °C VTM(V) 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Tj(°C) 25 Figure 11. Relative variation of static dV/dt immunity versus junction temperature dV/dt [Tj] / dV/dt [Tj = 150 °C] 50 75 100 125 150 Figure 12. Relative variation of leakage current versus junction temperature for different values of blocking voltage IDRM/IRRM [Tj, VDRM/VRRM] / IDRM/IRRM [Tj max.,VDRM/VRRM]* 6 1.0E+00 VD = VR = 402 V 5 4 1.0E-01 *[Tj max = 125 °C; VDRM, VRRM = 800 V] [Tj max = 150 °C; VDRM, VRRM = 600 V] VDRM = VRRM = 800 V 3 VDRM = VRRM = 600 V 2 1.0E-02 1 Tj(°C) 0 25 DS12531 - Rev 3 50 75 100 125 150 1.0E-03 25 Tj(°C) 50 75 100 125 150 page 5/11 T835T-8G Ordering information 2 Ordering information Figure 13. Ordering information scheme T 8 35 T - 8 G TR SnubberlessTM TRIAC T = Triac Current (RMS) / Type 8=8A Gate Current 35 = 35 mA Specific application T = increased (dl/dt) and dV/dt producing reduced ITSM Voltage 8 = 800 V Package G = D²PAK Packing Blank = Tube TR = Tape and reel Table 5. Ordering information Order code T835T-8G-TR T835T-8G DS12531 - Rev 3 Marking Package Weight T835T-8G D²PAK 1.38 g Base qty. Delivery mode 1000 Tape and reel 50 Tube page 6/11 T835T-8G Package information 3 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 3.1 D²PAK package information • • • ECOPACK2® compliant Lead-free package leads finishing Molding compound resin is halogen-free and meets UL standard level V0 Figure 14. D²PAK package outline A E E1 E2 H D D1 L2 c2 2 3 D2 L3 1 b2 b e Max resin gate protrusion: 0.5 mm (1) G A1 A2 A3 L R Gauge Plane V2 c (1) Resin gate is accepted in each of position shown on the drawing, or their symmetrical. DS12531 - Rev 3 page 7/11 T835T-8G D²PAK package information Table 6. D²PAK package mechanical data Dimensions Ref. Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A 4.30 4.60 0.1693 0.1811 A1 2.49 2.69 0.0980 0.1059 A2 0.03 0.23 0.0012 A3 0.25 0.0091 0.0098 b 0.70 0.93 0.0276 0.0366 b2 1.25 1.7 0.0492 0.0669 c 0.45 0.60 0.0177 0.0236 c2 1.21 1.36 0.0476 0.0535 D 8.95 9.35 0.3524 0.3681 D1 7.50 8.00 0.2953 0.3150 D2 1.30 1.70 0.0512 0.0669 e 2.54 0.1 E 10.00 10.28 0.3937 0.4047 E1 8.30 8.70 0.3268 0.3425 E2 6.85 7.25 0.2697 0.2854 G 4.88 5.28 0.1921 0.2079 H 15 15.85 0.5906 0.6240 L 1.78 2.28 0.0701 0.0898 L2 1.27 1.40 0.0500 0.0551 L3 1.40 1.75 0.0551 0.0689 R V2(2) 0.40 0° 0.0157 8° 0° 8° 1. Dimensions in inches are given for reference only 2. Degrees DS12531 - Rev 3 page 8/11 T835T-8G D²PAK package information Figure 15. D²PAK recommended footprint (dimensions are in mm) 16.90 10.30 5.08 1.30 8.90 3.70 Figure 16. D²PAK stencil definitions(dimensions are in mm) DS12531 - Rev 3 page 9/11 T835T-8G Revision history Table 7. Document revision history DS12531 - Rev 3 Date Version Changes 30-Mar-2018 1 Initial release. 6-Jun-2018 2 Updated cover page description. 17-Jul-2018 3 Updated Table 2. Electrical characteristics (Tj = 25 °C, unless otherwise specified). page 10/11 T835T-8G IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS12531 - Rev 3 page 11/11