TDA7529TR

TDA7529 RF front-end for AM/FM DSP car-radio with IF sampling Features ■ Fully integrated VCO for world tuning ■ High performance PLL for fast RDS system ■ I/Q mixer for FM IF 10.7 MHz with image rejection and integrated LNA ■ I/Q mixer for AM IF 10.7 MHz up conversion with high dynamic range ■ Integrated balun, which allows saving of external mixer tank ■ RF AGC, IF AGC, DAGC ■ Low noise IF amplifier with switched wide dynamic AGC range Description ■ IF switch for FM / AM / IBOC ■ Electronic alignment for the preselection stages ■ I2C/SPI controlled ■ Single 5 V supply ■ Alternative frequency control signals to DSP The front-end is a high performance tuner circuit for AM/FM - DSP car-radios with 10.7 MHz IF sampling. It contains mixer and IF amplifiers for AM and FM, fully integrated VCO and PLL synthesizer on a single chip. Use of BiCMOS technology allows the implementation of several tuning functions and a minimum of external components. Table 1. ) s ( ct Device summary Order code TDA7529 r P e u d o TDA7529TR LQFP64 e t le c u d ) s t( o r P o s b O Package Packing LQFP64 exposed pad (10x10x1.4) Tray LQFP64 exposed pad (10x10x1.4) Tape and reel t e l o s b O December 2009 Doc ID 13311 Rev 3 1/60 www.st.com 1 Contents TDA7529 Contents 1 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 3.1 IMR mixer and active balun output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 FM RF-AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 AM RF-AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 IF AGC and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 FREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . 16 3.11 AFSAMPLE/AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12 Serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 c u d e t le ) s t( o r P o s b O - Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ) s ( ct 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 r P e 4.4 4.5 t e l o 4.7 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.9 Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.10 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 Phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . 25 4.12 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.13 D/A-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 bs 2/60 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 O u d o IF - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 13311 Rev 3 TDA7529 5 Contents 4.14 A/D-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.15 GPIO – general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . 27 4.16 AFSAMPLE / AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.17 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Tuning state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 6 Tuning state machine modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.1 Mode 000: buffer (nil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.2 Mode 001: preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1.3 Mode 010: search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.4 Mode 011: AF update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1.5 Mode 100: jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ) s t( 5.2 Mode 100: check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Mode 110: load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 Mode 111: end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 Register SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 State machine start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 c u d e t le o r P Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 6.1.1 Short_reg (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 ADCctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.3 GPIO mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1.4 AGC and mixer control (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 r P e 6.1.6 6.1.7 t e l o ) s ( ct u d o 6.1.5 s b O o s b O - Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Divider R (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 IF AGC control (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.8 FM AGC (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.9 AGC voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.10 Mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.11 Mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.12 PLL control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.13 PLL control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.14 PLL test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.15 Misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.16 Wait lock (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Doc ID 13311 Rev 3 3/60 Contents TDA7529 6.1.17 AGC time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.18 AMAGC control (17 / 33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.19 GPIO output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.20 IF control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.21 AF state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.22 PLL main divider (N-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.23 PLL main divider (N-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.24 PLL main divider (N-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.25 PLL Divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.26 VCO divider (V-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.27 Charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.28 Tuning DAC 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.29 Tuning DAC 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.30 Different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.31 Misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.32 Analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.33 AD converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.34 Read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.35 Read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 c u d e t le ) s t( o r P o s b O - 7 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ) s ( ct u d o r P e t e l o s b O 4/60 Doc ID 13311 Rev 3 TDA7529 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 IF AGC and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching frequency as a function of the process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Supports data communication using the SPI and the I2C protocol . . . . . . . . . . . . . . . . . . . 17 I2C addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 IF - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Phase frequency detector and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 D/A-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 A/D-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 GPIO - general purpose IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AFSAMPLE / AFHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Values of the programmable wait times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Short_reg (0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ADCctrl (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 GPIO mode (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AGC and mixer control (3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Register (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Divider R (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 IF AGC control (6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FM AGC (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AGC voltage threshold (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mixer alignment 1 (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mixer alignment 2 (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PLL control 1 (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL control 2 (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PLL test (13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Misc 2 (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Wait lock (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AGC time constant settings (16 / 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 AMAGC control (17 / 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 GPIO output level control (18 / 34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 IF control (19 / 35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AF state machine wait time 1 (20 / 36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 1 (21 / 37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PLL main divider (N-divider) 2 (22 / 38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e s b O t e l o Doc ID 13311 Rev 3 5/60 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. TDA7529 PLL main divider (N-divider) 3 (23 / 39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL Divider ratio calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VCO divider (V-divider) (24 / 40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Charge pump current (25 / 41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tuning DAC 1 (26 / 42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Tuning DAC 2 (27 / 43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Different controls (28 / 44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Misc 3 (29 / 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Analog test select (30 / 46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AD converter test (31 / 47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Read 1 (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Read 2 (49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 c u d e t le ) s ( ct o s b O - u d o r P e t e l o s b O 6/60 Doc ID 13311 Rev 3 o r P ) s t( TDA7529 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Positive current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Positive/negative current diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voltage and current mode with hand-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C (sub address mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Preset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Search timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AF update timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Jump timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Check timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Load timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 End timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Buffer/control serial bus sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LQFP64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions . 58 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Doc ID 13311 Rev 3 7/60 Functional block diagram 1 TDA7529 Functional block diagram Figure 1. Functional block diagram IBOC FM DAGC AM 2 AGC AGC 2 FM WX 2 I Q AF update Bus Interface AGC TV1 2 c u d TV2 Supply AM I Q DIV :N PLL VCO e t le so ) s ( ct b O - u d o r P e t e l o s b O 8/60 IF 10.7MHz MSB/LSB Doc ID 13311 Rev 3 o r P AFHOLD AFSAMPLE ) s t( I2C SPI DIV 2 Fref AC00038 TDA7529 Pin description TCIF2 IFdec IFin4 VCCIF IFin3 IFin2 BIASD1 GP2 IFin2 GP5 GNDRF2 TCAM TCFM VCCRF2 Pin connection Balunout2 Figure 2. Balunout1 2 Pin description 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 BALUN1 1 48 GNDIF BALUNdec 2 47 TCIF1 DAC2 3 46 IFout1 DAC1 4 45 IFout2 FMMIX1in 5 44 BIASD2 FMMIX1dec 6 43 VDDdec FMAGC2/GP7 7 42 VCCBUS FMAGC1 8 41 MISO FMMIX2in 9 40 MOSI FMMIX2dec 10 39 CLK GNDRF1 11 AMAGC1 12 AMMIXdec 13 AMMIXin 14 MIXbiasdec 15 IFAGC1 16 e t le Pr uc od so b O - ) s t( 38 CS/AS 37 PS 36 BUSGND 35 VCCRO 34 XTALO 33 XTALI Table 2. t e l o O bs GP1 GNDRO VCCPLL GNDPLL LFHC LFLC GNDVCO Vtune Pin Name Description 1 BALUN1 2 BALUNdec 3 DAC2 Tuning DAC 2 output 4 DAC1 Tuning DAC 1 output 5 FMMIX1in 6 FMMIX1dec 7 VCOdec2 VCOdec1 u d o AC00039 Pin assignment r P e Pin # VCCRF1 ) s ( ct AFSAMPLE AFHOLD AMAGC2/GP8 IFAG2 GP4/VDS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Active balun input 1 Active balun input 2 (de coupling) FM mixer input – high gain stage = mode 1 FM mixer de couple FMAGC2/GP7 FM AGC voltage output / alternative GP7 output 8 FMAGC1 FM PIN diode driver output 9 FMMIX2in FM Mixer input – low gain stage = mode2 Doc ID 13311 Rev 3 9/60 Pin description TDA7529 Table 2. Pin assignment (continued) Pin # Pin Name 10 FMMIX2dec 11 GNDRF1 GND RF1 section 12 AMAGC1 AMAGC PIN diode driver output 13 AMMIXdec 14 AMMIXin 15 MIXbiasdec 16 IFAGC1 IFAMP gain control via IFAGC - LSB 17 IFAGC2 IFAMP gain control via IFAGC - MSB 18 GP4/VDS GPIO 4 / VDS input 19 AMAGC2 / GP8 AMAGC voltage output / alternative GP8 output 20 AFHOLD 21 AFSAMPLE 22 VCCRF1 Supply RF1 section 23 VCOdec1 BIAS de couple for VCO 24 Vtune 25 VCOdec2 BIAS de couple for VCO 26 GNDVCO VCO Ground 27 LFLC Loop filter low current output 28 LFHC Loop filter high current output 29 GNDPLL 30 VCCPLL 31 GP1 32 10/60 AM mixer input Mixer bias de coupling AF state machine hold output c u d AF state machine sample output VCO tuning voltage e t le o s b O - PLL Ground ) s ( ct Supply PLL GPIO 1 Ground PLL digital part Reference oscillator input XTALO Reference oscillator output 35 VCCRO Supply PLL digital part 36 BUSGND BUSinterface Ground 37 PS 38 CS/AS 39 CLK 40 MOSI SPIdata input / I2C Data 41 MISO SPI Data Output 42 VCCBUS Supply of BUSinterface 43 VDDdec De couple of internal 3.3V (=3,3V + Vbe) t e l o O AM mixer de couple XTALI 34 bs FM Mixer de couple u d o GNDRO r P e 33 Description Protocol Select Chip select / Address select SPI / I2C clodk Doc ID 13311 Rev 3 o r P ) s t( TDA7529 Pin description Table 2. Pin assignment (continued) Pin # Pin Name Description 44 BIASD2 De coupling for Biasing 45 IFout2 Differential IF output 2 46 IFout1 Differential IF output 1 47 TCIF1 time constant IF AGC for AM 48 GNDIF ground IF section 49 TCIF2 time constant IF AGC for FM 50 IFdec De couple of IF amplifier 51 IFin4 IF input 4 52 VCCIF 53 IFin3 54 BIASD1 55 IFin2 IF input 2 56 GP2 GPIO 2 57 IFin1 IF input 1 58 GP5 GPIO 5 59 GNDRF2 60 TCAM AM AGC time constant 61 TCFM FM AGC time constant 62 VCCRF2 Supply voltage RF2 section 63 Balunout1 Active balun output 2 = FM output 64 Balunout2 Supply IF section IF input 3 De coupling for Biasing c u d GND RF2 section = active balun GND ) s ( ct e t le ) s t( o r P o s b O - Active balun output 1 = AM output u d o r P e t e l o s b O Doc ID 13311 Rev 3 11/60 Function description TDA7529 3 Function description 3.1 IMR mixer and active balun output The IMR mixer has two FM inputs (referred as mode 1 / mode 2) and one AM input selectable by software. The FM inputs differ by their gains, noise figures, IIP3 and maximum signal handling capability. The mode 1 FM input (with the higher gain, lower IIP3 and lower noise figure) is normally coupled with passive antenna input stages; the mode 2 FM input is normally used for input stages featuring an external preamplifier. There are two single ended outputs of the IMR mixer: Balunout1 has a 4 dB higher gain than Balunout2. It is not recommended to use both outputs in parallel. The Balun1 pin is the current mixer output over an internal resistor. The LC filter at Balun1 can be realized with a low cost SMD-coil (Q ~ 4). 3.2 FM RF-AGC ) s t( The FM AGC system is controlled by a peak detector, whose gain can be varied by the keyed AGC. The latter function is meant to be controlled by a D/A converter in the back-end part of the system. c u d o r P The time constant of the FM RF-AGC is defined by an external capacitor connected to TCFM and programmable internal currents. The currents can be selected independently for AGC attack and decay. By this the ratio between the attack and the decay time can be programmed between 0.4 and 250. e t le o s b O - The FM RF-AGC has two output pins to drive one PIN diode attenuator and the external preamplifier gain control. The AGC outputs can be programmed to the following modes: 1. Positive current I=f(e): after reaching the AGC threshold voltage, the current output delivers a current I=f(e) up to 15mA in a voltage range from 0.1V (@10µA sink current) up to VCC-1.2V with a quasi-exponential characteristic referred to the voltage at TCFM. Figure 3. u d o Positive current diagram r P e t e l o ) s ( ct Iout 15mA f(e) current s b O V_TCFM 2. 12/60 AC00040 Pos/neg current I = f(e): below the AGC threshold voltage the AGC output sinks a constant current of -5 mA. When the RF input level crosses the AGC threshold voltage, the current is reduced down to 0 mA with a quasi-logarithmic behavior. At half control voltage the current becomes positive and reaches up to 15mA following an exponential function. Doc ID 13311 Rev 3 TDA7529 Function description Figure 4. Positive/negative current diagram Iout 15mA f(e) current 1.65V AC00041 3. Constant current mode: the output current can be set to 2 mA source current. The AGC detector is in power -down mode and only the PIN diode driver is active. 4. Voltage and current mode with hand-over: the Vthr level is programmable with 6 bit in the range of 0.2V to 2.56V. The voltage Vthr is the internal reference voltage of an external cascode transistor emitter feedback loop. Figure 5. Voltage and current mode with hand-over Iout c u d Vout Vthr e t le ) s t( o r P so Vthr AC00042 b O - The voltage output swing is comprised between 0V and 3.3V (VDD). The microcontroller can read the voltage at the AGC capacitor via the serial control interface. ) s ( ct u d o 3.3 AM RF-AGC r P e The AM AGC system is controlled by an average detector. The time constant of the AM RFAGC is defined by an external capacitor connected to TCAM and programmable internal currents with symmetrical attack/decay behavior. s b O t e l o The AM RF-AGC has two output pins to drive one PIN diode attenuator and the external preamplifier gain control. The AGC outputs can be programmed to the same modes as the FM RF-AGC with the exception of pos/neg current. The microcontroller can read the voltage at the AGC capacitor via the serial control interface. Doc ID 13311 Rev 3 13/60 Function description 3.4 TDA7529 IF AGC and IF amplifier The IF AGC system is controlled in AM with an average detector and in FM with a peak detector, and reduces the mixer gain. The time constant is defined by two external capacitors connected to TCIF1 and TCIF2 respectively, and programmable internal currents. The microcontroller can read the voltage at the AGC capacitors via the serial control interface. The IF amplifier gain is not affected by the on-chip IF-AGC but is meant to be controlled by the back-end part of the system through pins IFAGC1 and IFAGC2. The gain is reduced in 6 dB steps starting from the programmed value "G" according to the following table: Table 3. 3.5 IF AGC and IF amplifier IFAGC2 IFAGC1 Gain 0 0 G 0 1 G - 6 dB 1 1 G - 12 dB 1 0 c u d ) s t( G - 18 dB Dividers e t le o r P The mixer divider V is followed by a divide-by-4-stage that generates 0°/90°/-90° LO signals for the IMR mixer (90°/-90° mode to switch between upper or lower side-band suppression in the IMR mixer). The main divider N can be operated in integer mode. 3.6 ) s ( ct D/A converters o s b O - The front-end contains two D/A-converters for tuning the filters of the FM pre-stage. The converters have a resolution of 9 bit. u d o r P e t e l o s b O 14/60 Doc ID 13311 Rev 3 TDA7529 3.7 Function description VCO The 3.7 GHz VCO has an internal switch that allows extending the oscillation frequency range. This is required by the fact that each of the two resulting VCO sub-bands (upper/lower) cannot individually cover the complete required frequency range versus temperature and process; for this reason a calibration procedure is needed to determine the process type (typical, slow, fast) and select the transition frequency between the two VCO sub-bands. To run the procedure the VCO range 2 must be selected, the synthesized frequency needs to be set to 4GHz; then if Vtuning > 2.6V then the process is 'slow', if Vtuning < 1.7V then is 'fast' and otherwise is 'typical'. The switching frequency as a function of the process is reported in the following table: Table 4. 3.8 Switching frequency as a function of the process Slow Typ. Fast 3.635 GHz 3.72 GHz 3.794 GHz c u d FREF ) s t( The reference frequency for the PLL can be derived by a XTAL directly connected to the device or by means of an LVDS signal. In the latter case an external matching resistor must be used to obtain the desired input signal level. 3.9 e t le A/D converter o r P o s b O - The front-end contains a 6 bit SAR A/D-converter for sensing several analog values of the tuner. The following analog sources can be switched to the ADC input by software command: ) s ( ct ● FM RF AGC capacitor voltage ● AM RF AGC capacitor voltage ● IF AGC capacitor voltage (automatically connected to the FM or AM IF AGC filtering capacitor) ● ● t e l o ● s b O ● u d o r P e ● PLL tuning voltage Temperature sensor GPIO 1 voltage GPIO 2 voltage ADC reference generated from VCC. The ADC can be clocked by an integrated RC-oscillator, in which case the oscillation frequency is programmable, or by the PLL reference frequency. Doc ID 13311 Rev 3 15/60 Function description 3.10 TDA7529 GPIO - general purpose IO interface pins The front-end has seven GPIO - general purpose control pins to switch external stages (output), e.g amplifiers, or to read the status of external stages (input), e.g. control voltages. Some control pins are multiplexed with other functions that are not necessary in every tuner design (FM AGC keying, AM cascode control). All the GPIOs may put in tristate or in enable mode. When in enable the GPIOs can be configured as shown in the following table. All GPIOs are short-circuit protected by current limiter and voltage-tolerant up to 3.5 V. Table 5. GPIO - general purpose IO interface pins GPIO ports Function Note GPIO1 Selects function of GPIO1: if input, connects GPIO1 to ADC (ADC must then be configured – AnlgIn to AD to use GPIO1 as input); if output, level depends – DigOut on GPIO Out Lev Ctrl → GPIO1 GPIO2 Selects function of GPIO2: if input, connects GPIO2 to ADC (ADC must then be configured to use GPIO2 as input) and to KAGC (FM KAGC must then be enabled); if output, level depends on GPIO Out Lev Ctr → GPIO2 GPIO4 Selects function of GPIO4: if input, configures GPIO4 as AM Cascode VDS input; if output, level depends on GPIO Out Lev Ctrl → GPIO4 GPIO5 Selects function of GPIO5: if input, it is directly connected to read-only register byte 48 bit 4; if output, level depends on GPIO Out Lev Ctrl → GPIO5. – DigIn When set to input, it is necessary to set IF AMP – Out (Dig or Anlg) → GPIO5 out mode to “ON GPIO5 out En” (labels are wrong). Also used for production testing as analog output (not relevant for application). e t le ) s ( ct t e l o s b O 16/60 c u d o r P – AnlgIn – DigOut o s b O - Selects function of GPIO6 if device is configured in I2C mode: if input, it is directly connected to read-only register byte 48 bit 5; if output, level depends on GPIO Out Lev Ctrl → GPIO5. When the device is configured in SPI mode, program GPIO Out Lev Ctr → GPIO5 to “Low”. The value of GPIO mode → GPIO5 does not matter u d o r P e GPIO6 ) s t( – AnlgIn to AD – Kagc In – DigOut – Din (spi MISO out) – Dout (spi MISO out) GPIO7 Selects function of GPIO7: if digital output is – Digital Out selected, level depends on GPIO Out Lev Ctrl → GPIO7; otherwise, configures GPIO7 as FM – FM agc Vout AGC Vout GPIO8 Selects function of GPIO8: if output, level depends on GPIO Out Lev Ctrl → GPIO8; otherwise, configures GPIO8 as AM AGC Vout Doc ID 13311 Rev 3 – Digital Out – AM agc Vout TDA7529 3.11 Function description AFSAMPLE/AFHOLD On the TDA7529 there are two dedicated open drain pins (AFSAMPLE and AFHOLD), that allow the control of the DSP (mute and quality controls) during AF update. Details are given in Chapter 5. 3.12 Serial bus interface The TDA7529 has a serial data port for communication with the microcontroller. It is used for programming the device and for reading out its detectors. This port supports data communication using the SPI and the I2C protocol. The data transfer of several consecutive bytes is supported by the auto increment feature. Table 6. Supports data communication using the SPI and the I2C protocol SPI signal I2C signal Name Pin Pin Signal 1 PS Protocol Select SPI/I2C PS Protocol Select SPI/I2C Signal 2 CS Chip Select AS Address Select Signal 3 CLK Clock CLK Clock Signal 4 MOSI Master Out – Slave In DATA bidirectional Data Signal 5 MISO Master In – Slave Out GP6 e t le c u d ) s t( o r P General Purpose Out The "PS"- pin (protocol select) determines which communication protocol is used. The information is not latched, so any level change at this pin immediately affects the protocol used by the TDA7529. o s b O - The SPI protocol is selected by setting PS = 0 while, during the I2C operation, PS needs to be open (internally set to 1). SPI-Protocol: CPOL=1, CPHA=1. ) s ( ct The CS pin performs the Chip Select function during the SPI operation; it has to be reset to 0 during transmission or reception, otherwise set to 1 (the CS pin is set to 1 by leaving it open). u d o Both the CS and the AS functions are performed by the CS pin. r P e When the I2C mode is used, the "AS" pin determines which I2C address or group of addresses (see below) is used. Three different external connections are defined to represent three groups of addresses (refer to the following table for details). The information is not latched, so any level change at this pin immediately affects the address used by the TDA7529. s b O t e l o First the IC address is transmitted including the R/W bit for setting the direction of the following data transfer Doc ID 13311 Rev 3 17/60 Function description TDA7529 I2C addresses Table 7. Tuner: Tuner 3 Tuner 2 Tuner 1 level at pin AS 2.2V – 3.5V 1.1V – 1.7V 0.0V – 0.6V address: 1100 1xxd 1100 x1xd 1100 xx1d MSB ... LSB - - - 1100 000d - - - 1100 001d - - R/W 1100 010d - R/W - 1100 011d - W W 1100 100d R/W - - 1100 101d W - W 1100 110d W W - 1100 111d W W W c u d ) s t( x = must be "0" for reading, can be "1" or "0" for writing to the TDA7529 d = determinates the direction of data transfer, reading or writing R/W = indicates the address to read to and/or to write from a single TDA7529 W = indicates those addresses that can be used to transmit equal data to several TDA7529 frontends. A read out has no purpose for these addresses (data collision), but must be possible without damaging the tuner IC. 2 e t le o r P The two serial bus protocols, I C and SPI, are as follows: Figure 6. 1st byte 7 2nd byte 1 address Figure 7. 0 R/W r P e subaddress N 1 0 R/W 1 ) s ( ct u d o SPI 7 SM 1st byte 7 SM o s b O - I2C (sub address mode) subaddress N 0 x 4th byte 0 7 data byte N 0 data byte N+1 AC00043 2nd byte 7 3rd byte 7 3rd byte 0 7 data byte N 4th byte 0 data byte N+1 7 0 data byte N+2 AC00044 t e l o Data auto increment mode is always active regardless of the serial bus mode chosen. s b O 18/60 Doc ID 13311 Rev 3 TDA7529 4 Electrical specifications Electrical specifications Electrical parameters are guaranteed if Fref = 100kHz, with frequency stability of +/- 20ppm max. 4.1 Absolute maximum ratings Table 8. Absolute maximum ratings Symbol Parameter Test condition Min Typ Max Units VCC Abs. supply voltage - - - 5.5 V Tamb Ambient temperature range - -40 - 105 °C Tstg Storage temperature - -55 - 150 °C Tj Junction temperature - - - 150 °C 4.2 Thermal data Table 9. Thermal data Symbol Rthj-amb c u d Parameter Test condition, comments Min Typ Max Units - - 33 °C/W Test Condition, Comments Min Typ Max Units e t le 2s2p std Jedec board with thermal via underneath the Thermal resistance junction to component (36 board via: ambient diameter = 0.5mm / pitch = 1.5mm), max 30% missing soldering so ) s ( ct b O - 4.3 General key parameters Table 10. General key parameters u d o r P e Symbol Parameter o r P ) s t( VCC 5V supply voltage - 4.7 5 5.35 V ICC Supply current @ 5V - - 145 175 mA Supply current @ 5V in power down mode - 9 14 mA -40 - 105 °C t e l o s b O ICC_pwd Tamb Ambient temperature range - Doc ID 13311 Rev 3 19/60 Electrical specifications 4.4 TDA7529 FM - section Refer to application circuit in figure 3. VCC = 4.7V to 5.35V; Tamb = -40 to +105°C; fc = 76 to 108 MHz; 60dBµV antenna level; mono signal, unless otherwise specified. Antenna level equivalence: 0dBµV = 1µVrms, all RF levels are intended as PD. Table 11. FM - section Symbol Parameter Test condition, comments Min Typ Max mode 1 (unloaded) 20 22 24 mode 2 (unloaded) 14 16 18 Units FM IMR Mixer and active balun Gmix1 Mixer conversion gain - Gain attenuation range controlled by IF-AGC 18 20 - mode 1 30 50 - mode 2 5 6.5 9.5 Rin Input impedance Rout Output impedance active balun 15 20 30 Vout_max Max. output voltage without clipping (unloaded) - vnoise IIP3 Input noise voltage 3rd order intercept point(1) 122 - Mode1, Rsource=1.5kΩ, noiseless - 3 Mode 2, Rsource=800, noiseless - 5 mode 1 up to Vin/tone = 90 dBµV mode 2 up to Vin/tone = 98 dBµV e t le o r P dB kΩ Ω ) s t( dBµV nV/√Hz 6 125 - dBµV - - dBµV 30 - - with gain/phase adjust 40 45 - mode 1, min. setting 82 85 88 mode 1, max setting 97 100 103 mode 2, min. setting 90 93 96 mode 2, max setting 105 108 111 Threshold steps 4 bit control 0.5 1 1.5 dB Pin diode source current AGC control pin 1 Logarithmic current 10 - - mA - Pin diode sink current AGC control pin 1 Logarithmic current - - -3 mA - Pin diode source current in constant current mode - 1 2 - mA - Threshold shift keyed AGC Control input = 1V 10.5 12.5 13.5 dB/V IIP2 2nd order intercept point IRR Image rejection ratio Lthr without gain/phase adjust ) s ( ct r P e t e l o - u d o Mixer input referred RF level threshold s b O o s b O - mode 1 mode 2 FM RF AGC 1. parameter guaranteed by correlation. 20/60 123 c u d 3.7 dB Doc ID 13311 Rev 3 132 134 144 152 dB dBµV TDA7529 4.5 Electrical specifications AM - section Refer to application circuit in figure 3. VCC = 4.7V to 5.35V; Tamb = -40 to +105°C; LW, MW and SW bands; 74dBµV antenna level, unless otherwise specified. Antenna level equivalence: 0dBµV = 1µVrms, all RF levels are intended as EMF. Table 12. AM - section Symbol Parameter Test condition, comments Min Typ Max Units AM IMR Mixer and active balun Gmix1 Mixer conversion gain - 7.2 9 10.5 dB Δgmix1 Gain attenuation range controlled by IF-AGC 18 20 - dB Input impedance - 5 6.5 9.5 kΩ Rout Output impedance - 15 20 30 Ω - Min. external load - 400 - - Ω Vin_max Max. output voltage without clipping (unloaded) 122 - - Vnoise Input noise voltage - - 6 8.3 IIP3 3rd order intercept point - 130 134 IIP2 2nd - 159 IRR Image rejection ratio without gain/phase adjust 30 IRR Image rejection ratio with gain/phase adjust Rin order intercept point AM RF AGC e t le o s b O - 40 c u d o r P - - ) s t( dBµV nV/√Hz dBµV - dBµV - - dB 45 - dB External capacitance for time constant from 1nF to 4700nF – time constant values are directly proportional to the external capacitor value 83 86 89 max setting 98 101 104 4 bit control 0.5 1 1.5 dB AGC control pin 1 Logarithmic current 10 - - mA AGC control pin 1 with 5µA sink current - - 0.1 V Isink 5µA sink current 5 10 - µA Pin diode source current in constant current mode - 1 - - mA - Max. voltage AGC control pin 1 VCC1.4 VCC-1.2 - V - Max. output voltage in GPO mode AGC control pin 2 VDD0.3 - VDD V - Min. output voltage AGC control pin 2 - - 0.3 V Lthr - threshold steps - Pin diode source current - Min. voltage o r P e ) s ( ct du t e l o - min. setting Mixer input referred RF level threshold s b O Doc ID 13311 Rev 3 dBµV 21/60 Electrical specifications Table 12. TDA7529 AM - section (continued) Symbol Test condition, comments Min Typ Max Units Fast attack time constant active in case of overdrive (more than 7dB) 0.05 0.5 5 ms Time constant Range, mode T1 Range, mode T2 Range, mode T3 - 0.5-50 2.5-250 12.5-1250 - ms ms ms Min Typ Max Units Input 1-3 (FM,HD,AM), min. 23 25 27 Input 1-3 (FM,HD,AM), max 36 38 40 Input 4 (HD-Radio AM), min. 15 17 Input 4 (HD-Radio AM), max 29 Gain step 3 bit control 1.5 AGC range - AGC steps 2-bit control Rin_input1 Input impedance input 1 FM –input @ 10.7MHz Rin_input2 Input impedance input 2 HD-Radio FM input @ 10.7MHz Rin_input3 Input impedance input 3 Rin_input4 Input impedance input 4 - - Parameter 4.6 IF - section Table 13. IF - section Symbol Parameter Test condition, comments IF AMPLIFIER Grange Gstep ΔAGC Rout Vout_max r P e Max. output voltage dB od 2 2.5 dB 18 19 dB 5.2 6 6.6 230 330 450 Ω 2.2 2.9 3.6 kΩ AM input @ 10.7MHz 7 8.2 10 kΩ HD-Radio AM input @ 10.7MHz 7 8.7 11 kΩ - - 15 - Ω - 115 - 117 dBµV e t le 16.5 ) s ( ct u d o Differential output impedance 19 so b O - Pr 31 33 Gain variation in loaded conditions 10pF between each IFAMP outputs and GND, 10kΩ differential load - - 0.5 dB IIP3,load IIP3 decrease in loaded conditions 10pF between each IFAMP outputs and GND, 10kΩ differential load - - 1 dB 3rd order intercept point input stage 1-3, @ 25dB gain 119 122 - IIP3 input stage 4, @ 17dB gain 130 133 - input stage 1-3 142 - - input stage 4 154 - - t e l o Gain, load bs O uc Gain range ) s t( IIP2 22/60 2nd order intercept point dBµV dBµV Doc ID 13311 Rev 3 TDA7529 Table 13. Electrical specifications IF - section (continued) Symbol Parameter Test condition, comments Min Typ Max Units Vnoise_input 1 IN1 input noise voltage @ source impedance 330Ω · noiseless, @31dB gain - 3.5 4.2 nV/√Hz Vnoise_input 2 IN2 input noise voltage @ source impedance 470Ω · noiseless, @ 31dB gain, with external 560Ω input termination resistor - 3.8 4.6 nV/√Hz Vnoise_input 3 IN3 input noise voltage @ source impedance 2.2kΩ · noiseless, @ 29dB gain, with external 2.7kΩ input termination resistor - 5 6.5 nV/√Hz Vnoise_input 4 IN4 input noise voltage @ source impedance 2.2kΩ · noiseless, @ 24dB gain, with external 2.7kΩ input termination resistor - 7 8.5 nV/√Hz IF AGC ) s t( External capacitance for time constant from 10nF to 500nF in FM (asym. mode), from 100nF to 4700nF in AM (sym. mode) – time constant values are directly proportional to the external capacitor value Lthr FM, min. setting 88.5 FM, max setting 99.5 IFAmp input referred e t le AM, min. setting 86.5 o r P 101 93.5 103.5 dBµV 91.5 96.5 99 101.5 1 1.5 2 dB 0.05 0.5 5 ms FM: asym. mode U1 FM: asym. mode U2 AM: sym. mode S1 AM: sym. mode S2 - 10-500 0.05-2.5 2.0-100 20-1000 - µs ms ms ms FM: asym. mode U1 / U2 AM: sym. mode S1 AM: sym. mode S2 - 2-100 2-100 20-1000 - ms ms ms so - Threshold steps - - Fast attack mode in AMmode, range active in case of overdrive - Time constant attack, range - Time constant decay, range r P e c u d 89 AM, max setting ) s ( ct u d o 91 b O - t e l o s b O Doc ID 13311 Rev 3 23/60 Electrical specifications 4.7 VCO Table 14. VCO Symbol - TDA7529 Parameter Test condition, comments Min Typ Frequency range VCO ±8% tuning range 3430 - Phase Noise of LO Free running VCO; values referred @ 100MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz -46 -76 -103 -40 -60 -86 -106 - Deviation error FM reception, de-emphasis 50µs, fNF=20Hz...20kHz @ min. VCO frequency - 8 4.8 Reference frequency input buffer Table 15. Reference frequency input buffer Symbol Parameter Test condition, comments Hz ) s t( Max Units 925 - - mV 200 - 400 mV 150 - - kΩ 10 - - kΩ 200 - 1000 mVPP Min Typ Max Units 5 - 131 - phase calibration in IMR -0.5 - 0.5 DEG 21bit (32/33 pre scaler) 992 - 2097151 - 1 - 255 - Min. input voltage low - - Input differential voltage - - Input impedance (xtal mode) - - Input impedance (lvds mode) - - Input voltage range so ) s ( ct b O - Single ended mode u d o r P e t e l o - mV - Symbol dBc/Hz 1475 - Dividers - - Max input voltage high Table 16. MHz - - Dividers 4010 P e let Reference frequency input buffer mode 4.9 Typ Units c u d ro Min Max Parameter Test condition, comments Mixer divider V – integer values s b O NV divider value divider_V 7 bit Divide by 4 – generation of 0°/90°/-90° LO signal for IMR - I/Q phase error of divider Main divider N – integer divider NN divider value divider_N Reference divider R – integer values NR 24/60 divider value divider_R 8 bit Doc ID 13311 Rev 3 TDA7529 Electrical specifications 4.10 Phase locked loop Table 17. Phase Locked Loop Symbol Parameter Test Condition, Comments - Settling time AM/FM Δf < 0,01% @ fPFD = 100 kHz - Spurious suppression @ divided VCO signal Min Typ Max Units - 800 1200 µs 70 - - dB Min Typ Max Units 2 - 3000 -0.4 -0.8 -1.7 -3.1 -40 -80 -160 -320 -640 -0.65 -1.3 -2.4 -4.5 -60 -120 -240 -480 -960 4.11 Phase frequency detector and charge pump Table 18. Phase frequency detector and charge pump Symbol Parameter Test Condition, Comments PFD fPFD PFD input frequency - c u d Charge pump - high current mode bit1 high current mode bit2 high current mode bit3 high current mode bit4 low current mode bit5 low current mode bit6 low current mode bit7 low current mode bit8 low current mode bit9 - Sink current Source current u d o r P e t e l o ) s ( ct o s b O - e t le high current mode bit1 high current mode bit2 high current mode bit3 high current mode bit4 low current mode bit5 low current mode bit6 low current mode bit7 low current mode bit8 low current mode bit9 0.4 0.8 1.7 3.1 40 80 160 320 640 o r P 0.65 1.3 2.4 4.5 60 120 240 480 960 ) s t( kHz -0.9 -1.7 -3.1 -5.8 -80 -160 -320 -640 -1280 mA mA mA mA µA µA µA µA µA 0.9 1.7 3.1 5.8 80 160 320 640 1280 mA mA mA mA µA µA µA µA µA s b O Doc ID 13311 Rev 3 25/60 Electrical specifications TDA7529 4.12 Temperature sensor Table 19. Temperature sensor Symbol Parameter Test condition, comments Min Units 150 °C Temperature range - - Resolution °C/LSB (no direct measurement possible) - 5 - °C - Absolute error - - - 15 °C - Relative error - - 0.5 - LSB Min Typ Max 0.5 0.6 0.8 VCC – 0.2 VCC – 0.1 - 2 - kΩ - - µA 9 9.5 mV -2 - 2 LSB b O - -0.5 - 0.5 LSB - 20 40 µs 20 - - dB Test condition, comments Min Typ Max Units D/A-converter Table 20. D/A-converter Symbol Parameter -40 Max - 4.13 Test condition, comments Output voltage minimum value Unloaded output Vout Output voltage maximum value Unloaded output - Output impedance - - - Max. output current - 500 - Average Voltage step resolution 9bit - INL - - DNL - - Conversion time @ CL=1nF VSRR Supply voltage ripple rejection ratio (s) t c 4.14 A/D-converteru d o r P e t e l o s b O Table 21. e t le 8.5 so o r P c u d ) s t( Units V V A/D-converter Symbol Parameter - INL - -2 - 2 LSB - DNL - -0.5 - 0.5 LSB - Input voltage range - 0 - VDD V Conversion time - - - 7 µs tADC 26/60 Typ Doc ID 13311 Rev 3 TDA7529 Electrical specifications 4.15 GPIO – general purpose IO interface pins Table 22. GPIO - general purpose IO interface pins GPIO functionality GPIO-Output Pin name High level Voltage Multiplexed functionality details are given in the corresponding chapters GPIO-Input Low level Functionality Source Sink Voltage current current Voltage GP1 3.3V 1 mA 0V 1 mA Analog input ADC 0 ... 3.3V GP2 3.3V 1 mA 0V 1 mA Analog input ADC 0 ... 3.3V FM key AGC input GP4 3.3V 0.1 mA 0V 10 mA AM cascode VDS input 0 ... 3.3V GP5 3.3V 1 mA 0V 1 mA Digital Input 0 / 3.3V 0 / 3.3V GP6 3.3V 1 mA 0V 1 mA Digital Input GP7 3.3V 1 mA 0V 1 mA - - FM-AGC voltage output GP8 3.3V 1 mA 0V 1 mA - - AM-AGC voltage output Symbol Parameter Test Condition V V 0.5 1 - mA 0.08 0.1 - mA GP1 / GP2 / GP5 / GP6: @ 1kΩ load to VDD 0.8 1 GP4: @ 100Ω load to VDD 8.0 10 digital input mode 100 - - kΩ 0 - 3.5 V GP5 / GP6 used as digital input 2.2 - 3.5 V GP5 / GP6 used as digital input -0.05 - 1.0 V Min Typ Max Units - - 3.6 V 800 - - μA @ 100kΩ load to VDD - High level source current GP1 / GP2 / GP5 / GP6: @ 1kΩ load to GND - High level source current GP4 @ 1kΩ load to GND - low level sink current - low level sink current - Input impedance - Input voltage range - High level input voltage s b O P e let so (t s) b O - - GP1 / GP2 t e l o - 4.16 r P e Low level input voltage ro - Units - @ 100kΩ load to GND Low level output voltage VDD-0.3 Max 0.3 High level output voltage - od c u d Typ ) s t( - - uc Min SPI MISO output - mA mA AFSAMPLE / AFHOLD Table 23. AFSAMPLE / AFHOLD Symbol Parameter Test Condition, Comments - Output voltage at AFSAMPLE/AFHOLD - - Maximum sink current Vo = 0.4V Doc ID 13311 Rev 3 27/60 Electrical specifications TDA7529 4.17 Serial data interface Table 24. Serial data interface Symbol VDD Parameter Test condition, comments Typ Max Units 2.7 - 3.5 V Supply voltage - Clock frequency Guaranteed range @ SPI Guaranteed range @ I2C 4 1 - - MHz MHz - Power On Delay time Ready for communication after Power-On-Reset - - 10 ms - High level output voltage Output signals VDD-0.3 - VDD V - Low level output voltage Output signals -0.05 - 0.3 V - High level source current Output signals 0.08 0.1 - mA - low level sink current Output signals 0.8 1 - mA - Rise / fall time Output signals, 90% 15 25 40 - High level input voltage Input signals, except AS 2.3 - 3.5 - Low level input voltage Input signals, except AS -0.05 - - High level input voltage AS input signal 2.2 - Medium level input voltage AS input signal 1.1 - Low level input voltage AS input signal - Input impedance Input signals - Power-On impedance All signals fclk b O - Rise / fall time ) s ( ct - u d o Input signal CLK, min. acceptable duration range, 90% r P e t e l o s b O Doc ID 13311 Rev 3 V - 3.5 V - 1.7 V - 0.6 V 100 - - kΩ 100 - - kΩ 0.01 - 1000 µs 0.01 - 10 µs e t le so 1.0 ) s t( ns uc -0.05 Input signals except CLK, min. acceptable duration range, 90% - 28/60 Min Pr od V TDA7529 5 Tuning state machine Tuning state machine Frequency changes in a system employing the TDA7529 can be efficiently performed using a built-in state machine which simplifies the microprocessor supervisory functions. The state machine, which can work in 8 different modes, can be invoked by a simple WRITE operation into the tuner registers and, provided that the frequency to be jumped to has been preloaded into the front-end registers through a previous separate or is loaded through a concurrent WRITE operation, the FE jump sequence is automatically managed and flags are provided to the back-end to indicate the current condition. 5.1 Tuning state machine modes Hereafter the description of the 8 modes can be found. They are chosen by Byte 12 bits. The diagrams depicting the FE and flag conditions for each of the 8 modes are as follows: 5.1.1 Mode 000: buffer (nil) c u d When this mode is selected, no action is undertaken by the state machine. 5.1.2 Mode 001: preset Figure 8. e t le Preset timing diagram bus STOP event EVENTS TIME ) s ( ct AFHOLD u d o B.E. OPERATION o s b O - wait T1ms transmission with subaddr. bit 7 = 1 AFSAMPLE regs swap wait for Tplllock mute audio r P e wait 50 us ) s t( o r P wait T60ms quality dets in fast mode unmute audio AC00045 This mode is used to jump to a different frequency and stay there, with reception at the end of the sequence. s b O t e l o AFSAMPLE can be used to tell the back-end when to mute and to unmute the audio output. The 60 ms mute time (programmable) after the PLL has reached the locked condition can be used to check the RDS signal presence and content in addition to the analog quality information. AFHOLD can be used to tell the back-end to switch to faster time constants for quick quality acquisition. Doc ID 13311 Rev 3 29/60 Tuning state machine 5.1.3 TDA7529 Mode 010: search Figure 9. Search timing diagram bus STOP event EVENTS TIME transmission with subaddr. bit 7 = 1 regs swap wait T1ms wait for Tplllock wait 50 us AFSAMPLE AFHOLD B.E. OPERATION mute audio quality dets in fast mode AC00046 This mode is used to jump to a different frequency and stay there, with audio muted. AFSAMPLE can be used to tell the back-end when to mute the audio output. ) s t( AFHOLD can be used to tell the back-end to switch to faster time constants for quick quality acquisition. 5.1.4 c u d Mode 011: AF update e t le Figure 10. AF update timing diagram bus STOP event EVENTS TIME regs swap transmission with subaddr. bit 7 = 1 AFSAMPLE ) s ( ct AFHOLD B.E. OPERATION regs swap o s b O - mute audio u d o o r P hold unmute audio freeze AF qual AC00047 r P e This mode is used to jump to an AF frequency, check its quality, jump back to the starting frequency and continue reception. t e l o AFSAMPLE can be used to tell the back-end when to acquire the AF frequency quality. bs O 30/60 AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. Doc ID 13311 Rev 3 TDA7529 5.1.5 Tuning state machine Mode 100: jump Figure 11. Jump timing diagram bus STOP event EVENTS TIME transmission with subaddr. bit 7 = 1 regs swap wait T1ms wait for Tplllock mute audio hold wait T0.5ms wait 50 us AFSAMPLE AFHOLD B.E. OPERATION unmute audio AC00048 This mode is used to jump to a different frequency and stay there, with reception at the end of the sequence. ) s t( AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. c u d AFSAMPLE can be used to tell the back-end when the quality signal processing can be restarted, with a stable situation to start from. 5.2 e t le Mode 100: check o s b O - Figure 12. Check timing diagram EVENTS TIME ) s ( ct o r P bus STOP event transmission with subaddr. bit 7 = 1 regs swap wait T1ms wait for Tplllock u d o AFSAMPLE r P e s b O t e l o AFHOLD B.E. OPERATION mute audio hold AC00049 This mode is used to jump to a different frequency and stay there, with audio muted. AFHOLD can be used to tell the back-end to mute/unmute the audio and keep normal processing on hold. AFSAMPLE can be used to tell the back-end when to freeze the quality signal processing. Doc ID 13311 Rev 3 31/60 Tuning state machine 5.3 TDA7529 Mode 110: load Figure 13. Load timing diagram bus STOP event EVENTS TIME transmission with subaddr. bit 7 = 1 regs swap AC00050 The content of the buffer and control registers is swapped. No transition occurs on the AFHOLD and AFSAMPLE lines. 5.4 Mode 111: end Figure 14. End timing diagram c u d bus STOP event EVENTS TIME e t le transmission with subaddr. bit 7 = 1 AFSAMPLE AFHOLD ) s ( ct B.E. OPERATION o s b O - wait 50 us ) s t( o r P unmute audio AC00051 u d o This mode is used to end sequences that terminate with muted audio, after the decision on whether to stay to that frequency or jump to a different one has been taken. r P e AFHOLD can be used to tell the back-end to unmute the audio. t e l o AFSAMPLE can be used to tell the back-end to restore normal quality signal processing. Most of the wait times of the algorithm can actually be programmed. bs O 32/60 The following table summarizes the minimum, maximum and default values of the programmable wait times. The indicated values are valid only for the advised configuration where the phase detector reference frequency is 100 kHz. Doc ID 13311 Rev 3 TDA7529 Tuning state machine Table 25. Values of the programmable wait times PARAMETER NAME Tplllock REGISTER Byte 15 bits Byte 30 bits T0.5ms Byte 20 bits T1ms Byte 29 bits T2ms T60ms Byte 04 bits VALUE TIME min. 00000 20 us default 00110 1 ms maximum 11111 5 ms min. 000000 70 us default 000101 0.5 ms maximum 111111 5 ms min. 000000 10 us default 001100 1 ms maximum 111111 5 ms min. 000000 50 us default 011000 maximum 111111 min. 00000 default 10111 maximum 5.5 e t le Register SWAP Pr uc od 11111 ) s t( 2 ms 5 ms 1 ms 60 ms 80 ms o s b O - Some of these modes contain one or two register "swap" operation(s). The changes within the register structure during a swap operation depend on the operating mode of the chip. If the chip is programmed in the "buffer/control" mode (chosen by setting byte 12 bit 7 = 1), which is necessary to take advantage of the tuning state machine, it is suggested that the microprocessor write data only in the normal register bank (bytes from 16 to 31), because the state machine itself takes care of exchanging the content of the normal register bank with that of the shadow bank (bytes from 32 to 47) during a swap. The normal registers are intended to be written to by the radio microprocessor, whereas the registers that actually control the device circuits are the shadow ones. ) s ( ct u d o r P e In any case it is suggested that the bits 5 and 4 of byte 0, that define which control bank is actually used to drive the device circuits, should not be touched after setting them to 0 after reset because they are automatically updated by the tuning state machine. t e l o s b O Doc ID 13311 Rev 3 33/60 Tuning state machine 5.6 TDA7529 State machine start The tuning state machine is activated only at the end of the transmission if bit 7 of the subaddress is 1. The activation sequence, therefore, is to be done in the following way. Figure 15. Buffer/control serial bus sequence START ADDRESS (if I2C) SUBADDRESS REGS 0:31 STOP bit 7 = 1 REG 12 bit 6:4 sets desired state machine mode sets F2 into buffer registers tuning state machine starts AC00052 c u d e t le ) s ( ct o s b O - u d o r P e t e l o s b O 34/60 Doc ID 13311 Rev 3 o r P ) s t( TDA7529 6 Registers description Registers description Figure 16. Registers description No name r/w MSB (7) 6 5 4 3 2 1 LSB (0) Power on default 0 Short reg 1 ADCctrl r/w x x ShAGC ShPLL r/w ADCclk ADCs2 ADCs1 ADCs0 2 GPIOval r/w GPO8_AMAGCv GPO7_FMAGCv GPIO6_MISO GPIO5_Aout 3 AGCmixCtrl r/w IFin1_AM_FM KeyAGCen FMAGCpwr 4 Misc1 r/w WAIT60ms(4) WAIT60ms(3) 5 DivR r/w divr7 divr6 6 IFAGC_SH r/w IFAGC_FM_AM 7 FMAGC r/w FMthr3 8 FM_AM_Vthr 9 MIXalign1 r/w r/w r/w IMRph3 IMRph2 11 PLLctrl r/w 12 PLLctrl2 r/w DZ4 FUNC MODE2 13 PLLtest r/w POL PFD_D1 PFD_D0 14 Misc2 r/w IFAGCin4ctrl EnSMOOTH reg48sel IFAMP_Ictrl0 15 WAIT_LOCK r/w 16 AGCtc_A r/w WAIT LOCK(4) IFAGCtcAM WAIT LOCK(3) IFAGCtcFM WAIT LOCK(2) AMtc1 WAIT LOCK(1) AMtc0 17 AMAGC_A r/w AMthr3 AMthr2 AMthr1 AMthr0 AMAGCmodeC1 18 GPIOm_A r/w GPO8hl GPO7hl GPIO6hl GPIO5hl GPO4hl 19 IFCTRL_A r/w IFin0_Std_IBOC IFAmpgainA2 IFAmpgainA1 IFAmpgainA0 MixinFM AMAGCinbuffer 20 r/w WAIT1ms(5) WAIT1ms(4) WAIT1ms(3) WAIT1ms(2) WAIT1ms(1) WAIT1ms(0) 21 DivN_A1 r/w divnA20 divnA19 divnA18 divnA17 divnA16 divnA15 divnA14 22 DivN_A2 r/w divnA12 divnA11 divnA10 divnA9 divnA8 divnA7 divnA6 23 DivN_A3 r/w divnA4 divnA3 divnA2 divnA1 divnA0 24 DivV_A r/w VCO1r divVA6 divVA5 divVA4 divVA3 divVA2 divVA1 divVA0 00h 25 CPcur_A r/w CPAh3 CPAh2 CPAh1 CPAh0 CPAl3 CPAl2 CPAl1 CPAl0 00h 26 DAC1_A r/w DAC1A8 DAC1A6 DAC1A5 DAC1A4 DAC1A3 DAC1A2 DAC1A1 DAC1A1 27 DAC2_A r/w DAC2A8 DAC2A6 DAC2A5 DAC2A4 DAC2A3 DAC2A2 DAC2A1 DAC2A1 00h 28 PLL_DAC_A r/w IQselA VCOsw DAC1A0 DAC2off DAC1off 00h 29 Misc4_A r/w WAIT2ms(5) WAIT2ms(4) WAIT2ms(3) WAIT2ms(2) WAIT2ms(1) MIN16 00h 30 r/w WAIT0.5ms(5) WAIT0.5ms(4) WAIT0.5ms(3) WAIT0.5ms(2) WAIT0.5ms(1) 31 r/w IF test 10 MIXalign2 ADCen GPIOen PWR 00h ADCautomode Temp_pwr 00h GPO4_AMcas RCenable CP_curr_switch GPIO2io GPIO1io 00h AMAGCpwr MixinFMAM BalunoutIMP Mixout1 Mixout2 00h WAIT60ms(2) WAIT60ms(1) WAIT60ms(0) disvcc PLLtest AMAGC_Isink 00h divr5 divr4 divr3 divr2 divr1 divr0 00h IFAGCthr2 IFAGCthr1 IFAGCthr0 GPIO5 output IFsection_pwr 00h FMthr2 FMthr1 FMthr0 FMAGCmodeC1 FMAGCmodeC0 FMAGCmodeV1 FMAGCmodeV0 00h AMAGCfat AFH_MUX Vthr5 Vthr4 Vthr3 Vthr2 Vthr1 Vthr0 00h IFAMP_Ictrl2 IFAMP_Ictrl1 IredH IMRph1 IredL IMRph0 Casc_ctrl IMRG3 IMRF2 IMRF1 IMRF0 00h IMRG2 IMRG1 IMRG0 00h DZ2 DZ1 CPcur_800u SWfref divRen PLLpwr 00h MODE1 MODE0 DS4 DS3 DS2 DS1 00h PLLT4 PLLT3 PLLT2 PLLT1 PLLT0 00h RCfreq_1 RCfreq_0 VCOMag1 VCOMag0 00h WAIT LOCK(0) FMtc3 DIVVtest FMtc2 VCOext FMtc1 LOCK_bit FMtc0 00h AMAGCmodeC0 AMAGCmodeV1 AMAGCmodeV0 00h GPIO2hl GPIO1hl DZ3 ADCstart RCtest d o r P e let DAC2A0 WAIT2ms(0) WAIT0.5ms(0) 00h so r/w all bytes from 33 to 45 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 29 are valid on the output 34 GPIOm_B r/w 35 IFCTRL_B r/w 36 AMFilt_B r/w 37 DivN_B1 r/w 38 DivN_B2 r/w 39 DivN_B3 r/w 40 DivV_B r/w 41 CPcur_B r/w 42 DAC1_B r/w r/w 45 Misc4_B r/w o r P e 46 47 48 READ_Status r 49 READ_ADC r 00h 00h b O - 00h 00h 00h 00h 00h 00h 00h ct du lock ADCok 00h 00h r/w r/w 00h 00h AGCtest0 33 AMAGC_B 44 PLL_DAC_B 00h 00h ADCDAC0 32 AGCtc_B 43 DAC2_B divnA5 00h 00h AGCtest1 ADC test ADCDAC5 ADCDAC4 ADCDAC3 ADCDAC2 ADCDAC1 this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output (s) uc divnA13 ) s t( 00h 00h 00h 00h 00h 00h 00h 00h GPIO6r GPIO5r MaskMetal1 MaskMetal0 MaskSet1 MaskSet0 00h ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 00h t e l o s b O Doc ID 13311 Rev 3 35/60 Registers description TDA7529 6.1 Data byte specification 6.1.1 Short_reg (0) Table 26. Short_reg (0) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - GPIO enable all GPIO in tristate all GPIO enable - - - - - 0 1 - - ADCen 6bit ADC on 6bit ADC off - - - - 0 1 - - - ADCstart No conversion Starts a single AD conversion - - - 0 1 - - - - ShPLL PLL register from 17 to 31 are valid PLL register from 33 to 47 are valid - - 0 1 - - - - - X - - - - - X - - - - - (s) - Global PWR Power down the IC Power on the IC e t le - ShAGC AGC TC register 16 is valid AGC TC register 32 is valid - Not used - Not used o s b O - t c u d o r P e t e l o s b O 36/60 o r P Doc ID 13311 Rev 3 c u d ) s t( TDA7529 Registers description 6.1.2 ADCctrl (1) Table 27. ADCctrl (1) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - ADC auto mode automatic restart disable automatic restart enable - - - - - 0 1 - - RC oscillator enable enable disable - - - - X - - - ADCstart (like bit 0.3) - ADC input selection Temp sensor FM AGC AM AGC IF AGC VCO tuning voltage (3/5 * Vtune) GP1 GP2 2/5 * VCC - 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 - - - - - - Temperature sensor power Enabled Disabled e t le - - - ) s ( ct c u d ) s t( o r P o s b O - ADC clock selection ADC clock source = RC osc ADC clock source = refdiv output u d o r P e t e l o s b O Doc ID 13311 Rev 3 37/60 Registers description TDA7529 6.1.3 GPIO mode (2) Table 28. GPIO mode (2) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - GPIO2 input / output Analog input to AD converter Digital output - - - - - 0 1 - - CP Current Switch Automatic switch disabled Automatic switch enabled - - - - 0 1 - - - GPIO4 input / output Analog Input digital output GPIO1 input / output Analog input to AD converter digital output c u d ) s t( - - - 0 1 - - - - GPIO5 input / output digital input output (analog or digital) - - 0 1 - - - - - GPIO6 input / output digital input (or MISO output in SPI mode) digital output (or MISO output in SPI mode) - 0 1 0 1 - - - - - - - - - ct (s) u d o - - e t le o s b O - GPIO7 input / output FM AGC voltage output Digital output - GPIO8 input / output AM AGC voltage output Digital output r P e t e l o s b O 38/60 o r P Doc ID 13311 Rev 3 TDA7529 Registers description 6.1.4 AGC and mixer control (3) Table 29. AGC and mixer control (3 MSB LSB Function D6 D7 - D5 - - D4 - D3 D2 - - D1 D0 0 0 1 1 0 1 0 1 Mixout 1 / 2 All Off = power down mixer section Mixout 1 active Mixout 2 active Forbidden state - - - - - 0 1 - - Balun output drive capability Low drive capability High drive capability - - - - 0 1 - - - Mixer input FM / AM selection AM input active FM input active - - - 0 1 - - - - AM AGC On / Off Off On - FM AGC On / Off Off On - - 0 1 - - - - - 0 1 - - - - - 0 1 - - - - ) s ( ct - - e t le c u d ) s t( o r P o s b O - Keyed AGC enable Keyed AGC off keyed AGC on - IF input selection FM / AM IF input AM IF input FM u d o r P e t e l o s b O Doc ID 13311 Rev 3 39/60 Registers description TDA7529 6.1.5 Register (4) Table 30. Register (4) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - PLLtest Off On - - - - - 0 1 - - Disvcc POR activated from IFVCC POR non activated from IFVCC - WAIT60ms 1ms (min. value) 60ms (default value) 80ms (max value) 0 1 1 0 0 1 0 1 1 0 1 1 6.1.6 Divider R (5) Table 31. Divider R (5) 0 1 1 - - MSB AMAGC Isink (2mA fixed current) Off On e t le LSB D6 D7 D5 - X - D4 D3 - o r P e D2 D1 ) s ( ct - du - - so b O D0 X Divider R value DivR0 : : DivR7 t e l o s b O 40/60 Doc ID 13311 Rev 3 c u d o r P Divider R value ) s t( TDA7529 Registers description 6.1.7 IF AGC control (6) Table 32. IF AGC control (6) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - GPIO 5 output mode Off On = GPIO 5 analog output enable - - - - X X - Not used 0 0 : : 1 0 0 : : 1 0 1 : : 1 - IF AGC threshold IF output level = 89dBµV(AM) / 91dBµV (FM) IF output level = 90.5dBµV(AM) / 92.5dBµV (FM) : : IF output level = 99dBµV(AM) / 101dBµV (FM) - - - - 0 1 - - - IF section On / Off Off On c u d - - - - o r P IF AGC mode FM / AM selection FM mode AM mode e t le ) s ( ct ) s t( o s b O - u d o r P e t e l o s b O Doc ID 13311 Rev 3 41/60 Registers description TDA7529 6.1.8 FM AGC (7) Table 33. FM AGC (7) MSB LSB Function D6 D7 - D5 - - - 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D4 - D3 - 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 - - 0 0 1 1 0 1 0 1 D1 D0 0 0 1 1 0 1 0 1 - - Voltage output mode Off N/A Calibration mode Voltage output On Current output mode Off Constant 2mA output Positive current output Neg. / Pos. current output c u d - - - u d o ) s ( ct r P e t e l o s b O 42/60 e t le o s b O - ) s t( FM AGC threshold Mixer input level = 93dBµV (FM1) / 97dBµV (FM2) Mixer input level = 94dBµV (FM1) / 98dBµV (FM2) Mixer input level = 95dBµV (FM1) / 99dBµV (FM2) Mixer input level = 96dBµV (FM1) / 100dBµV (FM2) Mixer input level = 97dBµV (FM1) / 101dBµV (FM2) Mixer input level = 98dBµV (FM1) / 102dBµV (FM2) Mixer input level = 99dBµV (FM1) / 103dBµV (FM2) Mixer input level = 100dBµV (FM1) / 104dBµV (FM2) Mixer input level = 93dBµV (FM1) / 97dBµV (FM2) Mixer input level = 92dBµV (FM1) / 96dBµV (FM2) Mixer input level = 91dBµV (FM1) / 95dBµV (FM2) Mixer input level = 90dBµV (FM1) / 94dBµV (FM2) Mixer input level = 89dBµV (FM1) / 93dBµV (FM2) Mixer input level = 88dBµV (FM1) / 92dBµV (FM2) Mixer input level = 87dBµV (FM1) / 91dBµV (FM2) Mixer input level = 86dBµV (FM1) / 90dBµV (FM2) Doc ID 13311 Rev 3 o r P TDA7529 Registers description 6.1.9 AGC voltage threshold (8) Table 34. AGC voltage threshold (8) MSB LSB Function D6 D7 - - 0 1 - D5 D4 D3 D2 D1 D0 0 0 : : 1 1 0 0 : : 1 1 0 0 : : 1 1 0 0 : : 1 1 0 0 : : 1 1 0 1 : : 0 1 - - - - - - 6.1.10 Mixer alignment 1 (9) Table 35. Mixer alignment 1 (9) MSB Transfer voltage from voltage out to current out 200mV 237.5mV : : 2.5625V 2.6V AM fast attack Off On c u d LSB ) s t( o r P Function D6 D7 - - - - - - s b O - 0 1 0 1 D4 - D3 0 0 1 1 - - 0 1 - - D1 0 0 : 1 : 1 0 0 : 0 : 1 - - ) s ( ct u d o - 0 1 0 1 D2 - r P e t e l o - 0 0 1 1 D5 - - - - e t le D0 IQ-filter frequency adjust +2.4MHz +1.8MHz : 0 : -1.8MHz o s b O 0 1 : 0 : 1 - Cascode control loop On / Off On Off - Mixers current control Normal bias Low reduction High reduction N/A - IFAMP driving capability Normal Intermediate 1 Intermediate 2 High Doc ID 13311 Rev 3 43/60 Registers description TDA7529 6.1.11 Mixer alignment 2 (10) Table 36. Mixer alignment 2 (10) MSB LSB Function D6 D7 D5 D4 - - - - 0 0 0 0 0 : 0 1 1 1 1 1 : 1 1 0 0 0 0 1 : 1 0 0 0 0 1 : 1 1 0 0 1 1 0 : 1 0 0 1 1 0 : 1 1 0 1 0 1 0 : 1 0 1 0 1 0 : 0 1 D3 D2 D1 D0 0 0 0 : 0 1 : 1 1 1 1 1 : 0 0 : 1 1 1 1 0 : 0 0 : 1 1 1 0 1 : 0 0 : 0 1 - - - u d o ) s ( ct - IQ-filter gain adjust -0.7dB -0.6dB -0.5dB : 0dB 0dB : +0.6dB +0.7dB IQ-filter phase adjust 0 +0.2 deg +0.2 deg +0.4 deg +0.6 deg : +1.2 deg -1.2 deg -1.0 deg -1.0 deg -0.8 deg -0.6 deg : -0.2 deg 0 o s b O - r P e t e l o s b O 44/60 e t le Doc ID 13311 Rev 3 o r P c u d ) s t( TDA7529 Registers description 6.1.12 PLL control 1 (11) Table 37. PLL control 1 (11) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Divider R enable Divider R off; = div / 1 Divider R on - - - - - 0 1 - - Select reference input Reference frequency input = LVDS Reference frequency input = Xtal - - - - 0 1 - - - Charge pump current 800μA 0 µA 800 µA - Slope of high current CP highest : lowest 0 : 1 0 : 1 0 : 1 0 : 1 - 6.1.13 PLL control 2 (12) Table 38. PLL control 2 (12) - - e t le MSB D6 - D5 - - D4 D3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 - - - ) s ( ct D2 u d o - r P e t e l o s b O 0 1 o s b O - c u d ) s t( o r P LSB D7 - PLL enable PLL Off PLL On 0 : 1 0 : 1 D1 0 : 1 Function D0 0 : 1 Delay of high current CP shortest : longest - - - - State machine modes decode Buffer mode Preset Search AF update Jump Check Load End - - - - Register functionality control Normal/shadow mode Buffer/control mode Doc ID 13311 Rev 3 45/60 Registers description TDA7529 6.1.14 PLL test (13) Table 39. PLL test (13) MSB LSB Function D7 D6 D5 - - - 0 1 - - 0 D4 D3 D2 D1 X X 1 0 - - - - - - 6.1.15 Misc 2 (14) Table 40. Misc 2 (14) D0 - PLL test Set to default - - PFD default - - PFD polarity MSB LSB Function D6 D7 - D5 - - D4 - - - - - - - - 0 1 - - 0 1 - - - s b O 0 1 46/60 0 1 - - - D2 - - 0 0 1 1 0 1 0 1 D1 0 0 1 1 - ) s ( ct c u d D0 0 1 0 1 VCO magnitude 1V 2V 3V 4V e t le o r P o s b O - Oscillation frequency of RC oscillator 0.68 MHz 1.31 MHz 1.92 MHz 2.49 MHz - - - IFAMP current control Normal bias High current mode bias - - - - Reg48sel ShAGC and ShPLL on D48 MaskMetal and MaskSet on D48 - - - - EnSMOOTH Smooth disabled Smooth enabled - IFAGC control when IN4 selected Normal Thresholds shift - u d o r P e t e l o - D3 - - - Doc ID 13311 Rev 3 ) s t( TDA7529 Registers description 6.1.16 Wait lock (15) Table 41. Wait lock (15) MSB LSB Function D6 D7 - D5 - 0 0 1 0 0 1 - 0 1 1 D4 D3 - D2 - 0 1 1 - 0 0 1 - D1 D0 0 0 1 1 0 1 0 1 - - Test D18 LOCK_bit CMPout VdivOUT Wait lock 0.04ms (min. value) 1ms (default value) 5.08ms (default value) 6.1.17 AGC time constant settings (16 / 32) Table 42. AGC time constant settings (16 / 32) MSB LSB o r P Function D6 D7 - - - - - - - s b O 0 1 - D4 D3 - - - 0 0 1 0 1 0 o r P e t e l o - 0 1 D5 - - - - D2 - - 0 0 1 0 1 0 D1 D0 0 0 1 0 1 0 du ) s ( ct - e t le FM AGC decay time constant D1 D2 D3 o s b O - FM AGC attack time constant A1 A2 A3 - - - - AM AGC time constant T1 T2 T3 - - - - IF AGC time constant FM U1 U2 - IF AGC time constant AM S1 S2 - - - c u d ) s t( Doc ID 13311 Rev 3 47/60 Registers description TDA7529 6.1.18 AMAGC control (17 / 33) Table 43. AMAGC control (17 / 33 MSB LSB Function D6 D7 - D5 - - - 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 - 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 - D3 - - 0 0 1 1 - 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 - 0 1 0 1 - D0 0 0 1 1 0 1 0 1 - - ) s ( ct u d o r P e D1 - AM AGC voltage output mode Off Voltage output / sense internal Calibration Voltage output / sense external AM AGC current output mode Off Constant 2mA Positive current N/A AM AGC thresholds Mixer input level = 94 dBµV Mixer input level = 95 dBµV Mixer input level = 96 dBµV Mixer input level = 97 dBµV Mixer input level = 98 dBµV Mixer input level = 99 dBµV Mixer input level = 100 dBµV Mixer input level = 101 dBµV Mixer input level = 94 dBµV Mixer input level = 93 dBµV Mixer input level = 92 dBµV Mixer input level = 91 dBµV Mixer input level = 90 dBµV Mixer input level = 89 dBµV Mixer input level = 88 dBµV Mixer input level = 87 dBµV o s b O - t e l o s b O 48/60 e t le Doc ID 13311 Rev 3 o r P c u d ) s t( TDA7529 Registers description 6.1.19 GPIO output level control (18 / 34) Table 44. GPIO output level control (18 / 34) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 D0 0 1 0 1 : X : : X : : X : : X : : X : 0 1 6.1.20 IF control (19 / 35) Table 45. IF control (19 / 35) MSB GPIOx high / low output level GPIO1 low GPIO1 high GPIO2 low GPIO2 high : GPIOx low / high : GPIO8 low GPIO8 high c u d LSB ) s t( o r P Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - X - - - - - - 0 1 - - - - - - - - - du t e l o - s b O 0 1 o r P e 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 - - - 0 1 ) s ( ct 0 1 - - - e t le Not used o s b O - RC test Test enabled Test disabled - AMAGC input buffer Buffer enabled Buffer disabled - Mixer input selection for FM FM1 mixer input FM2 mixer input - - - - IF amplifier Gain 25dB (input1-3) / 19dB (input4) 27dB (input1-3) / 21dB (input4) : 37dB (input1-3) / 31dB (input4) 39dB (input1-3) / 33dB (input4) - - - - IF input selection analog / IBOC IBOC Analog Doc ID 13311 Rev 3 49/60 Registers description TDA7529 6.1.21 AF state machine wait time 1 (20 / 36) Table 46. AF state machine wait time 1 (20 / 36) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - X - - - - - - X 0 0 0 0 0 1 0 1 0 0 0 0 - Not used Not used - WAIT 1ms 0.04ms (min. value) 1ms (default value) 6.1.22 PLL main divider (N-divider) 1 (21 / 37) Table 47. PLL main divider (N-divider) 1 (21 / 37) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 X X X Divider N value M8 M9 M10 M11 M12 M13 M14 M15 e t le X X X X X ) s ( ct PLL main divider (N-divider) 2 (22 / 38) Table 48. PLL main divider (N-divider) 2 (22 / 38) u d o D6 D7 r P e D5 D4 D3 t e l o s b O X X 50/60 D1 D0 X X X X LSB Function D2 X X o r P o s b O - 6.1.23 MSB c u d D0 Divider N value M0 M1 M2 M3 M4 M5 M6 M7 Doc ID 13311 Rev 3 ) s t( TDA7529 Registers description 6.1.24 PLL main divider (N-divider) 3 (23 / 39) Table 49. PLL main divider (N-divider) 3 (23 / 39) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 D0 Divider N value A0 A1 A2 A3 A4 X X - X - - X X 6.1.25 PLL Divider ratio calculation Table 50. PLL Divider ratio calculation M counter M16 M15 … M7 A counter … M1 M0 A4 A3 6.1.26 VCO divider (V-divider) (24 / 40) Table 51. VCO divider (V-divider) (24 / 40) MSB D6 D5 D4 D3 D2 D1 ) s ( ct u d o X X X s b O t e l o - - - - X X - - c u d N= 32*P + A N= M*P + A (P=32) M=32 M>32 ) s t( o r P Function D0 r P e X A0 o s b O - X - A1 e t le LSB D7 0 1 A2 Notes - Divider V value V0 V1 V2 V3 V4 V5 V6 VCO range selection Range 2 Range 1 Doc ID 13311 Rev 3 51/60 Registers description TDA7529 6.1.27 Charge pump current (25 / 41) Table 52. Charge pump current (25 / 41) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 D0 X Low current charge pump 50 µA 100 µA 200 µA 400 µA - High current charge pump 0.5 mA 1mA 2mA 4mA X - - - X X X X - - - X X 6.1.28 Tuning DAC 1 (26 / 42) Table 53. Tuning DAC 1 (26 / 42) MSB c u d LSB o r P Function D6 D7 D5 D4 D3 D2 D1 X X ) s ( ct X X X u d o X DAC 1 voltage 8..1 DAC1_. DAC1_2 DAC1_3 DAC1_4 DAC1_5 DAC1_6 DAC1_7 DAC1_8 o s b O X X r P e t e l o s b O 52/60 e t le D0 Doc ID 13311 Rev 3 ) s t( TDA7529 Registers description 6.1.29 Tuning DAC 2 (27 / 43) Table 54. Tuning DAC 2 (27 / 43) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 D0 X X X X X X X X DAC 2 voltage 8..1 DAC2_1 DAC2_2 DAC2_3 DAC2_4 DAC2_5 DAC2_6 DAC2_7 DAC2_8 Note: DAC output voltage = 600mV + DACval * 9mV 6.1.30 Different controls (28 / 44) Table 55. Different controls (28 / 44) MSB LSB D6 D7 D5 D4 D3 - - - - - - - - - - - - - - - - - - - - - X X - X - - - - 0 1 c u d s b O - D1 - e t le D0 o s b O 0 1 DAC 2 On / Off Off On - - DAC 1_0 - - - DAC 2_0 - - - - Not used - - - - Not used - - - - IQ phase select I anticipates Q Q anticipates I ) s ( ct X - 0 1 X o r P Function DAC 1 On / Off Off On - u d o r P e t e l o - D2 ) s t( Doc ID 13311 Rev 3 53/60 Registers description TDA7529 6.1.31 Misc 3 (29 / 45) Table 56. Misc 3 (29 / 45) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 - - - - - - - - - - - - - X Not used 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1 1 - WAIT 2ms 0.08ms (min. value) 2ms (default value) 5.04ms (default value) 6.1.32 Analog test select (30 / 46) Table 57. Analog test select (30 / 46) MSB D0 X - PLL N divider MSB M16 c u d LSB Function D6 D7 - D5 0 0 1 - 0 0 1 - 0 0 1 D4 - D3 D2 0 1 1 - 0 1 1 - 0 0 1 D1 D0 0 0 1 1 0 1 0 1 - ) s ( ct e t le o s b O - WAIT 0.5ms 0.02ms (min. value) 0.5ms (default value) 5.06ms (max value) u d o r P e t e l o s b O 54/60 o r P Analog test output signal select IF AGC FM AGC AMAGC DAC voltage of ADC Doc ID 13311 Rev 3 ) s t( TDA7529 Registers description 6.1.33 AD converter test (31 / 47) Table 58. AD converter test (31 / 47) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 D0 X X - X X X X - 0 1 0 1 - - - - - - - - 6.1.34 Read 1 (48) Table 59. Read 1 (48) - - - MSB D6 - D5 - - - D4 - D3 r P e - - - 0 1 - - 0 1 - - D1 0 0 1 1 ) s ( ct u d o - t e l o D2 - 0 0 1 1 - s b O - - ADC test enable Off On - AGC test enable Off On e t le LSB D7 - ADC DAC direct programming DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 - D0 so o r P Function b O 0 1 0 1 Mask set revision A B C D - - Metal mask revision A B C D - - - GPIO 5 level low high - - - GPIO 6 level low high 0 1 0 1 c u d ) s t( Doc ID 13311 Rev 3 55/60 Registers description TDA7529 6.1.35 Read 2 (49) Table 60. Read 2 (49) MSB LSB Function D6 D7 D5 D4 D3 D2 D1 D0 X X - X X X X - 0 1 - - - - - - AD converter result ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 AD converter result status Not OK OK c u d e t le ) s ( ct o s b O - u d o r P e t e l o s b O 56/60 Doc ID 13311 Rev 3 o r P ) s t( AMANT FMANT CON29 180nH Toko LLQ2012-FR18 R3 220 REFN REFP IFAGC1 IFAGC2 AFHOLD AFSAMPLE MISO SDA SCL CSN VCC_5V IFOUT1 IFOUT2 DAC1/DAC2 VPLL_5V RF L5 1nF 18pF RF C36 C26 D1 KP2311E Toko PLL RF L3 IF BALUN 100nF C19 R13 4.7nF C46 3 2 1 C43 D4 BAR14-I Infineon 10k 22nF 100nF C50 220 C34 22pF 5.6pF RF 1nF C32 2.2uF C51 C24 8.2pF 1mH RF L11 5 RF 100nF C40 R9 27 C11 L2 680pF 22uF C39 RF 100nF VRF_5V C37 100nF RF C29 3 C16 39pF BALUN 33pF C47 C20 C13 100nF L1 3 2 1 12pF 6 5 4 1uF C49 IFAGC2 IFAGC1 RF 100nF BALUN 22uF C69 DAC2 Balundec BALUN1 IFAGC1 MIXbiasdec AMMIXin AMMIXdec AMAGC1 GNDRF1 FMMIX2dec FMMIX2in FMAGC1 FMAGC2/GP7 FMMIX1dec FMMIX1in DAC1 RF 2k R11 C35 16 15 14 13 12 11 10 9 8 FMAGC2/GP7 7 10uH muRata LQM18FN100M00B 68pF 220nF L12 C45 C44 L10 BLMM18BD102SN1 muRata LLQ2012-FR33 Toko 330 nH 68uH muRata LQ2MCN680K02B LLQ2012-FR33 Toko 330 nH 1M R16 4 2 2 10nF C27 RF C22 680pF DAC1/DAC2 D3 KV1770R Toko L7 C10 100nF Toko E558HN-100101 93 nH 1 Q1 HN3G01J Thoshiba 390 R10 RF C28 L6 xxx R7 68K 330 R1 VCC_5V XT1 100nF C4 BALUN SFEL10M7 muRata 1 VRF_5V 100nF C52 22uF 2 U1 TDA7529 220pF C48 C38 100nF VCO IF PLL VCO 100nF C53 100 R14 4.7K R12 100nF C1 GP1 RO 10nF PLL XTALI XTALO VCCRO GNDBUS PS CS/AS CLK MOSI MISO/GP6 VCCBUS VDDdec BIASD2 IFout2 IFout1 TCIF1 4 22uF C70 VPLL_5V L8 BLM18D102SNI muRata 22uF RO 100nF AC00053 REFP 22uF 33 VDIG_5V VDIG_5V C33 100 100nF C23 L4 BLMM18BD102SN1 muRata C71 BUS 22uF C25 22uF C18 IFOUT2 IFOUT1 REFN 22k R8 SCL SDA R2 100nF C21 10nF C15 C17 10nF C12 34 220 R6 2.2uF 220 IF VCC_5V BLMM18BD102SN1 muRata R5 C14 22uF C6666 L20 35 36 37 38 39 40 41 42 43 44 45 46 47 48 IF 22nF IF GNDIF 100nF C9 C6 C42 c u d R15 C30 R4 1.5k L9 68uH muRata LQ2MCN680K02B LLQ2012-FR39 Toko 390 nH RO BUS VCO RF 3 FMANT AMANT 2 1 62 VRF_5V D2 KP2311E Toko 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 18 AMAGC2/GP8 19 GP4/VDS AFSAMPLE AFHOLD 20 53 o r P 1 64 BALUNout2 17 GP5 J1 21 IFAGC2 AFHOLD 1uF C8 1uF 61 TCFM 63 BALUNout1 C7 VCCRF2 60 TCAM AFSAMPLE 58 GP5 VCOdec1 23 Vtune 24 VCCRF1 22 GP2/Key 56 25 59 GNDRF2 57 IFin1 55 100nF C5 54 C76 GP2/Key VCOdec2 52 VCCIF GndPLL 51 IFin4 VCCPLL 50 IFdec GP1 49 TCIF2 GndRO IFin2 VCOgnd 26 BIASD1 LFLC 27 IFin3 LFHC 28 Doc ID 13311 Rev 3 29 t e l o 30 RF 31 s b O o s b O e t le 32 d o r P e t c u (s) BUS IF 7 3 TDA7529 Application schematic Application schematic Figure 17. Application schematic ) s t( 57/60 Package information 8 TDA7529 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 18. LQFP64 (10x10x1.4mm) exposed pad down mechanical data and package dimensions (exposed pad size for D2 and E2: 4.5mm max.) mm inch DIM. MIN. TYP. MAX. MIN. TYP. 0.150 0.0020 A1 0.050 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 0.0059 c 0.090 D 11.800 12.000 12.200 0.4646 0.4724 0.4803 D1 9.800 10.000 10.200 0.3858 0.3937 0.4016 D2 OUTLINE AND MECHANICAL DATA MAX. 0.200 0.0035 0.0079 c u d According to Pad size D3 7.500 0.2953 E 11.800 12.000 12.200 0.4646 0.4724 0.4803 E1 9.800 10.000 10.200 0.3858 0.3937 0.4016 E2 According to Pad size E3 7.500 e 0.500 L 0.450 0.0197 0.600 L1 1.000 k 3.500 e t le 0.2953 o s b O - 0.750 0.0177 0.0236 0.0295 ccc 0.0394 7.000 0.1378 0.2756 0.080 0.0031 Note: 1. Exact shape of each corner is optional. ) s ( ct ) s t( o r P LQFP64 (10x10x1.4mm) Exposed Pad Down u d o r P e t e l o s b O 7278841 C 58/60 Doc ID 13311 Rev 3 TDA7529 9 Revision history Revision history Table 61. Document revision history Date Revision Changes 07-Mar-2007 1 Initial release. 04-Jun-2007 2 Minor text changes. 17-Dec-2009 3 Modify Table 24: Serial data interface on page 28. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Doc ID 13311 Rev 3 59/60 TDA7529 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. c u d ) s t( Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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