USBULC1606-4M8

USBULC1606-4M8 Ultra low capacitance ESD protection for enhanced mini USB interface Features ■ Diode array topology ■ D+/D- and ID lines protection with 6.8 V low voltage diodes (LV) ■ VBUS line protection with 14.6 V high voltage diodes (HV) ■ Ultra low capacitance 0.5 pF on low voltage diodes ■ 5 GHz bandwidth at -3 dB ■ 1.35 mm width and 0.5 mm height package ■ Lead-free package ■ Low capacitance between lines to ground for optimized data integrity ■ Low PCB space consumption: 2.3 mm² max foot print ■ Low clamping voltage ■ Easy layout ■ CEA-936-A specification compliant u d o Pr r P e t e l o Figure 1. bs s ( t c High bandwidth Pin configuration (top view) 1 8 2 7 GND 3 6 4 5 Description Complies with following standards e t e ol u d o Micro QFN-8L package O ) ■ ■ ) s ( ct The USBULC1606-4M8 is an application specific discrete device dedicated to ESD protection of an enhanced Mini USB interface. IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) bs The device is ideal for applications where both reduced print circuit board space and power absorption capability are required. OApplications Where transient over-voltage protection in ESD sensitive equipment is required, such as: ■ Computers ■ Printers ■ Communication systems ■ Cellular phone handsets and accessories ■ Video equipment December 2009 Doc ID 16864 Rev 1 1/15 www.st.com 15 Characteristics USBULC1606-4M8 1 Characteristics Table 1. Absolute maximum ratings Tamb = 25 °C Symbol VPP Parameter Value ESD discharge IEC 61000-4-2, level 4 Contact discharge HV diode Contact discharge LV diodes Air discharge all pins 15 15 8 Unit kV VLVMAX DC Voltage on low-voltage pins 6.0 V VHVMAX DC Voltage on high-voltage pin (Vcc pin) 14.5 V 2.5 A Ipp Ppp Tj Peak pulse power dissipation (8/20 µs) on high voltage pin (Vcc Tj initial = Tamb Top Operating temperature range Tstg Storage temperature range Table 2. r P e let o s b O ) Parameter Test conditions s ( t c VF1 + LV Diode Reverse Voltage – Positive Voltage VF1 - LV Diode Forward Voltage – Negative Voltage IRM1 Low Voltage diode leakage current Rd1 Dynamic Resistance of LV Diode du e t e l o r P o s b W 125 °C -30 to + 85 °C -55 to +150 °C Low Voltage diode input capacitance Min. Typ. Max. Unit IF = 10 mA 6.8 9.2 V IF = 10 mA -1.05 -0.6 V 0.1 µA VIN = 3.3 V, VN = 0 V Ta = -30 to + 65 °C IPP = 1 A, tp = 8/20 µs 1.5 VIN = 0 V, Vosc = 30 mV F = 1 MHz Any I/O pin to VN 0.95 VIN = 200 mV, Vosc = 200 mV F = 240 MHz Any I/O pin to VN 0.5 VCL1 Low Voltage diode clamping voltage IPP = 1 A, tp = 8/20 µs Positive Transient Negative transient VCL2 High Voltage diode clamping voltage IPP = 1 A, tp = 8/20 µs IPP = 2.5 A, tp = 8/20 µs VF2 + HV Diode Reverse Voltage – Positive Voltage IF = 10 mA 2/15 u d o 70 Electrical characteristics Tamb = 25 °C, otherwise specified Symbol C1 pin)(1) Junction temperature 1. For a surge greater than the maximum values, the diode will fail in short-circuit O ) s ( ct Peak pulse current (8/20 µs) on high voltage pin (Vcc pin) Doc ID 16864 Rev 1 Ω 1.1 pF 0.55 10 -2.4 14.6 V 21 28 V 17.7 V USBULC1606-4M8 Table 2. Characteristics Electrical characteristics Tamb = 25 °C, otherwise specified (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit -0.4 V 1.0 µA VF2 - HV Diode Forward Voltage – Negative Voltage IRM2 High Voltage diode leakage current VIN = 11 V, DAP grounded 0.1 Rd2 Dynamic Resistance of HV Diode IPP = 1 A, tp = 8/20 µs 2.8 Ω C2 High Voltage diode input capacitance Exposed pad grounded, VIN = 2.5 V, F = 1 MHz 10 pF Figure 2. IF = 10 mA -1.5 S21 attenuation measurement on high speed lines 0 ) s ( ct dB VIN = 0V u d o -0.5 VIN = 1.65V -1 r P e -1.5 t e l o -2 -2.5 -3 ) (s -3.5 -4 t c u -4.5 d o r -5 P e -5.5 t e l o -6 s b O 100k 100k F(Hz) 1M 1M 10M 10M f/Hz 100M 100M 1G 1G s b O Doc ID 16864 Rev 1 3/15 Characteristics USBULC1606-4M8 Figure 3. Electrical schematic VCC VP (Internal) Pin 4 14.6V Pin 1 CH1 Pin 2 CH2 Pin 3 CH3 6.8V EP Pin 5 GND Figure 4. ) s ( ct VN u d o Typical application VCC t e l o high speed data lines )- s ( t c Pr Table 3. ete Pin ol bs O 4/15 u d o r P e s b O EP* VN channel GND * Exposed pad on back of package (connect to ground) Pin configuration typical application Name Type Description 1 CH1 I/O LV low-capacitance ESD channel 2 CH2 I/O LV low-capacitance ESD channel 3 CH3 I/O LV low-capacitance ESD channel 4 VCC 5 VN 6 NC 7 NC 8 NC EP GND HV VDD HV ESD Channel Negative voltage supply rail Exposed pad Doc ID 16864 Rev 1 USBULC1606-4M8 Figure 5. Characteristics Low voltage diode capacitance vs. reverse voltage (typical value) C(pF) 3.00 2.50 2.00 1.50 1.00 ) s ( ct 0.50 VR(V) u d o 0.00 0.5 0 Figure 6. 1 1.5 r P e Low voltage diode capacitance versus frequency (typical value) 1.000 t e l o C (pF) 0.900 0.800 0.700 ) (s 0.600 0.500 s b O IO/GND Vosc = 30 mVRMS Tj = 25 °C t c u 0.400 0.300 d o r 0.200 let P e o s b 0.100 Frequency(GHz) 0.000 0 1 2 3 O Doc ID 16864 Rev 1 5/15 Characteristics Figure 7. USBULC1606-4M8 ESD response to IEC 61000-4-2 (+15 kV air discharge) on high speed lines 100 ns/div 5.00 V/div Figure 9. ESD response to IEC 61000-4-2 (+15 kV air discharge) on Vcc Figure 8. ESD response to IEC 61000-4-2 (-15 kV air discharge) on high speed lines ) s ( ct 100 ns/div 5.00 V/div u d o Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge) on Vcc r P e t e l o ) (s t c u 10.0 V/div 100 ns/div d o r Figure 11. Relative variation of peak pulse power versus initial junction temperature 1.1 P e t e l o PPP[Tj initial] / PPP [Tj initial=25 °C] 1.0 0.8 100 ns/div 5.00 V/div Figure 12. Peak pulse power versus exponential pulse duration (Typical values - VCC pin) 10000 PPP(W) VCC/GND Tj initial = 25 °C VCC/GND s b O 0.9 s b O 1000 0.7 0.6 100 0.5 0.4 0.3 10 0.2 0.1 Tj (°C) 0.0 0 6/15 25 50 75 100 125 150 TP (µs) 1 1 Doc ID 16864 Rev 1 10 100 1000 USBULC1606-4M8 Characteristics Figure 13. Clamping voltage versus peak pulse current (typical values - VCC pin) 10.0 Figure 14. Forward voltage drop versus peak forward current (typical values - VCC pin) IPP(A) 10.0 IFM (A) VCC/GND Tj initial = 25 °C VCC/GND Tj initial = 25 °C 8/20 µs 1.0 1.0 0.1 0.1 14 16 18 20 22 24 26 ) s ( ct VFM (V) VCL (V) 0.0 0.5 28 1.0 1.5 2.0 2.5 3.0 3.5 u d o Figure 15. Relative variation of leakage current versus junction temperature (typical values -VCC pin) 1000 r P e IR[Tj]/IR[Tj = 25 °C] t e l o VCC/GND VR = 11V 100 ) (s 10 t c u 1 25 d o r 50 Figure 16. Eye diagram PCB only 400 mV amplitude, F = 480 Mbps P e t e l o s b O Tj (°C) 75 100 125 Figure 17. Eye diagram PCB + USBULC1064M8 400 mV amplitude, F = 480 Mbps s b O Doc ID 16864 Rev 1 7/15 Ordering information scheme 2 USBULC1606-4M8 Ordering information scheme Figure 18. Ordering information scheme ULC USB 1606 – 4 M8 USB protection Ultra low capacitance Breakdown voltage 1606 = Dual voltage 14.6 Volts min and 6.8 V min ) s ( ct Number of lines 4 = 4 lines u d o Package M8 = µQFN- 8L r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 8/15 Doc ID 16864 Rev 1 USBULC1606-4M8 3 Package information Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 4. Micro QFN 1.7 x 1.35 package dimensions Ref D E Millimeters Min Typ A 0.45 0.50 A1 0.00 0.025 b 0.15 0.20 e t e l A A1 E2 s ( t c e D2 u d o du Min o r P Typ Max 0.55 0.018 0.020 0.022 0.05 0.00 0.001 0.002 0.25 0.006 0.008 0.010 o s b 1.10 1.2 1.30 0.043 0.047 0.051 E 1.25 1.35 1.45 0.050 0.053 0.057 E2 0.30 0.40 0.50 0.012 0.016 0.020 1.60 1.7 1.80 0.063 0.067 0.071 D2 O ) b Max Inches D k L ) s ( ct Dimensions Pin 1 index area e 0.40 k 0.17 L 0.15 0.016 0.007 0.25 0.35 0.006 0.010 0.014 r P e t e l o s b O Doc ID 16864 Rev 1 9/15 Package information USBULC1606-4M8 Figure 19. Foot print recommendations (dimensions in mm) Figure 20. Marking 1.4 Pin 1 16 0.225 0.4 0.45 0.4 ) s ( ct 0.2 u d o Figure 21. Micro QFN-8L tape and reel specifications 2.0 ± 0.05 t c u 16 1.60 ± 0.10 3.5 ±- 0.05 1.95 ± 0.10 16 16 t e l o ) (s s b O 16 P e t e l o 16 8.0 ± 0.3 0.30 ± 0.05 d o r r P e Ø 1.55 ± 0.05 4.0 ± 0.1 1.75 ± 0.1 1.75 16 1.2 16 4.0 ± 0.1 0.60 ± 0.05 bs O Note: 10/15 All dimensions in mm User direction of unreeling Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 16864 Rev 1 USBULC1606-4M8 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 22. Stencil opening dimensions L T b) u d o General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L×W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. ) s ( ct W Reference design ) (s r P e t e l o s b O a) Stencil opening thickness: 100 µm b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. c) Stencil opening for leads: Opening to footprint ratio is 90%. t c u d o r Figure 23. Recommended stencil window position 5 µm 5 µm P e s b O 450 µm 425 µm t e l o 12.5 µm 1.4 190 µm 12.5 µm 1.2 1.75 200 µm 0.225 0.4 1200 µm 0.45 400 µm 240 µm 80 µm 960 µm 0.2 Footprint 80 µm 120 µm 0.4 120 µm Doc ID 16864 Rev 1 Stencil windo w Footprint 11/15 Recommendation on PCB assembly 4.2 USBULC1606-4M8 4.3 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. 4.4 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. u d o r P e t e l o ) (s PCB design preference s b O t c u 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. d o r P e t e l o s b O 12/15 ) s ( ct Doc ID 16864 Rev 1 USBULC1606-4M8 4.5 Recommendation on PCB assembly Reflow profile Figure 24. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max ) s ( ct 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec e t e ol 90 to 150 sec Note: 90 sec max Pr u d o 6 7 Time (min) s b O Minimize air convection currents in the reflow oven to avoid component movement. ) (s t c u d o r P e t e l o s b O Doc ID 16864 Rev 1 13/15 Ordering information 5 USBULC1606-4M8 Ordering information Table 5. Ordering information Order code Marking Package Weight Base qty Delivery mode USBULC1606-4M8 16(1) µQFN 3.43 mg 3000 Tape and reel (7”) 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history Table 6. Document revision history Date Revision 03-Dec-2009 1 Changes r P e Initial release. t e l o ) (s s b O t c u d o r P e t e l o s b O 14/15 u d o Doc ID 16864 Rev 1 ) s ( ct USBULC1606-4M8 ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. r P e All ST products are sold pursuant to ST’s terms and conditions of sale. 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