VN5E160ASO-E
Single channel high-side driver with analog
for automotive applications
Datasheet − production data
Features
Max supply voltage
VCC
Operating voltage range
VCC 4.5 V to 28 V
Max on-state resistance (per ch.) RON
41 V
SO-16L
("1($'5
160 mΩ
Current limitation (typ)
ILIMH
10 A
Off-state supply current
IS
2 µA(1)
– Overtemperature shutdown with
autorestart (thermal shutdown)
– Reverse battery protected
– Electrostatic discharge protection
1. Typical value with all loads connected.
■
■
■
General
– Inrush current active management by
power limitation
– Very low standby current
– 3.0 V CMOS compatible inputs
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– Compliant with European directive
2002/95/EC
– Very low current sense leakage
– AEC-Q100 qualified
Diagnostic functions
– Proportional load current sense
– High-precision current sense for
wide-range currents
– Current sense disable
– OFF-state open-load detection
– Output short to VCC detection
– Overload and short to ground
(power limitation) indication
Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self-limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
September 2013
This is information on a product in full production.
Application
■
All types of resistive, inductive and capacitive
loads
■
Suitable as LED driver
Description
The VN5E160ASO-E is a single channel highside driver manufactured using ST proprietary
VIPower® M0-5 technology and housed in
SO-16L package. The device is designed to drive
12 V automotive grounded loads, and to provide
protection and diagnostics. It also implements a
3 V and 5 V CMOS-compatible interface for the
use with any microcontroller.
The device integrates advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, overtemperature shut-off with
auto-restart and overvoltage active clamp. A
dedicated analog current sense pin is associated
with every output channel providing ehnanced
diagnostic functions including fast detection of
overload and short-circuit to ground through
power limitation indication, overtemperature
indication, short-circuit to VCC diagnosis and ONstate and off-state open-load detection. The
current sensing and diagnostic feedback of the
whole device can be disabled by pulling the
CS_DIS pin high to share the external sense
resistor with similar devices.
Doc ID 022475 Rev. 5
1/37
www.st.com
1
Contents
VN5E160ASO-E
Contents
1
Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 24
3.1.2
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 25
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1
3.5
4
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 28
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1
5
Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . 27
SO-16L thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Open-load detection (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO-16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 022475 Rev. 5
3/37
List of figures
VN5E160ASO-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
4/37
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OFF-state open-load delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Delay response time between rising edge of output current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Maximum current sense ratio drift vs load current(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OFF-state open-load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Tj evolution in overload or short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input voltage clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Hysteresis input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ON-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ON-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CS_DIS voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Low-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Maximum turn-off current versus inductance (for each channel)(1) . . . . . . . . . . . . . . . . . . 28
SO-16L PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 29
SO-16L thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . 30
Thermal fitting model of a single channel HSD in SO-16L . . . . . . . . . . . . . . . . . . . . . . . . . 30
SO-16L package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SO-16L tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SO-16L tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 022475 Rev. 5
VN5E160ASO-E
1
Block diagram and pin configuration
Block diagram and pin configuration
Figure 1.
Block diagram
6 &&
6LJQDO&ODPS
8QGHUYROWDJH
,1
&RQWURO 'LDJQRVWLF
3RZHU
&ODPS
'5,9(5
921
/LPLWDWLRQ
2YHU
WHPSHUDWXUH
&XUUHQW
/LPLWDWLRQ
2))6WDWH
2SHQORDG
&6B
',6
96(16(+
&6
&XUUHQW
6HQVH
287
29(5/2$'3527(&7,21
$&7,9(32:(5/,0,7$7 ,21
/2*,&
*1'
*$3*&)7
Table 1.
Pin function
Name
Function
VCC
Battery connection.
OUT
Power output.
GND
Ground connection. Must be reverse battery protected by an external
diode/resistor network.
IN
Voltage-controlled input pin with hysteresis, CMOS compatible; it controls output
switch state.
CS
Analog current sense pin; it delivers a current proportional to the load current.
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin.
Doc ID 022475 Rev. 5
5/37
Block diagram and pin configuration
Figure 2.
VN5E160ASO-E
Configuration diagram (top view)
9FF
9FF
*1'
1&
1&
1&
,1387
1&
&6(16(
287387
1&
287387
287387
&6',6
9FF
9FF
("1($'5
Table 2.
Suggested connections for unused and not connected pins
Connection / pin
Current sense
N.C.
Output
Input
CS_DIS
Floating
Not allowed
X(1)
X
X
X
To ground
Through 1 kΩ
resistor
X
Not allowed
1. X: do not care.
6/37
Doc ID 022475 Rev. 5
Through 10 kΩ Through 10 kΩ
resistor
resistor
VN5E160ASO-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
)6
9&&
,&6'
9)
,287
287
&6B',6
9287
9&6'
,,1
9&&
,1
,6(16(
&6
9,1
*1'
96(16(
,*1'
*$3*&)7
1. VF = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in the “absolute maximum ratings” table for extended periods
may affect device reliability.
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
0.3
V
-IGND
DC reverse ground pin current
200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
6
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
200
mA
VCC - 41
+VCC
V
V
36
mJ
IIN
ICSD
-ICSENSE DC reverse CS pin current
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy (single pulse)
(L = 8 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150°C;
IOUT = IlimL(Typ.) )
Doc ID 022475 Rev. 5
7/37
Electrical specifications
Table 3.
VN5E160ASO-E
Absolute maximum ratings (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge
(human body model: R = 1.5 KΩ; C = 100 pF)
– IN
– CS
– CS_DIS
– OUT
– VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Tj
Tstg
2.2
Parameter
Thermal data
Table 4.
Thermal data
Symbol
Parameter
Rthj-pcb
junction-pcb(1)
Thermal resistance
Rthj-amb Thermal resistance junction - ambient on two layers pcb
Rthj-amb Thermal resistance junction - ambient on two layers
Typical value
Unit
18.5
°C/W
See Figure 36
°C/W
38
°C/W
pcb(2)
1. The measure is done in accordance with the JESD 51-8.
2. Four Layers PCB characteristics:
- Cu thickness: 70 um outer layers, 35 um inner layers
- Board finish thickness 1.6 mm +/- 10%
- Thermal vias separation 1.2 mm
- Thermal via diameter 0.3 mm +/- 0.08 mm
- Cu thickness on vias 0.025 mm
- Device soldered at about 2cm from the PCB edge with two sqcm of exposed copper.
8/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8 V < VCC < 28 V; -40°C < Tj < 150°C, unless
otherwise stated.
Table 5.
Power section
Symbol
Parameter
Test conditions
VCC
Operating supply voltage
VUSD
VUSDhyst
Min. Typ. Max. Unit
4.5
13
28
V
Undervoltage shut-down
3.5
4.5
V
Undervoltage shut-down
hysteresis
0.5
IOUT = 1 A; Tj = 25°C
RON
Vclamp
IS
IL(off1)
VF
ON-state resistance
Voltage clamp
160
IOUT = 1 A; Tj = 150°C
320
IOUT = 1 A; VCC = 5 V; Tj = 25°C
210
IS = 20 mA
Supply current
OFF-state output current
Output - VCC diode
voltage
V
41
mΩ
46
52
V
OFF-state: VCC = 13 V;
VIN = VOUT = 0 V; Tj = 25°C
2(1)
5(1)
µA
ON-state: VIN = 5 V; VCC = 13 V;
IOUT = 0 A
1.9
3.5
mA
0.01
3
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25°C
0
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125°C
0
µA
-IOUT = 1 A; Tj = 150°C
5
0.7
V
1. PowerMOS leakage included.
Table 6.
Symbol
Switching (VCC = 13 V; Tj = 25 °C)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RL = 13 Ω
(see Figure 6)
—
10
—
µs
td(off)
Turn-off delay time
RL = 13 Ω
(see Figure 6)
—
10
—
µs
dVOUT/dt(on) Turn-on voltage slope RL = 13 Ω
—
See Figure 26
—
V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 13 Ω
—
See Figure 28
—
V/µs
WON
Switching energy
losses during twon
RL = 13 Ω
(see Figure 6)
—
0.05
—
mJ
WOFF
Switching energy
losses during twoff
RL = 13 Ω
(see Figure 6)
—
0.03
—
mJ
Doc ID 022475 Rev. 5
9/37
Electrical specifications
Table 7.
Symbol
VN5E160ASO-E
Logic inputs
Parameter
Test conditions
VIL
Low-level input voltage
IIL
Low-level input current
VIH
High-level input voltage
IIH
High-level input current
VI(hyst)
Hysteresis input voltage
VICL
ICSDL
Low-level CS_DIS current
VCSDH
High-level CS_DIS voltage
ICSDH
High-level CS_DIS current
VCSD(hyst)
Hysteresis CS_DIS voltage
Symbol
CS_DIS voltage clamp
0.9
V
2.1
V
10
5.5
7
V
-0.7
VCSD = 0.9 V
µA
2.1
V
VCSD = 2.1 V
10
0.25
ICSD = 1 mA
V
1
µA
V
5.5
7
V
ICSD = -1 mA
-0.7
Protection and diagnostics(1)
Parameter
Test conditions
VCC = 13 V
Short-circuit current
V = 13 V; TR < Tj < TTSD
during thermal cycling CC
TTSD
Shutdown
temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
Min.
Typ.
Max.
Unit
7
10
14
A
14
A
5 V < VCC < 28 V
2.5
150
175
TRS + 1
TRS + 5
A
200
135
Thermal hysteresis
(TTSD - TR)
Turn-off output
voltage clamp
IOUT = 1 A; VIN = 0,
L = 20 mH
Output voltage drop
limitation
IOUT = 0.03 A (see Figure 8)
Tj = -40 °C to +150 °C
Doc ID 022475 Rev. 5
°C
°C
°C
7
°C
VCC - 41 VCC - 46 VCC - 52
V
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/37
µA
V
0.9
IlimL
VON
Unit
0.25
DC short-circuit
current
VDEMAG
Max.
µA
VIN = 2.1 V
IlimH
THYST
Typ.
1
IIN = -1 mA
Low-level CS_DIS voltage
Table 8.
VIN = 0.9 V
IIN = 1 mA
Input voltage clamp
VCSDL
VCSCL
Min.
VN5E160ASO-E
Electrical specifications
Table 9.
Symbol
Current sense (8 V < VCC < 18 V)
Parameter
Test conditions
Min.
Typ.
Max.
265
490
715
355
385
465
465
575
545
Unit
K0
IOUT/ISENSE
IOUT = 0.025 A;
VSENSE = 0.5 V
Tj = -40°C to 150°C
K1
IOUT/ISENSE
IOUT = 0.35 A; VSENSE = 0.5 V
Tj = -40°C to 150°C
Tj = 25°C to 150°C
Current sense ratio drift
IOUT =0.35 A; VSENSE = 0.5 V
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 0.5 A; VSENSE = 4 V
Tj = -40°C to 150°C
Tj = 25°C to 150°C
Current sense ratio drift
IOUT = 0.5 A;
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 1.5 A; VSENSE = 4 V
Tj = -40°C to 150°C
Tj = 25°C to 150°C
Current sense ratio drift
IOUT = 1.5 A;
Tj = -40°C to 150°C
-4
+4
IOUT = 0 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 0 V;
Tj = -40°C to 150°C
0
1
IOUT = 0 A; VSENSE = 0 V;
VCSD = 0 V; VIN = 5 V;
Tj = -40°C to 150°C
0
2
IOUT = 1 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 5 V;
Tj = -40°C to 150°C
0
1
Max analog sense
output voltage
RSENSE = 10 KΩ
IOUT = 1 A;
5
VSENSEH(2)
Analog sense output
voltage in fault condition
VCC = 13 V; RSENSE = 3.9 KΩ
8
V
ISENSEH(2)
Analog sense output
current in fault condition
VCC = 13 V; VSENSE = 5 V
9
mA
Delay response time
tDSENSE1H from falling edge of
CS_DIS pin
VSENSE < 4 V;
0.025 A < IOUT < 1.5 A
ISENSE = 90% of ISENSE max
(see Figure 4)
40
100
µs
Delay response time
tDSENSE1L from rising edge of
CS_DIS pin
VSENSE < 4 V;
0.025 A < IOUT < 1.5 A
ISENSE = 10% of ISENSE max
(see Figure 4)
5
20
µs
dK1/K1(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
ISENSE0
VSENSE
Analog sense leakage
current
Doc ID 022475 Rev. 5
-11
380
400
+11
455
455
-8
420
420
530
510
+8
455
455
%
%
490
480
%
µA
V
11/37
Electrical specifications
Table 9.
Symbol
VN5E160ASO-E
Current sense (8 V < VCC < 18 V) (continued)
Parameter
Test conditions
Min.
VSENSE < 4 V;
Delay response time
0.025 A < IOUT < 1.5 A
tDSENSE2H
from rising edge of IN pin ISENSE=90% of ISENSE max
(see Figure 4)
Delay response time
between rising edge of
ΔtDSENSE2H
output current and rising
edge of current sense
VSENSE < 4 V;
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=1.5A (see Figure 7)
Delay response time
tDSENSE2L from falling edge of IN
pin
VSENSE < 4 V;
0.025 A < IOUT < 1.5 A
ISENSE=10% of ISENSE max
(see Figure 4)
Typ.
Max.
Unit
30
160
µs
110
µs
250
µs
Max.
Unit
80
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open load OFF-state detection.
Table 10.
Symbol
Parameter
Test conditions
Min.
Typ.
VOL
OFF-state open-load
V = 0 V; 8 V < VCC < 18 V
voltage detection threshold IN
2
4
V
IOL
ON-state open-load
VIN = 5V; 8 V < VCC < 18 V
current detection threshold ISENSE = 5 µA
0.5
5
mA
Output short-circuit to VCC
detection delay at turn-off
180
1200
µs
tDSTKON
12/37
Open-load detection (8 V < VCC < 18 V)
See Figure 5
IL(off2)r
OFF-state output current at VIN = 0 V; VSENSE = 0 V
VOUT = 4 V
VOUT rising from 0 V to 4 V
-120
0
IL(off2)f
VIN = 0 V;
OFF-state output current at
VSENSE = VSENSEH
VOUT = 2 V
VOUT falling from VCC to 2 V
-50
90
td_vol
Delay response from
output rising edge to
VSENSE rising edge in
open-load
VOUT = 4 V; VIN = 0 V
VSENSE= 90% of VSENSEH
Doc ID 022475 Rev. 5
µA
20
µs
VN5E160ASO-E
Electrical specifications
Figure 4.
Current sense delay characteristics
,1387
&6B',6
/2$'&855(17
6(16(&855(17
W'6(16(+
W'6(16(/
W'6(16(+
W'6(16(/
$*9
Figure 5.
OFF-state open-load delay timing
2XWSXWVWXFNDW9&&
9287!92/
9,1
96(16(+
9&6
W'67.21
*$3*&)7
Figure 6.
Switching characteristics
9287
W:RQ
W:RII
G9287GW RII
G9287GW RQ
WU
WI
W
,1387
WG RQ
WG RII
W
*$3*&)7
Doc ID 022475 Rev. 5
13/37
Electrical specifications
Figure 7.
VN5E160ASO-E
Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
9,1
ǻW'6(16(+
W
,287
,2870$;
,2870$;
W
,6(16(
,6(16(0$;
,6(16(0$;
W
$*9
Figure 8.
Output voltage drop limitation
9&&9287
7M &
7M &
7M &
921
,287
921521 7
$*9
14/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
Electrical specifications
Figure 9.
IOUT/ISENSE vs IOUT
IOUT/ISENSE
620
590
560
A
530
B
500
470
C
440
410
D
380
E
350
320
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6
1.8
IOUT (A)
D: Min, Tj = 25°C to 150°C
E: Min, Tj = -40°C to 150°C
A: Max, Tj = -40°C to 150°C
B: Max, Tj = 25°C to 150°C
C: Typical, Tj = -40°C to 150°C
Figure 10. Maximum current sense ratio drift vs load current(1)
dK/K (%)
15
12
9
A
6
3
0
-3
-6
B
-9
-12
-15
0
0.2
0.4
0.6
0.8
1
1.2
1.4
IOUT (A)
A: Max, Tj = -40°C to 150°C
B: Min, Tj = 25°C to 150°C
1. Parameter guaranteed by design; it is not tested.
Doc ID 022475 Rev. 5
15/37
Electrical specifications
Table 11.
VN5E160ASO-E
Truth table
Conditions
IN
OUT
SENSE (VCSD = 0 V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
H
X
(no power limitation)
Cycling
(power limitation)
Nominal
Overload
H
VSENSEH
Short circuit to GND
(Power limitation)
L
H
L
L
0
VSENSEH
OFF-state open-load
(with external pull-up)
L
H
VSENSEH
1. If the VCSD is high, the SENSE output is at high impedance, its potential depends on leakage currents and
external circuit.
16/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
Electrical specifications
Table 12.
ISO 7637-2:
2004(E)
Electrical transient requirements (part 1)
Test levels(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
Test pulse
III
IV
1
-75 V
-100 V
5000
pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6 V
-7 V
1 pulse
100 ms,
0.01 Ω
5b(2)
+65 V
+87 V
1 pulse
400 ms, 2 Ω
Table 13.
Electrical transient requirements (part 2)
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.
Table 14.
Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 022475 Rev. 5
17/37
Electrical specifications
2.4
VN5E160ASO-E
Waveforms
Figure 11.
Normal operation
1RUPDORSHUDWLRQ
,1387
1RPLQDOORDG
1RPLQDOORDG
,287
96(16(
9&6B',6
$*9
Figure 12. Overload or short to GND
2YHUORDGRU6KRUWWR*1'
,1387
3RZHU/LPLWDWLRQ
, /LP+!
7KHUPDOF\FOLQJ
, /LP/!
,287
96(16(
9&6B',6
$*9
18/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
Electrical specifications
Figure 13. Intermittent overload
,QWHUPLWWHQW2YHUORDG
,1387
2YHUORDG
,/LP+ !
,/LP/ !
1RPLQDOORDG
,287
96(16(+ !
96(16(
9&6B',6
$* 9
Figure 14. OFF-state open-load with external circuitry
2)) 6WDWH2SHQ/RDG
ZLWKH[WHUQDOFLUFXWU\
,1387
9287!92/
9287
92/
,287
96(16(+ !
W'67. RQ
96(16(
9&6B',6
$*9
Doc ID 022475 Rev. 5
19/37
Electrical specifications
VN5E160ASO-E
Figure 15. Short to VCC
6KRUWWR9&&
9287
5HVLVWLYH
6KRUWWR9&&
+DUG
6KRUWWR9&&
92/
9287!92/
,287
W'67. RQ
W'67. RQ
9&6B',6
$*9
Figure 16. Tj evolution in overload or short to GND
7- HYROXWLRQLQ
2YHUORDGRU6KRUWWR*1'
,1387
6HOIOLPLWDWLRQRIIDVWWKHUPDOWUDQVLHQWV
776'
7+Q$@
,LK>X$@
7JO 7
7F> &@
Figure 19. Input voltage clamp
*$3*&)7
9LO>9@
*JO N"
Figure 20. Low-level input voltage
9LFO>9@
7F> &@
*$3*&)7
7F> &@
7F> &@
*$3*&)7
Figure 21. High-level input voltage
*$3*&)7
Figure 22. Hysteresis input voltage
9LK\VW>9@
9LK>9@
7F> &@
7F> &@
*$3*&)7
*$3*&)7
Doc ID 022475 Rev. 5
21/37
Electrical specifications
VN5E160ASO-E
Figure 23. ON-state resistance vs Tcase
Figure 24. ON-state resistance vs VCC
5RQ>P2KP@
5RQ>P2KP@
,RXW $
9FF 9
5D ¡$
5D ¡$
5D ¡$
5D ¡$
7F> &@
*$3*&)7
*$3*&)7
Figure 25. Undervoltage shutdown
Figure 26. Turn-on voltage slope
9XVG>9@
G9RXWGW 2Q>9PV@
9FF 9
5O ȍ
7F> &@
Figure 27. ILIMH vs Tcase
*$3*&)7
Figure 28. Turn-off voltage slope
,OLPK>$@
G9RXWGW 2II>9PV@
9FF 9
7F> &@
*$3*&)7
7F> &@
9FF 9
5O ȍ
7F> &@
*$3*&)7
22/37
9FF>9@
Doc ID 022475 Rev. 5
*$3*&)7
VN5E160ASO-E
Electrical specifications
Figure 29. High-level CS_DIS voltage
Figure 30. CS_DIS voltage clamp
9FVGFO>9@
9FVGK>9@
*JO N"
7F> &@
7F> &@
*$3*&)7
*$3*&)7
Figure 31. Low-level CS_DIS voltage
9FVGO>9@
7F> &@
*$3*&)7
Doc ID 022475 Rev. 5
23/37
Application information
3
VN5E160ASO-E
Application information
Figure 32. Application schematic
9
6 &&
5SURW
&6B',6
'OG
P&
5SURW
,1
287
5SURW
&6
*1'
56(16(
9*1'
&H[W
5*1'
'*1'
*$3*&)7
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to resize the RGND resistor.
1.
RGND ≤ 600 mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0: during reverse battery situations) is:
Equation 1
PD = (-VCC)2 / RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum ON-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output
24/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
Application information
values. This shift varies depending on how many devices are ON in case of several highside drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see Section 3.1.2: Solution 2: a
diode (DGND) in the ground line).
3.1.2
Solution 2: a diode (DGND) in the ground line
A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximux DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than the ones shown in the ISO T/R 7637/1 table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent
the microcontroller I/O pins from latching-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of
microcontroller I/Os.
Equation 2
-VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = - 100 V, Ilatchup ≥ 20 mA, VOHμC ≥ 4.5 V
5 kΩ ≤ Rprot ≤ 180 kΩ.
Recommended values: Rprot =10 kΩ, CEXT = 10 nF.
Doc ID 022475 Rev. 5
25/37
Application information
3.4
VN5E160ASO-E
Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and
diagnostic):
●
Current mirror of the load current in normal operation, delivering a current
proportional to the load current according to a known ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5 V
minimum (see parameter VSENSE in Table 9: Current sense (8 V < VCC < 18 V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 9: Current sense (8 V < VCC < 18 V)).
●
Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a
maximum current ISENSEH in case of the following fault conditions (refer to
Table 11: Truth table):
–
Power limitation activation
–
Overtemperature
–
Short to VCC in OFF-state
–
Open-load in OFF-state with additional external components.
A logic high-level on the CS_DIS pin simultaneously sets all the current sense pins of the
device in a high impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing
the sense resistance and ADC line among different devices.
Figure 33. Current sense and diagnostic
938
9%$7
9&&
-AIN-/3N
9
38B&0'
2YHUWHPSHUDWXUH
,287.;
538
2/2))
,6(16(+
92/
3ZUB/LP
&6B',6
287Q
,/RIIU
,/RIII
,1387Q
96(16(+
&855(17
6(16(Q
53527
7RX&$'&
56(16(
*1'
/RDG
53'
96(16(
*$3*&)7
26/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
3.4.1
Application information
Short to VCC and OFF-state open-load detection
Short to VCC
A short-circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device OFF-state. Little or no current is delivered by the current sense
during the ON-state depending on the nature of the short-circuit.
OFF-state open-load with external circuitry
Detection of an open-load in off-mode requires an external pull-up resistor (RPU) connecting
the output to a positive supply voltage (VPU).
It is preferable that VPU is switched-off during the module standby mode to avoid an
increase in overall standby current consumption in normal conditions, that is, when the load
is connected.
An external pull-down resistor (RPD) connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in OFF-state (see Figure 33: Current sense
and diagnostic).
RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external
circuitry:
Equation 3
RPD ≤ 22 KΩ is recommended.
For proper open load detection in OFF-state, the external pull-up resistor must be selected
according to the following formula:
Equation 4
For the values of VOLmin ,VOLmax, IL(off2)r and IL(off2)f (see Table 10: Open-load detection (8 V
< VCC < 18 V).
Doc ID 022475 Rev. 5
27/37
Application information
3.5
VN5E160ASO-E
Maximum demagnetization energy (VCC = 13.5 V)
Figure 34. Maximum turn-off current versus inductance (for each channel)(1)
A
B
C
, $
/ P+
*$3*&)7
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
9,1,/
'HPDJQHWL]DWLRQ
'HPDJQHWL]DWLRQ
'HPDJQHWL]DWLRQ
W
*$3*&)7
1. Values are generated with RL = 0 Ω.
In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.
28/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
Package and PC board thermal data
4
Package and PC board thermal data
4.1
SO-16L thermal data
Figure 35. SO-16L PC board
("1($'5
Note:
Layout condition of Rth and Zth measurements (PCB: Double Layers, Thermal Vias,FR4
area 77mm x 86 mm, PCB thickness=1.6mm, Cu thickness = 70µm (front and back side),
Copper area from minimum pad lay- out to 24 cm2 ).
Figure 36. Rthj-amb vs PCB copper area in open box free air condition
57+MDPE
57+MDPE
'!0'2)
Doc ID 022475 Rev. 5
29/37
Package and PC board thermal data
VN5E160ASO-E
Figure 37. SO-16L thermal impedance junction ambient single pulse
=7+ &:
&X FP
&X FP
&X IRRWSULQW
7LPH V
'!0'2)
Figure 38. Thermal fitting model of a single channel HSD in SO-16L
'!0'2)
Equation 5: pulse calculation formula:
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
30/37
δ = tp ⁄ T
Doc ID 022475 Rev. 5
VN5E160ASO-E
Package and PC board thermal data
Table 15.
Thermal parameter
Area/island (cm2)
Footprint
R1 (°C/W)
1.2
R2 (°C/W)
4.2
R3 (°C/W)
5
R4 (°C/W)
2
8
8
6
6
R5 (°C/W)
14
13
13
R6 (°C/W)
28
20
14.5
C1 (W.s/°C)
0.0008
C2 (W.s/°C)
0.002
C3 (W.s/°C)
0.1
C4 (W.s/°C)
0.5
C5 (W.s/°C)
1
1.5
1.5
C6 (W.s/°C)
3
9
12
Doc ID 022475 Rev. 5
31/37
Package and packing information
VN5E160ASO-E
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
Package mechanical data
Figure 39. SO-16L package dimensions
("1($'5
32/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
Package and packing information
Table 16.
SO-16L mechanical data
Millimeters
Symbol
Min
Typ
Max
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
10.10
10.50
E
7.40
7.60
e
1.27
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
k
0°
8°
ddd
0.10
Doc ID 022475 Rev. 5
33/37
Package and packing information
5.3
VN5E160ASO-E
Packing information
Figure 40. SO-16L tube shipment (no suffix)
"ASE1TY
"UL K 1 TY
4U BELE N G TH
!
"
#
#
"
!LLDIMENSIO NSAREINMM
!
("1($'5
Figure 41. SO-16L tape and reel shipment (suffix “TR”)
34/37
Doc ID 022475 Rev. 5
VN5E160ASO-E
6
Order codes
Order codes
Table 17.
Device summary
Order codes
Package
SO-16L
Tube
Tape and reel
VN5E160ASO-E
VN5E160ASOTR-E
Doc ID 022475 Rev. 5
35/37
Revision history
7
VN5E160ASO-E
Revision history
Table 18.
36/37
Document revision history
Date
Revision
Changes
14-Dec-2011
1
Initial release.
03-May-2012
2
Update Table 5: Power section
Added Section 4: Package and PC board thermal data
25-Jun-2012
3
Table 4: Thermal data:
– Rthj-pins: removed row
– Rthj-pcb: added row
18-Sep-2012
4
Updated Table 4: Thermal data
18-Sep-2013
5
Updated disclaimer.
Doc ID 022475 Rev. 5
VN5E160ASO-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 022475 Rev. 5
37/37
工商网监
湘ICP备2023018690号
