VNQ830PEP-E

VNQ830PEP-E Quad channel high side driver Features Type VNQ830PEP-E 1. Per each channel. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PowerSSO-24 RDS(on) 60mΩ(1) IOUT 14A(1) VCC 36V CMOS compatible inputs Open drain status outputs On-state open load detection Off-state open load detection Shorted load protection Undervoltage and overvoltage shutdown Loss of ground protection Very low standby current Reverse battery protection(a) In compliance with the 2002/95/EC european directive Description The VNQ830PEP-E is a monolithic device made using| STMicroelectronics VIPower™ M0-3 Technology. The VNQ830PEP-E is intended for driving any type of multiple load with one side connected to ground. The Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects the open load condition in both the on and off-state. In the off-state the device detects if the output is shorted to VCC. The device automatically turns off in the case where the ground pin becomes disconnected. a. See Application schematic on page 16 Table 1. Device summary Package PowerSSO-24 Order codes Tube VNQ830PEP-E Tape and reel VNQ830PEPTR-E July 2009 Doc ID 10871 Rev 7 1/27 www.st.com 1 Contents VNQ830PEP-E Contents 1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 2.3 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 3.1.1 3.1.2 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 17 3.2 3.3 3.4 3.5 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 19 4 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 5.3 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 Doc ID 10871 Rev 7 VNQ830PEP-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 10871 Rev 7 3/27 List of figures VNQ830PEP-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . 20 PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON). . . . . 21 Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 21 PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4/27 Doc ID 10871 Rev 7 VNQ830PEP-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC VCC CLAMP OVERVOLTAGE VCC UNDERVOLTAGE INPUT2 CONTROL & PROTECTION STATUS2 EQUIVALENT TO CHANNEL1 OUTPUT1 GND INPUT1 LOGIC STATUS1 DRIVER 1 CLAMP 1 OUTPUT2 VCC CURRENT LIMITER 1 INPUT3 CONTROL & PROTECTION STATUS3 EQUIVALENT TO CHANNEL1 INPUT2 STATUS2 INPUT3 STATUS3 INPUT4 STATUS4 OVERTEMP. 1 OUTPUT3 OPENLOAD ON 1 VCC OPENLOAD OFF 1 INPUT4 CONTROL & PROTECTION STATUS4 EQUIVALENT TO CHANNEL1 OUTPUT4 Figure 2. Configuration diagram (top view) VCC GND INPUT1 STATUS1 INPUT2 STATUS2 INPUT3 STATUS3 INPUT4 STATUS4 N.C. VCC OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4 TAB = VCC Table 2. Suggested connections for unused and not connected pins Status X N.C. X X Output X Input X Through 10KΩ resistor Connection / pin Floating To ground Doc ID 10871 Rev 7 5/27 Electrical specifications VNQ830PEP-E 2 2.1 Electrical specifications Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC Status current Electrostatic discharge (human body model: R=1.5KΩ; C = 100pF) – Input – Status – Output – VCC Power dissipation (per island) at Tlead = 25°C Junction operating temperature Case operating temperature Storage temperature Absolute maximum ratings Parameter Value 41 - 0.3 - 200 Internally limited - 12 +/- 10 +/- 10 Unit V V mA A A mA mA VESD 4000 4000 5000 5000 83 Internally limited - 40 to 150 - 55 to 150 V V V V W °C °C °C Ptot Tj Tc Tstg 2.2 Thermal data Table 4. Symbol Rthj-case Rthj-amb Thermal data (per island) Parameter Thermal resistance junction-case Thermal resistance junction-ambient (one chip ON) 56(1) Value 1.5 41.7(2) Unit °C/W °C/W 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35 µm thick). Horizontal mounting and no artificial air flow. 2. When mounted on a standard single-sided FR-4 board with 8cm2 of Cu (at least 35 µm thick). Horizontal mounting and no artificial air flow. 6/27 Doc ID 10871 Rev 7 VNQ830PEP-E Electrical specifications 2.3 Electrical characteristics Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise stated. Figure 3. Current and voltage conventions IS VF1 (*) IINn VINn ISTATn VCC INPUTn IOUTn STATUSn OUTPUTn VCC VOUTn GND IGND VSTATn Note: VFn = VCCn - VOUTn during reverse battery condition. Table 5. Symbol VCC VUSD VOV RON Power output Parameter Operating supply voltage Undervoltage shutdown Overvoltage shutdown On-state resistance IOUT = 2A; Tj = 25°C IOUT = 2A; VCC > 8V Off-state; VCC = 13V; VIN = VOUT = 0V Off-state; VCC = 13V; VIN = VOUT = 0V; Tj = 25°C On-state; VCC = 13V; VIN = 5V; IOUT = 0A 20 Test conditions Min. 5.5 3 36 65 120 60 Typ. Max. Unit 13 4 36 5.5 V V V mΩ mΩ µA IS Supply current 20 40 µA 8.5 0 -75 13.5 50 0 mA µA µA IL(off1) IL(off2) Off-state output current VIN = VOUT = 0V Off-state output current VIN = 0V; VOUT = 3.5V Doc ID 10871 Rev 7 7/27 Electrical specifications Table 5. Symbol IL(off3) IL(off4) VNQ830PEP-E Power output (continued) Parameter Off-state output current Off-state output current Test conditions VIN = VOUT = 0V; VCC = 13V; Tj = 125°C VIN = VOUT = 0V; VCC = 13V; Tj = 25°C Min. Typ. Max. Unit 5 3 µA µA Table 6. Symbol TTSD TR Thyst tSDL Ilim Vdemag Protections Parameter Shutdown temperature Reset temperature Thermal hysteresis Status delay in overload conditions Current limitation Turn-off output clamp voltage Tj > TTSD VCC = 13V 5.5V < VCC < 36V IOUT = 2A; L = 6mH 14 18 Test conditions Min. 150 135 7 15 20 23 23 Typ. 175 Max. 200 Unit °C °C °C µs A A V VCC - VCC - VCC 41 48 55 Note: To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 7. Symbol VF VCC - output diode Parameter Forward on voltage Test conditions - IOUT = 1.3A; Tj = 150°C Min. Typ. Max. 0.6 Unit V Table 8. Symbol td(on) td(off) Switching (VCC = 13V; Tj = 25°C) Parameter Turn-on delay time Turn-off delay time Test conditions RL = 6.5Ω from VIN rising edge to VOUT = 1.3V (see Figure 5) RL = 6.5Ω from VIN falling edge to VOUT = 11.7V (see Figure 5) RL = 6.5Ω from VOUT = 1.3V to VOUT = 10.4V (see Figure 5) RL = 6.5Ω from VOUT = 11.7V to VOUT = 1.3V (see Figure 5) Min. Typ. 30 30 See Figure 10 See Figure 12 Max. Unit µs µs V/µs V/µs dVOUT/dt(on) Turn-on voltage slope dVOUT/dt(off) Turn-off voltage slope 8/27 Doc ID 10871 Rev 7 VNQ830PEP-E Table 9. Symbol VIL IIL VIH IIH VI(hyst) VICL Electrical specifications Logic inputs Parameter Input low level Low level input current Input high level High level input current Input hysteresis voltage Input clamp voltage IIN = 1mA IIN = -1mA VIN = 3.25V 0.5 6 6.8 - 0.7 8 VIN = 1.25V 1 3.25 10 Test conditions Min. Typ. Max. 1.25 Unit V µA V µA V V V Table 10. Symbol VSTAT ILSTAT CSTAT VSCL Status pin Parameter Status low output voltage Status leakage current Status pin input capacitance Status clamp voltage Test conditions ISTAT = 1.6mA Normal operation; VSTAT = 5V Normal operation; VSTAT = 5V ISTAT = 1mA ISTAT = - 1mA 6 6.8 - 0.7 Min. Typ. Max. 0.5 10 100 8 Unit V µA pF V V Table 11. Symbol IOL tDOL(on) VOL tDOL(off) Open-load detection Parameter Open-load on-state detection threshold Open-load on-state detection delay Open-load off-state voltage detection threshold Open-load detection delay at turn-off Test conditions VIN = 5V IOUT = 0A VIN = 0V 1.5 2.5 Min. 35 Typ. Max. 70 140 200 3.5 1000 Unit mA µs V µs Figure 4. Status timings OVER TEMP STATUS TIMING Tj > TTSD OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL VINn VINn VSTATn VSTATn tSDL tDOL(off) tDOL(on) tSDL Doc ID 10871 Rev 7 9/27 Electrical specifications Figure 5. Switching characteristics VOUTn 90% 80% VNQ830PEP-E dVOUT/dt(on) 10% dVOUT/dt(off) t VINn td(on) td(off) t Table 12. Truth table Input L H L H H L H L H L H L H L H Output L H L X X L L L L L L H H L H Status H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L Conditions Normal operation Current limitation Overtemperature Undervoltage Overvoltage Output voltage > VOL Output current < IOL 10/27 Doc ID 10871 Rev 7 VNQ830PEP-E Table 13. ISO T/R 7637/1 Test pulse 1 2 3a 3b 4 5 I - 25V + 25V - 25V + 25V - 4V + 26.5V II - 50V + 50V - 50V + 50V - 5V + 46.5V III - 75V + 75V - 100V + 75V - 6V + 66.5V IV - 100V + 100V - 150V + 100V - 7V + 86.5V Electrical specifications Electrical transient requirements (part 1/3) Test level Delays and impedance 2ms, 10Ω 0.2ms, 10Ω 0.1µs, 50Ω 0.1µs, 50Ω 100ms, 0.01Ω 400ms, 2Ω Table 14. ISO T/R 7637/1 Electrical transient requirements (part 2/3) Test level I C C C C C C II C C C C C E III C C C C C E IV C C C C C E Test pulse 1 2 3a 3b 4 5 Table 15. Class C E Electrical transient requirements (part 3/3) Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Doc ID 10871 Rev 7 11/27 Electrical specifications Figure 6. Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VCC INPUTn OUTPUT VOLTAGEn STATUSn undefined OVERVOLTAGE VCCVOL VCC>VOV VUSD VUSDhyst VNQ830PEP-E Tj INPUTn TTSD TR OUTPUT CURRENTn STATUSn 12/27 Doc ID 10871 Rev 7 VNQ830PEP-E Electrical specifications 2.4 Figure 7. Electrical characteristics curves Off-state output current Figure 8. Iih (µA) 8 7 High level input current IL (off1) (µA) 2.8 2.45 2.1 1.75 1.4 1.05 0.7 0.35 0 -50 -25 0 25 50 75 100 125 150 175 Vcc=36 6 5 4 3 2 1 0 -50 Vcc=13V Vin=3.25V -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 9. Vicl (V) 8 7.8 Input clamp voltage Figure 10. Turn-on voltage slope dVout/dt (on) (V/ms) 0.9 0.8 0.7 0.6 0.5 Iin=1mA 7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 Vcc=13V Rl=6.5Ohm 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 11. Vov (V) 50 47.5 45 Overvoltage shutdown Figure 12. Turn-off voltage slope dVout/dt (off) (V/ms) 0.5 0.45 0.4 0.35 Vcc=13V Rl=6.5Ohm 42.5 40 37.5 35 0.3 0.25 0.2 0.15 0.1 32.5 30 -50 -25 0 25 50 75 100 125 150 175 0.05 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Doc ID 10871 Rev 7 13/27 Electrical specifications Figure 13. ILIM vs Tcase Ilim (A) 26 24 VNQ830PEP-E Figure 14. On-state resistance vs VCC Ron (mOhm) 180 160 Vcc=13V 22 20 18 Iout=2A 140 Tc=150°C 120 100 80 16 14 12 10 -50 -25 0 25 50 75 100 125 150 175 Tc=25°C 60 40 20 0 0 5 10 15 20 25 30 35 40 Tc=-40°C Tc (°C) Vcc (V) Figure 15. Input high level Figure 16. Input hysteresis voltage Vih(V) 4 3.8 3.6 Vhyst (V) 1.6 1.4 1.2 3.4 3.2 3 2.8 2.6 0.4 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175 0.2 0 -50 -25 0 25 50 75 100 125 150 175 1 0.8 0.6 Tc (°C) Tc (°C) Figure 17. On-state resistance vs Tcase Ron (mOhm) 160 140 120 100 80 60 40 Figure 18. Input low level Vil (V) 4 3.6 Iout=2A Vcc=8v; 13V; 36V 3.2 2.8 2.4 2 1.6 1.2 0.8 20 0 -50 -25 0 25 50 75 100 125 150 175 0.4 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) 14/27 Doc ID 10871 Rev 7 VNQ830PEP-E Figure 19. Status leakage current Istat (nA) 300 270 Electrical specifications Figure 20. Status low output voltage Vstat (V) 0.8 0.7 Vstat=5V 240 210 180 150 120 90 Istat=1.6mA 0.6 0.5 0.4 0.3 0.2 60 30 0 -50 -25 0 25 50 75 100 125 150 175 0.1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 21. Status clamp voltage Figure 22. Open-load on-state detection threshold Iol (mA) 0.13 0.12 Vscl (V) 8 7.8 7.6 7.4 7.2 Iin=1mA Vcc=13V 0.11 0.1 0.09 7 0.08 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 0.07 0.06 0.05 0.04 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 23. Open-load off-state voltage detection threshold Vol (V) 3.8 3.6 Vin=0V 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 10871 Rev 7 15/27 Application information VNQ830PEP-E 3 Application information Figure 24. Application schematic +5V +5V VCC Rprot STATUSn Dld μC Rprot INPUTn OUTPUTn GND VGND RGND DGND 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: a resistor in the ground line (RGND only) This can be used with any type of load. The following show how to dimension the RGND resistor: 1. 2. RGND ≤ 600mV / 2 (IS(on)max) RGND ≥ ( - VCC) / (- IGND) where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = (- VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. 16/27 Doc ID 10871 Rev 7 VNQ830PEP-E Application information Please note that, if the microprocessor ground is not shared by the device ground, then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/O pins from latching up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os: - VCCpeak / Ilatchup ≤ Rprot ≤ (VOHμC - VIH - VGND) / IIHmax Example For the following conditions: VCCpeak = - 100V Ilatchup ≥ 20mA VOHμC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended values are: Rprot = 10kΩ Doc ID 10871 Rev 7 17/27 Application information VNQ830PEP-E 3.4 Open-load detection in off-state Off-state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL + RPU))RL < VOlmin. 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. Figure 25. Open-load detection in off-state V batt. VCC RPU INPUT DRIVER + LOGIC OUT + STATUS VOL R IL(off2) VPU RL GROUND 18/27 Doc ID 10871 Rev 7 VNQ830PEP-E Application information 3.5 Maximum demagnetization energy (VCC = 13.5V) Figure 26. Maximum turn-off current versus load inductance ILMAX (A) 100 10 A B C 1 0.01 0.1 1 L(mH) 10 100 A = single pulse at TJstart = 150ºC B= repetitive pulse at TJstart = 100ºC C= repetitive pulse at TJstart = 125ºC VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL = 0Ω. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. Doc ID 10871 Rev 7 19/27 Package and PC board thermal data VNQ830PEP-E 4 4.1 Package and PC board thermal data PowerSSO-24 thermal data Figure 27. PowerSSO-24 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 78 mm x 78 mm, PCB thickness=2 mm, Cu thickness=70 mm (front and back side), Copper areas: from minimum pad lay-out to 8 cm2). Figure 28. Rthj-amb vs PCB copper area in open box free air condition (one channel ON) RTHj_amb(°C/W) 60 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 20/27 Doc ID 10871 Rev 7 VNQ830PEP-E Package and PC board thermal data Figure 29. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON) ZTH (°C/W) 100 Footprint 8 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 30. Thermal fitting model of a double channel HSD in PowerSSO-24 (b) b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Doc ID 10871 Rev 7 21/27 Package and PC board thermal data Equation 1: pulse calculation formula: Z TH δ =R TH ⋅δ+Z THtp (1 – δ) VNQ830PEP-E where δ = tP/T Table 16. Thermal parameters Area/island (cm2) R1 = R7 = R9 = R11 (°C/W) R2 = R8 = R10 = R12 (°C/W) R3 (°C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 = C7 = C9 = C11 (W.s/°C) C2 = C8 = C10 = C12 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) Footprint 0.1 0.9 1 4 13.5 37 0.0006 0.0025 0.025 0.08 0.7 3 8 22 5 22/27 Doc ID 10871 Rev 7 VNQ830PEP-E Package and packing information 5 5.1 Package and packing information ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 PowerSSO-24 mechanical data Figure 31. PowerSSO-24 package dimensions Doc ID 10871 Rev 7 23/27 Package and packing information Table 17. PowerSSO-24 mechanical data(1) (2) Millimeters Symbol Min. A A2 a1 b c D (3) VNQ830PEP-E Typ. Max. 2.45 2.15 0 0.33 0.23 10.10 7.40 0.8 8.8 2.3 2.35 0.10 0.51 0.32 10.50 7.60 E(3) e e3 F G G1 H h k L O Q S T U N X Y 0.1 0.06 10.1 10.5 0.4 0° 0.55 1.2 0.8 2.9 3.65 1 10º 4.1 6.5 4.9(4) 4.7 7.1 5.5(4) 8° 0.85 1. No intrusion allowed inwards the leads. 2. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side 3. “D and E” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15 mm. 4. Variations for small window lead frame option. 24/27 Doc ID 10871 Rev 7 VNQ830PEP-E Package and packing information 5.3 Packing information Figure 32. PowerSSO-24 tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) 49 1225 532 3.5 13.8 0.6 C B All dimensions are in mm. A Figure 33. PowerSSO-24 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 (± 0.1) P D (± 0.05) D1 (min) F (± 0.1) K (max) P1 (± 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets saled with cover tape. User direction of feed Doc ID 10871 Rev 7 25/27 Revision history VNQ830PEP-E 6 Revision history Table 18. Date 10-Nov-2004 22-Nov-2006 07-Dec-2004 04-May-2005 03-May-2006 Document revision history Revision 1 2 3 4 5 Initial release. Pdf changed. Mechanical data updating. PowerSSO-24 thermal characterization insertion PCB copper area correction. Changed document status from preliminary to definitive. Configuration diagram modification Shipment data insertion Document reformatted and restructured. Added list of contents, tables and figures. Added ECOPACK® packages information. Update PowerSSO-24 mechanical data. Table 17: PowerSSO-24 mechanical data: – Deleted A (min) value – Changed A (max) value from 2.50 to 2.45 – Changed A2 (max) value from 2.40 to 2.35 – Updated k values – Changed L (min) value from 0.6 to 0.55 – Changed L (max) value from 1 to 0.85 Changes 26-Nov-2008 6 01-Jul-2009 7 26/27 Doc ID 10871 Rev 7 VNQ830PEP-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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