VNQ830PTR-E

VNQ830P-E Quad channel high-side driver Datasheet - production data  Undervoltage shutdown  Overvoltage clamp  Output stuck to VCC detection  Load current limitation  Reverse battery protection  Electrostatic discharge protection 62GRXEOHLVODQG Description *$3*36 The VNQ830P-E is a quad HSD formed by assembling two VND830P-E chips in the same SO-28 package. The VND830P-E is a monolithic device made using| STMicroelectronics™ VIPower™ M0-3 technology. The VNQ830P-E is intended for driving any type of multiple load with one side connected to ground. Features Type RDS(on) IOUT VCC VNQ830P-E 65 mΩ(1) 6A 36V 1. Per each channel. The active VCC pin voltage clamp protects the device against low energy spikes. Active current limitation combined with thermal shutdown and automatic restart protects the device against over-load. The device detects the open-load condition in both the on and off-state.  ECOPACK®: lead free and RoHS compliant  Automotive Grade: compliance with AEC guidelines  Very low standby current In the off-state the device detects if the output is shorted to VCC. The device automatically turns off in the case where the ground pin becomes disconnected.  CMOS compatible input  On-state open-load detection  Off-state open-load detection  Thermal shutdown protection and diagnosis Table 1. Device summary Order codes Package SO-28 February 2015 This is information on a product in full production. Tube Tape and reel VNQ830P-E VNQ830PTR-E DocID10861 Rev 6 1/28 www.st.com Contents VNQ830P-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 4 6 2/28 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 17 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 18 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 20 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 SO-28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID10861 Rev 6 VNQ830P-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID10861 Rev 6 3/28 3 List of figures VNQ830P-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. 4/28 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 [Figure title] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22 SO-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal fitting model of a quad channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DocID10861 Rev 6 VNQ830P-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram 9&& 9FF 29(592/7$*( &/$03 81'(592/7$*( *1' &/$03 287387 ,1387 67$786 '5,9(5 &/$03  &855(17/,0,7(5 /2*,& '5,9(5 287387 29(57(03 23(1/2$'21 &855(17/,0,7(5 ,1387 23(1/2$'2)) 23(1/2$'21 67$786 23(1/2$'2)) 29(57(03 9&& 9FF &/$03 29(592/7$*( 81'(592/7$*( *1' &/$03 ,1387 287387 '5,9(5 &/$03 67$786 29(57(03 /2*,& &855(17/,0,7(5 '5,9(5 287387 23(1/2$'21 &855(17/,0,7(5 ,1387 23(1/2$'2)) 23(1/2$'21 67$786 23(1/2$'2)) 29(57(03 *$3*36 DocID10861 Rev 6 5/28 27 Block diagram and pin description VNQ830P-E Figure 2. Configuration diagram (top view)     9&& 9&& *1' 287387 ,1387 287387 67$786 287387 67$786 287387 ,1387 287387 9&& 287387 9&& 287387 *1' 287387 ,1387 287387 67$786 287387 67$786 287387 ,1387 287387 9&&   9&& *$3*36 Table 2. Suggested connections for unused and not connected pins Connection / pin Status N.C. Output Input Floating X X X X To ground 6/28 X DocID10861 Rev 6 Through 10 KΩ resistor VNQ830P-E Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol VCC Parameter DC supply voltage Value Unit 41 V - VCC Reverse DC supply voltage -0.3 V - IGND DC reverse ground pin current -200 mA Internally limited A -6 A IOUT - IOUT DC output current Reverse DC output current IIN DC input current ±10 mA ISTAT DC status current ±10 mA VESD Electrostatic discharge (Human Body Model: R=1.5 KΩ; C = 100 pF) – INPUT – STATUS – OUTPUT – VCC 4000 4000 5000 5000 V V V V EMAX Maximum switching energy (L = 1.5 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; IL = 9 A) 140 mJ Power dissipation (per island) at Tlead = 25 °C 6.25 W Internally limited °C - 55 to 150 °C Ptot Tj Tstg Junction operating temperature Storage temperature DocID10861 Rev 6 7/28 27 Electrical specifications 2.2 VNQ830P-E Thermal data Table 4. Thermal data (per island) Symbol Parameter Value Unit 15 °C/W Rthj-lead Thermal resistance junction-lead Rthj-amb Thermal resistance junction-ambient (one chip ON) 60(1) 44(2) °C/W Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 31(2) °C/W 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35 μm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35μm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2.3 Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40°C < Tj < 150°C, unless otherwise stated. Figure 3. Current and voltage conventions ,6 ,6 9&& 9&& 9&& 9) 9&& ,,1 ,67$7 9,1 ,,1 967$7 ,67$7  9,1 ,,1 967$7  ,67$7  9,1 967$7  ,,1 9,1 ,67$7 967$7 ,1387 ,287 67$786 287387 9287 ,287 ,1387 287387 67$786 9287 ,287 ,1387 287387 67$786 ,287 ,1387 287387 67$786 *1' 9287 9287 *1' ,*1' ,*1' *$3*36 1. VFn = VCCn - VOUTn during reverse battery condition. Table 5. Power Symbol 8/28 Parameter VCC Operating supply voltage VUSD VOV Test conditions Min. Typ. Max. Unit 5.5 13 36 V Undervoltage shutdown 3 4 5.5 V Overvoltage shutdown 36 DocID10861 Rev 6 V VNQ830P-E Electrical specifications Table 5. Power (continued) Symbol RON IS Parameter Test conditions Min. Typ. Max. Unit IOUT = 2 A; Tj = 25°C IOUT = 2 A; VCC > 8 V On-state resistance Supply current 65 130 mΩ mΩ Off-state; VCC = 13 V; VIN = VOUT = 0 V 12 40 μA Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25°C 12 25 μA On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A 5 7 mA 0 50 μA -75 0 μA IL(off1) Off-state output current VIN = VOUT = 0 V IL(off2) Off-state output current VIN = 0V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0V; VCC = 13 V; Tj = 125°C 5 μA IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj =25°C 3 μA Table 6. Protections Symbol Min. Typ. Max. Unit Shutdown temperature 150 175 200 °C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload conditions Ilim Current limitation TTSD Vdemag Note: Parameter Test conditions °C 15 °C Tj > TTSD VCC = 13 V 6 9 5.5 V < VCC < 36 V Turn-off output clamp voltage IOUT = 2 A; L = 6 mH VCC -41 20 μs 15 A 15 A VCC -48 VCC -55 V To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 7. VCC - output diode Symbol Parameter Test conditions VF Forward on voltage - IOUT = 1.2 A; Tj = 150°C DocID10861 Rev 6 Min. Typ. Max. Unit — — 0.6 V 9/28 27 Electrical specifications VNQ830P-E Table 8. Switching (VCC = 13V; Tj = 25°C) Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 6.5 Ω from VIN rising edge to VOUT = 1.3 V (see Figure 5) — 30 — μs td(off) Turn-off delay time RL = 6.5 Ωfrom VIN falling edge to VOUT = 11.7 V (see Figure 5) — 30 — μs dVOUT/dt(on) Turn-on voltage slope RL = 6.5 Ωfrom VOUT = 1.3 V to VOUT = 10.4 V (see Figure 5) — See Figure 10 — V/μs dVOUT/dt(off) Turn-off voltage slope RL = 6.5 Ωfrom VOUT = 11.7 V to VOUT = 1.3 V (see Figure 5) — See Figure 12 — V/μs Table 9. Logic inputs Symbol Parameter Test conditions VIL Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN = 1.25 V Min. Typ. Max. Unit 1.25 V 1 μA 3.25 V VIN = 3.25 V 10 0.5 IIN = 1 mA Input clamp voltage 6 IIN = -1 mA μA V 6.8 8 -0.7 V V Table 10. Status pin Symbol 10/28 Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT = 1.6 mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 μA CSTAT Status pin input capacitance Normal operation; VSTAT = 5 V 100 pF VSCL Status clamp voltage 8 V ISTAT = 1 mA ISTAT = - 1 mA DocID10861 Rev 6 6 6.8 -0.7 V VNQ830P-E Electrical specifications Table 11. Open-load detection Symbol Parameter Test conditions IOL Open-load on-state detection VIN = 5 V threshold tDOL(on) Open-load on-state detection IOUT = 0 A delay VOL Open-load off-state voltage detection threshold tDOL(off) Open-load detection delay at turn-off Min. Typ. Max. Unit 50 100 200 mA 200 μs 3.5 V 1000 μs VIN = 0 V 1.5 2.5 Figure 4. Status timings 23(1/2$'67$7867,0,1*ZLWKH[WHUQDOSXOOXS ,287,2/ 9287!92/ 29(57(0367$7867,0,1* 7M!776' 9,1Q 9,1Q 967$7Q 967$7Q W6'/ W'2/RII W6'/ W'2/RQ *$3*36 Figure 5. Switching characteristics 9287   G9287GWRII G9287GWRQ  W 9,1Q WGRQ WGRII W *$3*36 DocID10861 Rev 6 11/28 27 Electrical specifications VNQ830P-E Table 12. Truth table Conditions Input Output Status Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L Table 13. Electrical transient requirements ISO T/R Test level 7637/1 test pulse I II III IV Delays and impedance 1 -25 V(1) -50 V(1) -75 V(1) -100 V(1) 2 ms, 10 Ω 2 (1) +50 V(1) +75 V(1) +100 V(1) 0.2 ms, 10 Ω -50 V(1) -100 V(1) -150 V(1) 0.1 μs, 50 Ω +50 V(1) +75 V(1) +100 V(1) 0.1 μs, 50 Ω 3a 3b 4 5 +25 V (1) -25 V (1) +25 V -4 V(1) (1) +26.5 V -5 V(1) +46.5 V (2) -6 V(1) +66.5 V (2) -7 V(1) (2) +86.5 V 100 ms, 0.01 Ω 400 ms, 2 Ω 1. All functions of the device are performed as designed after exposure to disturbance. 2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 12/28 DocID10861 Rev 6 VNQ830P-E Electrical specifications Figure 6. Waveforms 1RUPDORSHUDWLRQ ,1387Q 28738792/7$*(Q 67$786Q 8QGHUYROWDJH 986'K\VW 9&& 986' ,1387Q 28738792/7$*(Q 67$786Q XQGHILQHG 2YHUYROWDJH 9&&929 9&&!929 9&& ,1387Q 28738792/7$*(Q 67$786Q 2SHQORDGZLWKH[WHUQDOSXOOXS ,1387Q 9287!92/ 28738792/7$*(Q 92/ 67$786Q 2SHQORDGZLWKRXWH[WHUQDOSXOOXS ,1387Q 28738792/7$*(Q 67$786Q 7M 776' 75 2YHUWHPSHUDWXUH ,1387Q 28738792/7$*(Q 67$786Q *$3*36 DocID10861 Rev 6 13/28 27 Electrical specifications 2.4 VNQ830P-E Electrical characteristics curves Figure 7. Off-state output current ,/RII—$ Figure 8. High level input current ,LK—$     2IIVWDWH 9FF 9 9LQ 9RXW 9   9LQ 9                            7Fƒ&         7Fƒ& *$3*36 Figure 9. Input clamp voltage  *$3*36 Figure 10. Turn-on voltage slope G9RXWGWRQ9PV 9LFO9     ,LQ P$  9FF 9 5O 2KP                                   7Fž& 7Fƒ& Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope 9RY9 G9RXWGWRII9PV     *$3*36 *$3*36  9FF 9 5O 2KP                       7Fƒ& 14/28     *$3*36 DocID10861 Rev 6           7Fž& *$3*36 VNQ830P-E Electrical specifications Figure 13. ILIM vs Tcase Figure 14. On-state resistance vs VCC ,OLP$ 5RQP2KP   7F ƒ&    9FF 9         7F ƒ&     7F ƒ&     ,RXW $             7Fƒ&      Figure 15. Input high level    9FF9 *$3*36  *$3*36 Figure 16. Input hysteresis voltage 9LK9 9K\VW9                              7F ƒ&          *$3*36 Figure 18. Input low level 5RQP2KP 9LO9    ,RXW $ 9FF 99 9   7Fƒ& Figure 17. On-state resistance vs Tcase   *$3*36                    7Fƒ&     *$3*36 DocID10861 Rev 6       7F ƒ&     *$3*36 15/28 27 Electrical specifications VNQ830P-E Figure 19. Status leakage current Figure 20. Status low output voltage ,OVWDW—$ 9VWDW9    ,VWDW P$   9VWDW  9                    7Fƒ&           *$3*36 Figure 21. Status clamp voltage Figure 22. [Figure title] ,ROP$ 9VFO9     ,VWDW P$                  9FF 9 9LQ 9           7Fƒ&        7Fƒ& *$3*36 Figure 23. Open-load off-state voltage detection threshold 9RO9   9LQ 9                    7F ƒ& *$3*36 16/28  7Fƒ& *$3*36 DocID10861 Rev 6     *$3*36 VNQ830P-E 3 Application information Application information Figure 24. Application schematic 9 9 9 9&& 9&& 5SURW 67$786 5SURW ,1387 'OG 5SURW 67$786 5SURW ,1387 5SURW 67$786 287387 —& 5SURW 287387 287387 ,1387 5SURW 67$786 287387 5SURW ,1387 *1' *1' 5*1' 9*1' 9 9 '*1' *$3*36 Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: a resistor in the ground line (RGND only) This can be used with any type of load. The following show how to dimension the RGND resistor: 1. RGND ≤ 600 mV / 2 (IS(on)max) 2. RGND ≥-VCC) / ( - IGND) DocID10861 Rev 6 17/28 27 Application information VNQ830P-E where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = ( - VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high-side drivers sharing the same RGND . If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1 k) should be inserted in parallel to DGND if the device is driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network produces a shift (~600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift not varies if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in Table 13. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os: - VCCpeak / Ilatchup ≤ Rprot ≤ (VOHC - VIH - VGND) / IIHmax 18/28 DocID10861 Rev 6 VNQ830P-E Application information Example For the following conditions: VCCpeak = - 100 V Ilatchup ≥ 20 mA VOHC ≥ 4.5 V 5 kΩ ≤ Rprot ≤ 65 kΩ. Recommended values are: Rprot = 10 kΩ 3.4 Open-load detection in off-state Off-state open-load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5 V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. No false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition: VOUT = (VPU / (RL + RPU))RL < VOlmin. 2. No misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition: RPU < (VPU - VOLmax) / IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. Figure 25. Open-load detection in off-state 9EDWW 938 9&& 538 ,1387 '5,9(5  /2*,& ,/RII  287  5 67$7 86  92/ 5/ *5281' *$3*36 DocID10861 Rev 6 19/28 27 Application information 3.5 VNQ830P-E Maximum demagnetization energy (VCC = 13.5 V) Figure 26. Maximum turn-off current versus load inductance ,/0 $;$   $ % &        /P+ $ VLQJOHSXOVHDW7-VWDUW  ž& % UHSHWLWLYHSXOVHDW7 -VWDUW  ž& & UHSHWLWLYHSXOVHDW7-VWDUW  ž& 9,1,/ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ W *$3*36 Note: Values are generated with RL = 0 Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 20/28 DocID10861 Rev 6 VNQ830P-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 SO-28 thermal data Figure 27. SO-28 PC board *$3*36 Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 μm, Copper areas: 0.5 cm2, 3 cm2, 6 cm2). Table 14. Thermal calculation according to the PCB heatsink area Chip 1 Chip 2 Tjchip1 Tjchip2 Note ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb ON ON RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2 ON ON (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1 Pdchip2 RthA = thermal resistance junction to ambient with one chip ON RthB = thermal resistance junction to ambient with both chips ON and Pdchip1 = Pdchip2 RthC = mutual thermal resistance DocID10861 Rev 6 21/28 27 Package and PCB thermal data VNQ830P-E Figure 28. Rthj-amb vs PCB copper area in open box free air condition 57+MBDP E ƒ&:    5WK$  5WK%   5WK&        3&%&XKHDWVLQNDUHDFP ALVODQG   *$3*36 Figure 29. SO-28 thermal impedance junction ambient single pulse =7 +ƒ&: :   )RRWSULQW FP FP           7 LPH V Equation 1: pulse calculation formula Z TH = R TH   + Z THtp  1 –   where 22/28  = tp  T DocID10861 Rev 6    *$3*36 VNQ830P-E Package and PCB thermal data Figure 30. Thermal fitting model of a quad channel HSD in SO-28 7MB 3 G 7MB & & & & & & 5 5 5 5 5 5 &  &  & &  5  & 5  3 G 5  7MB 5  & & & 5 5 5 3 G 7MB 3 G &  5  5  5  5  &  5  7 BD P E *$3*36 Table 15. Thermal parameters Area / island (cm2) Footprint R1 = R7 = R13 = R15 (°C/W) 0.15 R2 = R8 = R14 = R16 (°C/W) 0.7 R3 = R9 (°C/W) 1.8 R4 = R10 (°C/W) 10 R5 = R11 (°C/W) 15 R6 = R12 (°C/W) 30 C1 = C7 = C13 = C15 (W.s/°C) 0.0005 C2 = C8 = C14 = C16 (W.s/°C) 3E-03 C3 = C9 (W.s/°C) 1.50E-02 C4 = C10 (W.s/°C) 0.15 C5 = C11 (W.s/°C) 1.5 C6 = C12 (W.s/°C) 5 R17 = R18 (°C/W) 150 DocID10861 Rev 6 6 13 8 23/28 27 Package information 5 VNQ830P-E Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 SO-28 package information Figure 31. SO-28 package outline ' % GGG F $ $ K[ƒ &  6($7,1* 3/$1(  PP *$*(3/$1(   3,1 ,'(17,),&$7,21 N $ ( + & / H *$3*36 Table 16. SO-28 mechanical data Dimensions Ref. Millimeters Min. 24/28 Typ. Max. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D(1) 17.70 18.10 DocID10861 Rev 6 VNQ830P-E Package information Table 16. SO-28 mechanical data Dimensions Ref. Millimeters Min. E Typ. 7.40 e Max. 7.60 1.27 H 10.0 10.65 h 0.25 0.75 L 0.40 1.27 k 0° 8° ddd 0.10 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. DocID10861 Rev 6 25/28 27 Package information 5.2 VNQ830P-E SO-28 packing information Figure 32. SO-28 tube shipment (no suffix) & % %DVH4W\ %XON4W\ 7XEHOHQJWK“ $ % &“       $OOGLPHQVLRQVDUHLQPP $ *$3*36 Figure 33. SO-28 tape and reel shipment (suffix “TR”) 26/28 DocID10861 Rev 6 VNQ830P-E 6 Revision history Revision history Replaced Table 17. Document revision history Date Revision 03-May-2006 1 Initial release. 18-Dec-2008 2 Document reformatted and restructured. Added contents, list of tables and figures. Added ECOPACK® packages information. 03-May-2010 3 Changed Features list. Replaced VND830P-E to VND830-E. 07-Feb-2011 4 Table 3: Absolute maximum ratings – EMAX: updated value Updated Figure 5: Switching characteristics Updated Table 15: Thermal parameters 19-Sep-2013 5 Updated Disclaimer. 6 Updated: – Section 5.1: SO-28 package information; – Tape dimensions in Figure 33: SO-28 tape and reel shipment (suffix “TR”) on page 26. 16-Feb-2015 Changes DocID10861 Rev 6 27/28 27 VNQ830P-E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 28/28 DocID10861 Rev 6