IRL520L, SiHL520L
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
D
I2PAK (TO-262)
• Dynamic dV/dt rating
• Repetitive avalanche rated
Available
• Logic-level gate drive
G
D
S
G
• RDS (on) specified at VGS = 4 V and 5 V
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Available
• 175°C operating temperature
100
VGS = 5 V
0.27
Qg (Max.) (nC)
12
Qgs (nC)
3.0
Qgd (nC)
7.1
Configuration
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
Single
The I2PAK (TO-262) is a through hole power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface-mount package.
ORDERING INFORMATION
I2PAK (TO-262)
Package
Lead (Pb)-free and Halogen-free
SiHL520L-GE3
Lead (Pb)-free
IRL520LPbF
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
100
Gate-Source Voltage
VGS
± 10
Continuous Drain Current
VGS at 5 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
UNIT
V
9.2
6.5
A
36
Linear Derating Factor
0.40
Linear Derating Factor (PCB Mount)e
0.025
W/°C
Single Pulse Avalanche Energyb
EAS
170
Avalanche Currenta
IAR
9.2
A
Repetiitive Avalanche Energya
EAR
6.0
mJ
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
For 10 s
mJ
PD
60
W
dV/dt
5.5
V/ns
TJ, Tstg
- 55 to + 175
300d
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 3.0 mH, RG = 25 , IAS = 9.2 A (see fig. 12)
c. ISD 9.2 A, dI/dt 110 A/μs, VDD VDS, TJ 175 °C
d. 1.6 mm from case
S21-0932-Rev. B, 13-Sep-2021
Document Number: 91467
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL520L, SiHL520L
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
SYMBOL
TYP.
MAX.
UNIT
RthJA
RthJC
-
62
2.5
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
VDS/TJ
VGS(th)
IGSS
Zero Gate Voltage Drain Current
IDSS
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Dynamic
Internal Drain Inductance
Internal Source Inductance
RDS(on)
gfs
Ciss
Coss
Crss
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
LS
TEST CONDITIONS
VGS = 0, ID = 250 μA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 μA
VGS = ± 10 V
VDS = 100 V, VGS = 0 V
VDS = 80 V, VGS = 0 V, TJ = 150 °C
ID = 5.5 Ab
VGS = 5 V
ID = 4.6 Ab
VGS = 4 V
VDS = 50 V, ID = 5.5 Ab
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 5 V
ID = 9.2 A, VDS = 80 V,
see fig. 6 and 13b
VDD = 50 V, ID = 9.2 A,
RG = 9 , RD = 5.2 , see fig. 10b
Between lead,
6 mm (0.25") from
package and center of
die contact
D
MIN.
TYP.
MAX.
UNIT
100
1.0
3.2
0.12
-
2.0
± 100
25
250
0.27
0.38
-
V
V/°C
V
nA
-
490
150
30
9.8
64
21
27
12
3.0
7.1
-
-
4.5
-
-
7.5
-
-
-
9.2
-
-
36
μA
S
pF
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
VSD
trr
Qrr
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 9.2 A, VGS = 0 Vb
2.5
V
130
190
ns
TJ = 25 °C, IF = 9.2 A, dI/dt = 100 A/μsb
0.83
1.0
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width 300 μs; duty cycle 2 %
S21-0932-Rev. B, 13-Sep-2021
Document Number: 91467
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL520L, SiHL520L
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Transfer Characteristics
Fig. 3 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics, TC = 150 °C
S21-0932-Rev. B, 13-Sep-2021
Document Number: 91467
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL520L, SiHL520L
www.vishay.com
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0932-Rev. B, 13-Sep-2021
Vishay Siliconix
Fig. 6 - Typical Source-Drain Diode Forward Voltage
Fig. 7 - Maximum Safe Operating Area
Document Number: 91467
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL520L, SiHL520L
www.vishay.com
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
5V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
Fig. 8 - Maximum Drain Current vs. Case Temperature
10 %
VGS
td(on)
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 9 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0932-Rev. B, 13-Sep-2021
Document Number: 91467
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL520L, SiHL520L
www.vishay.com
Vishay Siliconix
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
RG
+
-
I AS
V DD
VDS
5V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
5V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0932-Rev. B, 13-Sep-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91467
6
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL520L, SiHL520L
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 10 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?94167.
S21-0932-Rev. B, 13-Sep-2021
Document Number: 91467
7
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Revision: 01-Jan-2022
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Document Number: 91000