SI2307CDS-T1-GE3

New Product Si2307CDS Vishay Siliconix P-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A)a, b 0.088 at VGS = - 10 V - 2.7 0.138 at VGS = - 4.5 V - 2.2 VDS (V) - 30 Qg (Typ.) APPLICATIONS COMPLIANT • Load Switch for Portable Devices 1 3 S RoHS 4.1 nC TO-236 (SOT-23) G • Halogen-free Option Available • TrenchFET® Power MOSFET D S 2 G Top View Si2307CDS (N7)* * Marking Code D Ordering Information: Si2307CDS-T1-E3 (Lead (Pb)-free) Si2307CDS-T1-GE3 (Lead (Pb)-free and Halogen-free) P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol Limit Drain-Source Voltage VDS - 30 Gate-Source Voltage VGS ± 20 TC = 25 °C Continuous Drain Current (TJ = 150 °C)a, b TC = 70 °C TA = 25 °C Continuous Source-Drain Diode Currenta, b - 2.8 ID - 2.7a, b - 2.2a, b IDM Maximum Power Dissipationa, b TC = 25 °C TA = 25 °C - 1.5 IS - 0.91a, b 1.8 TC = 70 °C 1.14 PD Soldering Recommendations (Peak W 1.1a, b 0.7a, b TA = 70 °C TJ, Tstg Operating Junction and Storage Temperature Range A - 12 TC = 25 °C TA = 25 °C V - 3.5 TA = 70 °C Pulsed Drain Current (10 µs Pulse Width) Unit - 55 to 150 Temperature)c °C 260 THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Maximum Junction-to-Ambienta, c t≤5s RthJA 90 115 Maximum Junction-to-Foot (Drain) Steady State RthJF 55 70 Unit °C/W Notes: a. Surface Mounted on 1" x 1" FR4 board. b. t = 5 s. c. Maximum under Steady State conditions is 166 °C/W. Document Number: 68768 S-81580-Rev. A, 07-Jul-08 www.vishay.com 1 New Product Si2307CDS Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = - 250 µA - 30 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS Temperature Coefficient ΔVDS/TJ VGS(th) Temperature Coefficient ΔVGS(th)/TJ Gate-Source Threshold Voltage ID = - 250 µA VGS(th) VDS = VGS, ID = - 250 µA Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Drain-Source On-State Resistancea Forward Transconductancea gfs mV/°C 4.5 -1 -3 V - 100 nA VDS = - 30 V, VGS = 0 V -1 VDS = - 30 V, VGS = 0 V, TJ = 55 °C - 10 VDS ≤ 5 V, VGS = - 10 V RDS(on) V - 32 -6 µA A VGS = - 10 V, ID = - 3.5 A 0.073 0.088 VGS = - 4.5 V, ID = - 2.5 A 0.110 0.138 VDS = - 10 V, ID = - 3.5 A 7 Ω S b Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 51 Total Gate Charge Qg 4.1 Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time 340 VDS = - 15 V, VGS = 0 V, f = 1 MHz VDS = - 15 V, VGS = - 4.5 V, ID = - 2.5 A pF 67 6.2 1.3 nC 1.8 f = 1 MHz td(on) VDD = - 15 V, RL = 15 Ω ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 1 Ω tr td(off) Ω 10 40 60 40 60 20 40 tf 17 30 td(on) 5.5 10 13 25 17 30 7.7 15 VDD = - 15 V, RL = 15 Ω ID ≅ - 1 A, VGEN = - 10 V, Rg = 1 Ω tr td(off) tf ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current TC = 25 °C IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb - 1.5 - 12 IS = - 0.75 A, VGS = 0 V IF = - 2.5 A, dI/dt = 100 A/µs, TJ = 25 °C A - 0.8 - 1.2 V 17 30 ns 11 20 nC 12 5 ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 68768 S-81580-Rev. A, 07-Jul-08 New Product Si2307CDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 12 2.0 VGS = 10 thru 6 V VGS = 5 V VGS = 4 V I D - Drain Current (A) I D - Drain Current (A) 10 8 6 4 1.0 TC = 25 °C 0.5 VGS = 3 V 2 1.5 TC = 125 °C TC = - 55 °C VGS = 2 V 0 0.0 0.5 1.0 1.5 0.0 1.0 2.0 1.5 VDS - Drain-to-Source Voltage (V) 2.0 3.0 3.5 4.0 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.20 600 0.15 450 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 2.5 VGS = 4.5 V 0.10 VGS = 10 V Ciss 300 150 0.05 Coss Crss 0 0.00 0 3 6 9 0 12 6 12 24 30 VDS - Drain-to-Source Voltage (V) ID - Drain Current (A) On-Resistance vs. Drain Current and Gate Voltage Capacitance 10 1.8 ID = 2.5 A ID = 3.2 A VDS = 15 V VGS = 10 V 1.6 8 VDS = 7.5 V 6 VDS = 22.5 V 4 2 1.4 (Normalized) R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 18 VGS = 4.5 V 1.2 1.0 0.8 0 0 2 4 6 Qg - Total Gate Charge (nC) Gate Charge Document Number: 68768 S-81580-Rev. A, 07-Jul-08 8 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) On-Resistance vs. Junction Temperature www.vishay.com 3 New Product Si2307CDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 0.4 ID = 3.5 A R DS(on) - On-Resistance (Ω) I S - Source Current (A) TJ = 25 °C 1 TJ = 150 °C 0.1 TJ = - 50 °C 0.01 0.3 0.2 TJ = 125 °C 0.1 TJ = 25 °C 0.001 0.0 0.0 0.3 0.6 0.9 1.2 1.5 0 2 VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage 6 8 10 On-Resistance vs. Gate-to-Source Voltage 10 0.6 8 0.4 ID = 250 µA ID = 1 mA 0.2 Power (W) VGS(th) Variance (V) 4 VGS - Gate-to-Source Voltage (V) 0.0 6 4 -0.2 -0.4 - 50 TA = 25 °C 2 - 25 0 25 50 75 100 125 0 0.01 150 0.1 1 10 100 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 1000 100 Limited by RDS(on)* 100 µs I D - Drain Current (A) 10 1 ms 1 10 ms 0.1 100 ms TA = 25 °C Single Pulse BVDSS Limited 0.01 0.1 1 10 1 s, 10 s 100 s, DC 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient www.vishay.com 4 Document Number: 68768 S-81580-Rev. A, 07-Jul-08 New Product Si2307CDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 100 10 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 PDM 0.05 t1 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJF = 70 °C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?68768. Document Number: 68768 S-81580-Rev. A, 07-Jul-08 www.vishay.com 5 Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 1 E 2 e S e1 D 0.10 mm C 0.004" A2 A C q Gauge Plane Seating Plane Seating Plane C A1 Dim 0.25 mm L L1 MILLIMETERS Min INCHES Max Min Max 0.044 A 0.89 1.12 0.035 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 e 0.95 BSC e1 L 1.90 BSC 0.40 L1 q 0.0748 Ref 0.60 0.016 0.64 Ref S 0.024 0.025 Ref 0.50 Ref 3° 0.055 0.0374 Ref 0.020 Ref 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 09-Jul-01 www.vishay.com 1 AN807 Vishay Siliconix Mounting LITTLE FOOTR SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. ambient air. This pattern uses all the available area underneath the body for this purpose. 0.114 2.9 0.081 2.05 0.150 3.8 0.059 1.5 0.0394 1.0 0.037 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the Document Number: 70739 26-Nov-03 Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. www.vishay.com 1 Application Note 826 Vishay Siliconix 0.049 (1.245) 0.029 0.022 (0.559) (0.724) 0.037 (0.950) (2.692) 0.106 RECOMMENDED MINIMUM PADS FOR SOT-23 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72609 Revision: 21-Jan-08 www.vishay.com 25 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 08-Feb-17 1 Document Number: 91000