SI3458BDV-T1-E3

Si3458BD www.vishay.com Vishay Siliconix N-Channel 60-V (D-S) MOSFET FEATURES TSOP-6 Single D 6 S 4 D 5 • TrenchFET® power MOSFET • 100 % Rg tested • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Available 1 D Top View 2 D 3 G APPLICATIONS • Load switch for portable applications • LED backlight switch • DC/DC converter Marking code: AN D PRODUCT SUMMARY VDS (V) 60 RDS(on) max. () at VGS = 10 V 0.100 RDS(on) max. () at VGS = 4.5 V 0.128 Qg typ. (nC) ID (A) Configuration G 3.5 4.1 S Single N-Channel MOSFET ORDERING INFORMATION Package TSOP-6 Lead (Pb)-free Si3458BD-T1-E3 Lead (Pb)-free and halogen-free Si3458BD-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 60 Gate-source voltage VGS ± 20 TC = 25 °C 3.2 ID TA = 25 °C 3.2 a, b 2.5 a, b TA = 70 °C Pulsed drain current IDM TC = 25 °C Continuous source-drain diode current 2.9 1.7 a, b TC = 25 °C 3.3 TC = 70 °C 2.1 PD TA = 25 °C W 2 a, b 1.3 a, b TA = 70 °C Operating junction and storage temperature range A 10 IS TA = 25 °C Maximum power dissipation V 4.1 TC = 70 °C Continuous drain current (TJ = 150 °C) UNIT TJ, Tstg -55 to +150 Soldering recommendations (peak temperature) °C 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM Maximum junction-to-ambient a, c t5s RthJA 53 62.5 Maximum junction-to-foot (drain) Steady state RthJF 32 38 UNIT °C/W Notes a. Surface Mounted on 1" x 1" FR4 board b. t = 5 s c. Maximum under steady state conditions is 110 °C/W d. Based on TC = 25 °C S09-0660-Rev. B, 20-Apr-2009 Document Number: 69501 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3458BD www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 60 - - - V 60 - - -6 - Static Drain-source breakdown voltage VDS temperature coefficient VDS/TJ VGS(th) temperature coefficient VGS(th)/TJ Gate-source threshold voltage ID = 250 μA mV/°C VGS(th) VDS = VGS , ID = 250 μA 1.5 - 3 V Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA Zero gate voltage drain current IDSS On-state drain current a ID(on) Drain-source on-state resistance a Forward transconductance a RDS(on) gfs VDS = 60 V, VGS = 0 V - - 1 VDS = 60 V, VGS = 0 V, TJ = 70 °C - - 10 VDS  5 V, VGS = 10 V 10 - - A  VGS = 10 V, ID = 3.2 A - 0.082 0.100 VGS = 4.5 V, ID = 2.8 A - 0.105 0.128 VDS = 15 V, ID = 3.2 A - 12 - - 350 - - 40 - - 20 - - 7.1 11 μA S Dynamic b Input capacitance Ciss Output capacitance Coss Reverse transfer capacitance Crss Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Gate resistance Rg Turn-on delay time Rise Ttime Turn-off delay time Fall time Turn-on delay time Rise time Turn-off delay time Fall time VDS = 30 V, VGS = 0 V, f = 1 MHz VDS = 30 V, VGS = 10 V, ID = 3.2 A - 3.5 5.5 VDS = 30 V, VGS = 4.5 V, ID = 3.2 A - 1.1 - - 0.95 - f = 1 MHz - 2.3 3.5 - 16 25 - 17 30 - 12 20 tf - 10 15 td(on) - 5 10 - 12 20 - 18 30 - 10 15 td(on) tr td(off) tr td(off) VDD = 30 V, RL = 12  ID  2.5 A, VGEN = 4.5 V, Rg = 1  VDD = 30 V, RL = 12  ID  2.5 A, VGEN = 10 V, Rg = 1  tf pF nC  ns Drain-source body diode characteristics Continuous source-drain diode current IS Pulse diode forward current ISM Body diode voltage VSD TC = 25 °C IS = 2.5 A, VGS = 0 V - - 2.9 - - 10 - 0.8 1.2 A V Body diode reverse recovery time trr - 25 50 ns Body diode reverse recovery charge Qrr - 40 80 nC Reverse recovery fall time ta - 22 - Reverse recovery rise time tb - 3 - IF = 2.5 A, dI/dt = 100 A/μs, TJ = 25 °C ns Notes a. Pulse test; pulse width  300 μs, duty cycle  2 % b. Guaranteed by design, not subject to production testing    Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S09-0660-Rev. B, 20-Apr-2009 Document Number: 69501 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3458BD www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 2.0 VGS = 10 V thru 4 V 1.6 I D - Drain Current (A) I D - Drain Current (A) 8 6 4 2 TC = - 55 °C 1.2 TC = 25 °C 0.8 TC = 125 °C 0.4 VGS = 3 V 0 0 0 0.4 0.8 1.2 1.6 2.0 0 0.5 VDS - Drain-to-Source Voltage (V) 1.5 2.0 2.5 3.0 3.5 Transfer Characteristics Output Characteristics 0.15 500 400 0.12 VGS = 4.5 V C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 1.0 VGS - Gate-to-Source Voltage (V) VGS = 10 V 0.09 Ciss 300 200 0.06 100 Coss 0.03 Crss 0 0 2 4 6 8 10 0 10 ID - Drain Current (A) 20 40 50 60 Capacitance On-Resistance vs. Drain Current and Gate Voltage 2.0 10 ID = 3.2 A ID = 3.2 A 1.8 VGS = 10 V 8 VDS = 30 V RDS(on) - On-Resistance (Normalized) VGS - Gate-to-Source Voltage (V) 30 VDS - Drain-to-Source Voltage (V) 6 VDS = 48 V 4 1.6 1.4 VGS = 4.5 V 1.2 1.0 0.8 2 0.6 0 0 2 4 6 8 0.4 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature S09-0660-Rev. B, 20-Apr-2009 Document Number: 69501 3 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3458BD www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.25 100 RDS(on) - On-Resistance (Ω) I S - Source Current (A) ID = 3.2 A 10 TJ = 150 °C TJ = 25 °C 0.20 0.15 125 °C 0.10 25 °C 0.05 1 0 0.2 0.4 0.6 0.8 1.0 0 1.2 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 30 2.50 ID = 250 µA 25 2.25 Power (W) V GS(th) (V) 20 2.00 1.75 15 10 1.50 1.25 - 50 5 - 25 0 25 50 75 100 125 0 0.001 150 0.01 0.1 1 10 100 1000 Time (s) TJ - Temperature (°C) Threshold Voltage Single Pulse Power (Junction-to-Ambient) 100 Limited by R DS(on)* I D - Drain Current (A) 10 100 µs 1 1 ms 10 ms 0.1 TA = 25 °C Single Pulse 100 ms 1 s, 10 s BVDSS Limited 0.01 0.1 1 * VGS 10 DC 100 VDS - Drain-to-Source Voltage (V) minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient S09-0660-Rev. B, 20-Apr-2009 Document Number: 69501 4 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3458BD www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 4 5 4 Power Dissipation (W) I D - Drain Current (A) 3 3 2 2 1 1 0 0 0 25 50 75 100 125 TC - Foot (Drain) Temperature (°C) Current Derating a 150 25 50 75 100 125 150 TC - Foot (Drain) Temperature (°C) Power Derating Note a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S09-0660-Rev. B, 20-Apr-2009 Document Number: 69501 5 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si3458BD www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 PDM t1 0.05 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 75 °C/W 0.02 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot                       Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69501. S09-0660-Rev. B, 20-Apr-2009 Document Number: 69501 6 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TSOP: 5/6−LEAD JEDEC Part Number: MO-193C e1 e1 5 4 6 E1 1 2 5 4 E E1 1 3 2 3 -B- e b E -B- e 0.15 M C B A 5-LEAD TSOP b 0.15 M C B A 6-LEAD TSOP 4x 1 -A- D 0.17 Ref c R R A2 A L2 Gauge Plane Seating Plane Seating Plane 0.08 C L A1 -C- (L1) 4x 1 MILLIMETERS Dim A A1 A2 b c D E E1 e e1 L L1 L2 R Min Nom Max Min Nom Max 0.91 - 1.10 0.036 - 0.043 0.01 - 0.10 0.0004 - 0.004 0.90 - 1.00 0.035 0.038 0.039 0.30 0.32 0.45 0.012 0.013 0.018 0.10 0.15 0.20 0.004 0.006 0.008 2.95 3.05 3.10 0.116 0.120 0.122 2.70 2.85 2.98 0.106 0.112 0.117 1.55 1.65 1.70 0.061 0.065 0.067 0.95 BSC 0.0374 BSC 1.80 1.90 2.00 0.071 0.075 0.079 0.32 - 0.50 0.012 - 0.020 0.60 Ref 0.024 Ref 0.25 BSC 0.010 BSC 0.10 - - 0.004 - - 0 4 8 0 4 8 7 Nom 1 ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540 Document Number: 71200 18-Dec-06 INCHES 7 Nom www.vishay.com 1 AN823 Vishay Siliconix Mounting LITTLE FOOTR TSOP-6 Power MOSFETs Surface mounted power MOSFET packaging has been based on integrated circuit and small signal packages. Those packages have been modified to provide the improvements in heat transfer required by power MOSFETs. Leadframe materials and design, molding compounds, and die attach materials have been changed. What has remained the same is the footprint of the packages. The basis of the pad design for surface mounted power MOSFET is the basic footprint for the package. For the TSOP-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. In converting the footprint to the pad set for a power MOSFET, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. Since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose. 0.167 4.25 0.074 1.875 0.014 0.35 0.122 3.1 0.026 0.65 0.049 1.25 0.049 1.25 0.010 0.25 FIGURE 1. Recommended Copper Spreading Footprint Document Number: 71743 27-Feb-04 Ramp-Up Rate +6_C/Second Maximum Temperature @ 155 " 15_C 120 Seconds Maximum Temperature Above 180_C 70 − 180 Seconds Maximum Temperature 240 +5/−0_C Time at Maximum Temperature 20 − 40 Seconds Ramp-Down Rate +6_C/Second Maximum FIGURE 2. Solder Reflow Temperature Profile www.vishay.com 1 AN823 Vishay Siliconix 10 s (max) 255 − 260_C 1X4_C/s (max) 3-6_C/s (max) 217_C 140 − 170_C 60 s (max) 60-120 s (min) Pre-Heating Zone 3_C/s (max) Reflow Zone Maximum peak temperature at 240_C is allowed. FIGURE 3. Solder Reflow Temperature and Time Durations THERMAL PERFORMANCE TABLE 1. Equivalent Steady State Performance—TSOP-6 Thermal Resistance Rqjf 30_C/W On-Resistance vs. Junction Temperature 1.6 VGS = 4.5 V ID = 6.1 A 1.4 rDS(on) − On-Resiistance (Normalized) A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rqjc, or the junction-to-foot thermal resistance, Rqjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows the thermal performance of the TSOP-6. 1.2 1.0 0.8 0.6 −50 SYSTEM AND ELECTRICAL IMPACT OF TSOP-6 −25 0 25 50 75 100 125 150 TJ − Junction Temperature (_C) FIGURE 4. Si3434DV In any design, one must take into account the change in MOSFET rDS(on) with temperature (Figure 4). www.vishay.com 2 Document Number: 71743 27-Feb-04 PAD Pattern www.vishay.com Vishay Siliconix Recommended Land Pattern For TSOP-5L / TSOP-6L 5 1 2 4 6 5 4 3 1 2 3 TSOP-6L TSOP-5L 0.028 (0.711) 0.119 (3.023) 0.064 (1.626) 0.095 (2.408) 0.037 (0.950) 0.020 (0.508) 0.017 (0.442) Note • All dimensions are in inches (millimeter) ECN: S22-0593-Rev. A, 18-Jul-2022 DWG: 3010 Revision: 18-Jul-2022 Document Number: 72610 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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