Si5504BDC
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Vishay Siliconix
N- and P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
N-Channel
30
P-Channel
-30
ID (A)
0.065 at VGS = 10 V
4a
0.100 at VGS = 4.5 V
4a
0.140 at VGS = -10 V
-3.7
0.235 at VGS = -4.5 V
-2.8
1206-8
8
1.
m
m
1
RDS(on) ()
3.0
ChipFET®
Qg (TYP.)
2 nC
2.2 nC
D1
D1
D2 7 8
D2 6
5
Top View
APPLICATIONS
Available
• DC/DC for portable applications
• Load switch
Dual
mm
• TrenchFET® Power MOSFETs
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
S2
D1
1
2 S
3 G 1
1
4 S
2
G2
G2
G1
Bottom View
Marking Code: EF
Ordering Information:
Si5504BDC-T1-E3 (Lead (Pb)-free)
Si5504BDC-T1-GE3 (Lead (Pb)-free and Halogen-free)
S1
D2
N-Channel MOSFET
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
Drain-Source Voltage
VDS
30
-30
Gate-Source Voltage
VGS
Continuous Drain Current (TJ = 150 °C)
4a
-3.7
TC = 85 °C
3.8
-2.7
3.7 b,c
-2.5 b,c
b,c
-1.8 b,c
ID
TA = 85 °C
Pulsed Drain Current
Source Drain Current Diode Current
Maximum Power Dissipation
V
± 20
TC = 25 °C
TA = 25 °C
2.6
IDM
TC = 25 °C
10
2.5
-2.5
-1.3 b,c
TC = 25 °C
3.12
3.1
TC = 85 °C
2
2
1.5 b,c
1.5 b,c
0.8 b,c
0.8 b,c
TA = 25 °C
IS
PD
TA = 85 °C
Operating Junction and Storage Temperature Range
TJ, Tstg
A
-10
1.3 b,c
TA = 25 °C
UNIT
W
-55 to 150
Soldering Recommendations (Peak Temperature) d,e
°C
260
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
TYP.
MAX.
TYP.
MAX.
Maximum Junction-to-Ambient b,f
t5s
RthJA
70
85
70
85
Maximum Junction-to-Foot (Drain)
Steady State
RthJF
33
40
33
40
UNIT
°C/W
Notes
a. Package limited.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. See reliability manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequade bottom side solder interconnection.
e. Rework conditions: Manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under steady state conditions is 120 °C/W.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current b
Drain-Source On-State Resistance b
Forward Transconductance b
VDS
VDS/TJ
VGS(th)/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 μA
N-Ch
30
-
-
VGS = 0 V, ID = -250 μA
P-Ch
-30
-
-
ID = 250 μA
N-Ch
-
27
-
ID = -250 μA
P-Ch
-
-30
-
ID = 250 μA
N-Ch
-
-5
-
ID = -250 μA
P-Ch
-
3.5
-
VDS = VGS, ID = 250 μA
N-Ch
1.5
-
3
VDS = VGS, ID = -250 μA
P-Ch
-1.5
-
-3
N-Ch
-
-
100
P-Ch
-
-
-100
VDS = 0 V, VGS = ± 20 V
IDSS
ID(on)
RDS(on)
gfs
VDS = 30 V, VGS = 0 V
N-Ch
-
-
1
VDS = -30 V, VGS = 0 V
P-Ch
-
-
-1
VDS = 30 V, VGS = 0 V, TJ = 85 °C
N-Ch
-
-
5
-5
VDS = -30 V, VGS = 0 V, TJ = 85 °C
P-Ch
-
-
VDS 5 V, VGS = 10 V
N-Ch
10
-
-
VDS -5 V, VGS = -10 V
P-Ch
-10
-
-
VGS = 10 V, ID = 3.1 A
N-Ch
-
0.053
0.065
VGS = -10 V, ID = -2.1 A
P-Ch
-
0.112
0.140
VGS = 4.5 V, ID = 1 A
N-Ch
-
0.081
0.100
VGS = -4.5 V, ID = -0.43 A
P-Ch
-
0.188
0.235
VDS = 15 V, ID = 3.1 A
N-Ch
-
5
-
VDS = -15 V, ID = -2.1 A
P-Ch
-
3.5
-
N-Ch
-
220
-
P-Ch
-
170
-
N-Ch
-
50
-
P-Ch
-
50
-
N-Ch
-
25
-
P-Ch
-
31
-
N-Ch
-
4.5
7
7
V
mV/°C
V
nA
μA
A
S
Dynamic a
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
N-Channel
VDS = 15 V, VGS = 0 V, f = 1 MHz
P-Channel
VDS = -15 V, VGS = 0 V, f = 1 MHz
Crss
VDS = 15 V, VGS = 10 V, ID = 3.6 A
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
VDS = -15 V, VGS = -10 V, ID = -2.5 A
Qg
-
4.5
-
2
3
N-Channel
VDS = 15 V, VGS = 4.5 V, ID = 3.6 A
P-Ch
-
2.2
3.5
N-Ch
-
0.7
-
P-Channel
VDS = -15 V, VGS = -4.5 V, ID = -2.5 A
P-Ch
-
0.7
-
N-Ch
-
0.7
-
P-Ch
-
1
-
N-Ch
-
3
-
P-Ch
-
13
-
Qgs
Qgd
P-Ch
N-Ch
Rg
f = 1 MHz
pF
nC
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width 300 μs, duty cycle 2 %.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Dynamic a
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(on)
N-Channel
VDD = 15 V, RL = 5.8
ID 2.6 A, VGEN = 4.5 V, Rg = 1
tr
P-Channel
VDD = -15 V, RL = 7.5
ID -2 A, VGEN = -4.5 V, Rg = 1
td(off)
tf
td(on)
N-Channel
VDD = 15 V, RL = 5.8
ID 2.6 A, VGEN = 10 V, Rg = 1
tr
P-Channel
VDD = -15 V, RL = 7.5
ID -2 A, VGEN = -10 V, Rg = 1
td(off)
tf
N-Ch
-
15
25
P-Ch
-
30
45
N-Ch
-
80
120
P-Ch
-
60
90
N-Ch
-
12
20
P-Ch
-
10
15
N-Ch
-
25
40
P-Ch
-
10
15
N-Ch
-
4
8
P-Ch
-
4
8
N-Ch
-
12
20
P-Ch
-
10
15
N-Ch
-
10
15
P-Ch
-
10
15
N-Ch
-
5
10
P-Ch
-
5
10
N-Ch
-
-
2.5
P-Ch
-
-
-2.5
N-Ch
-
-
10
-10
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current a
Body Diode Voltage
IS
TC = 25 °C
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
P-Ch
-
-
IS = 2.6 A, VGS = 0 V
N-Ch
-
0.8
1.2
IS = -2 A, VGS = 0 V
P-Ch
-
-0.8
-1.2
N-Ch
-
30
50
P-Ch
-
20
40
N-Channel
IF = 2.6 A, dI/dt = 100 A/μs, TJ = 25 °C
N-Ch
-
20
40
P-Ch
-
10
20
P-Channel
IF = -2 A, dI/dt = -100 A/μs, TJ = 25 °C
N-Ch
-
23
-
P-Ch
-
13
-
N-Ch
-
7
-
P-Ch
-
7
-
A
V
ns
nC
ns
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width 300 μs, duty cycle 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
3
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
20
5
VGS = 10 V thru 6 V
4
5V
I D - Drain Current (A)
I D - Drain Current (A)
16
12
8
4V
4
3
TC = 25 °C
2
TC = 125 °C
1
3V
0
0.0
0.5
1.0
1.5
2.0
0
0.0
2.5
1.0
1.5
2.0
2.5
3.0
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
3.5
4.0
300
250
0.16
Ciss
0.12
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
0.5
VDS - Drain-to-Source Voltage (V)
0.20
VGS = 4.5 V
0.08
VGS = 10 V
200
150
100
Coss
0.04
50
0.00
Crss
0
0
5
10
15
20
0
5
10
15
20
25
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
30
1.8
10
R DS(on) - On-Resistance (Normalized)
VDS = 15 V, ID = 3.6 A
VGS - Gate-to-Source Voltage (V)
TC = - 55 °C
8
6
4
VDS = 24 V, ID = 3.6 A
2
0
0
1
2
3
4
5
VGS = 10 V, 4.5 V
ID = 3.1 A
1.6
1.4
1.2
1.0
0.8
0.6
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
S13-2463-Rev. C, 02-Dec-13
150
Document Number: 74483
4
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
0.20
TJ = 150 °C
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 3.1 A
TJ = 25 °C
1
0.0
0.16
0.12
125 °C
25 °C
0.08
0.04
0.2
0.4
0.6
0.8
1.0
0
1.2
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
50
2.4
2.2
40
ID = 250 µA
Power (W)
VGS(th) (V)
2.0
1.8
30
20
1.6
10
1.4
1.2
- 50
- 25
0
25
50
75
100
125
0
0.0001 0.001
150
0.01
0.1
1
10
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
100
1000
10
Limited by RDS(on)*
I D - Drain Current (A)
100 µs
1
1 ms
10 ms
0.1
100 ms
1 s, 10 s
DC
TA = 25 °C
Single Pulse
BVDSS
Limited
0.01
0.01
* VGS
10
0.1
1
100
VDS - Drain-to-Source Voltage (V)
minimum VGS at which R DS(on) is specified
Safe Operating Area, Junction-to-Ambient
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
6
4
Power Dissipation (W)
ID - Drain Current (A)
5
4
Package Limited
3
2
3
2
1
1
0
0
0
25
50
75
100
125
150
25
50
75
100
TC - Case Temperature (°C)
TC - Case Temperature (°C)
Current Derating*
Power Derating
125
150
* The power dissipation PD is based on T(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
6
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
www.vishay.com
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.1
0.2
Notes:
0.1
PDM
t1
0.05
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 100 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
100
10
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
7
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
5
VGS = 10 V thru 5 V
4
I D - Drain Current (A)
I D - Drain Current (A)
8
6
4V
4
2
3
2
TC = 125 °C
1
3V
25 °C
0
0.0
0.5
1.0
1.5
2.0
2.5
0
0.0
3.0
0.5
1.0
1.5
2.0
2.5
3.0
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
3.5
4.0
250
0.4
200
0.3
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
- 55 °C
VGS = 4.5 V
0.2
VGS = 10 V
Ciss
150
100
Coss
0.1
50
Crss
0.0
0
0
2
4
6
8
10
0
5
ID - Drain Current (A)
10
20
25
30
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
1.8
10
RDS(on) - On-Resistance (Normalized)
ID = 2.5 A
VGS - Gate-to-Source Voltage (V)
15
8
VDS = 15 V
6
VDS = 24 V
4
2
0
0
1
2
3
4
5
VGS = 4.5 V, 10 V
ID = 2.2 A
1.6
1.4
1.2
1.0
0.8
0.6
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
S13-2463-Rev. C, 02-Dec-13
150
Document Number: 74483
8
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.4
10
RDS(on) - On-Resistance (Ω)
I S - Source Current (A)
ID = 2.2 A
TJ = 150 °C
TJ = 25 °C
1
0.0
125 °C
0.2
25 °C
0.1
0.0
0.2
0.4
0.6
0.8
1.0
2
1.2
4
6
8
10
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.2
50
2.1
ID = 250 µA
40
2.0
1.9
Power (W)
V GS(th) (V)
0.3
1.8
1.7
30
20
1.6
10
1.5
1.4
- 50
- 25
0
25
50
75
100
125
150
0
0.0001 0.001
0.01
0.1
1
10
TJ - Temperature (°C)
Time (s)
Threshold Voltage
Single Pulse Power
100
1000
10
Limited by RDS(on)*
I D - Drain Current (A)
100 µs
1
1 ms
10 ms
0.1
100 ms
TA = 25 °C
Single Pulse
0.01
0.01
* VGS
1 s, 10 s
DC
BVDSS
Limited
100
0.1
1
10
VDS - Drain-to-Source Voltage (V)
minimum VGS at which R DS(on) is specified
Safe Operating Area, Junction-to-Ambient
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
9
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
4
4.0
3.5
3
Power Dissipation (W)
I D - Drain Current (A)
3.0
2.5
2.0
1.5
2
1
1.0
0.5
0
0.0
0
25
50
75
100
TC - Case Temperature (°C)
Current Derating*
125
150
25
50
75
100
125
150
TC - Case Temperature (°C)
Power Derating
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
10
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si5504BDC
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Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.1
0.2
Notes:
0.1
PDM
t1
0.05
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 100 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
100
10
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74483.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
11
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
7
6
5
4
1
S
2
e
3
E1
5
6
7
8
4
3
2
1
E
4
b
x
c
Backside View
2X 0.10/0.13 R
C1
A
DETAIL X
NOTES:
1.
All dimensions are in millimeaters.
2.
Mold gate burrs shall not exceed 0.13 mm per side.
3.
Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4.
Dimensions exclusive of mold gate burrs.
5.
No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
Dim
A
b
c
c1
D
E
E1
e
L
S
INCHES
Min
Nom
Max
Min
Nom
Max
1.00
−
1.10
0.039
−
0.043
0.25
0.30
0.35
0.010
0.012
0.014
0.1
0.15
0.20
0.004
0.006
0.008
0
−
0.038
0
−
0.0015
2.95
3.05
3.10
0.116
0.120
0.122
1.825
1.90
1.975
0.072
0.075
0.078
1.55
1.65
1.70
0.061
0.065
0.067
0.65 BSC
0.28
−
0.0256 BSC
0.42
0.011
−
0.55 BSC
0.022 BSC
5_Nom
5_Nom
0.017
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
www.vishay.com
1
AN812
Vishay Siliconix
Dual-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8
pin-out, package outline, pad patterns, evaluation board
layout, and thermal performance.
80 mil
25 mil
43 mil
18 mil
10 mil
26 mil
PIN-OUT
FIGURE 2.
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thus thermal
performance. The legs of the device are very short, again
helping to reduce the thermal path to the external heatsink/pcb
and allowing a larger die to be fitted in the device if necessary.
Dual 1206-8 ChipFET
S1
G1
S2
Footprint With Copper Spreading
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins 5 and
6, pins 7 and 8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0019 sq. in. or
1.22 sq. mm. This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay
Siliconix Evaluation Board described in the next section
(Figure 3).
G2
D1
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE DUAL 1206-8
D1
D2
D2
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71127
12-Dec-03
The dual ChipFET 1206-08 evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around each of the two drain leads on the top-side—
approximately 0.0246 sq. in. or 15.87 sq. mm—and vias
added through to the underside of the board, again with a
maximized copper pad area of approximately the board-size
dimensions, split into two for each of the drains. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
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1
AN812
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30_C/W typical, 40_C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical RQja for the dual-channel 1206-8 ChipFET is
90_C/W steady state, identical to the SO-8. Maximum ratings
are 110_C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
200
Min. Footprint
160
Thermal Resistance (C/W)
THERMAL PERFORMANCE
Dual EVB
120
80
40
1” Square PCB
Testing
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the Dual 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
185_C/W
2) The evaluation board with the pad pattern
described on Figure 3.
128_C/W
3) Industry standard 1” square pcb with
maximum copper both sides.
90_C/W
www.vishay.com
2
0
10-5 10-4
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
FIGURE 4.
Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Single Thermal performance, AN811,
(http://www.vishay.com/doc?71126).
Document Number: 71127
12-Dec-03
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
0.036
(0.914)
0.022
(0.559)
(2.032)
0.080
(2.357)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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2
Document Number: 72593
Revision: 21-Jan-08
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Revision: 01-Jan-2019
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Document Number: 91000