SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
60 A VRPower® Integrated Power Stage
DESCRIPTION
FEATURES
The SiC620R and SiC620AR are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power density
performance. Packaged in Vishay’s proprietary 5 mm x 5 mm
MLP package, SiC620R and SiC620AR enables voltage
regulator designs to deliver up to 60 A continuous current
per phase.
• Thermally enhanced PowerPAK® MLP55-31L
double cooling package
• Vishay’s Gen IV MOSFET technology and a low
side MOSFET with integrated Schottky diode
• Delivers up to 60 A continuous current
• 95 % peak efficiency
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 12 V input stage
• 3.3 V (SiC620AR) / 5 V (SiC620R) PWM logic with tri-state
and hold-off
• Zero current detect control for light load efficiency
improvement
The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET® technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC620R and SiC620AR incorporates an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
zero current detect to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC620AR) /
5 V (SiC620R) PWM logic.
• Low PWM propagation delay (< 20 ns)
• Thermal monitor flag
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
TYPICAL APPLICATION DIAGRAM
5V
VIN
VIN
GH
VDRV
BOOT
PHASE
VCIN
ZCD_EN#
PWM
controller
DSBL#
PWM
VSWH
VOUT
Gate
driver
THWn
PGND
GL
CGND
Fig. 1 - SiC620R and SiC620AR Typical Application Diagram
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
24
33
GL
PWM 1
23 VSWH
VSWH
23
SMOD# 2
22 VSWH
VSWH
22
DSBL#
VSWH
25
THDn
VSWH
26
VDRV
VSWH
27
PGND
GL
28
GL
PGND
29
VSWH
VDRV
30
VSWH
THDn
31
VSWH
DSBL#
PINOUT CONFIGURATION
24
25
26
27
28
29
30
31
1 PWM
32
AGND
2 SMOD#
3 VCIN
VSWH
17
7 PHASE
VIN 8
16 VSWH
VSWH
16
8 VIN
9
10
11
12
13
14
15
15
14
13
12
11
10
9
VIN
17 VSWH
VIN
6 GH
PHASE 7
VIN
5 BOOT
18
PGND
19
VSWH
PGND
VSWH
18 VSWH
PGND
19 VSWH
GH 6
PGND
BOOT 5
PGND
4 AGND
PGND
20
PGND
21
VSWH
PGND
VSWH
20 VSWH
VIN
21 VSWH
4
VIN
3
VIN
VCIN
AGND
Top view
Bottom view
Fig. 2 - SiC620R and SiC620AR Pin Configuration
PIN CONFIGURATION
PIN NUMBER
NAME
1
PWM
FUNCTION
2
ZCD_EN#
3
VCIN
Supply voltage for internal logic circuitry
4, 32
CGND
Analog ground for the driver IC
5
BOOT
High side driver bootstrap voltage
6
GH
7
PHASE
8 to 11, 34
VIN
PWM control input
ZCD control. Active low
High side gate signal
Return path of high side gate driver
Power stage input voltage. Drain of high side MOSFET
12 to 15, 28, 35
PGND
Power ground
16 to 26
VSWH
Switch node of the power stage
27, 33
GL
29
VDRV
Low side gate signal
Supply voltage for internal gate driver
30
THWn
Thermal warning open drain output
31
DSBL#
Disable pin. Active low
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
2
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKING CODE
OPTION
SiC620RCD-T1-GE3
PowerPAK MLP55-31L
620
5 V PWM optimized
SiC620ARCD-T1-GE3
PowerPAK MLP55-31L
620
3.3 V PWM optimized
SiC620RDB / SiC620ARDB
Reference board
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
LIMIT
VIN
-0.3 to +25
Control logic supply voltage
VCIN
-0.3 to +7
Drive supply voltage
VDRV
Input voltage
Switch node (DC voltage)
BOOT voltage (DC voltage)
BOOT voltage (AC
-0.3 to +7
-0.3 to +25
VSWH
Switch node (AC voltage) (1)
-7 to +30
BOOT to PHASE (DC voltage)
38
-0.3 to +7
VBOOT-PHASE
BOOT to PHASE (AC voltage) (3)
-0.3 to +8
All logic inputs and outputs
(PWM, DSBL#, and THWn)
Output current, IOUT(AV) (4)
-0.3 to VCIN +0.3
fS = 300 kHz, VIN = 12 V, VOUT = 1.8 V
60
fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V
50
Max. operating junction temperature
TJ
150
Ambient temperature
TA
-40 to +125
Storage temperature
Tstg
-65 to +150
Human body model, JESD22-A114
3000
Charged device model, JESD22-C101
500
Electrostatic discharge protection
V
32
VBOOT
voltage) (2)
UNIT
A
°C
V
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1) The specification values indicated “AC” is V
SWH to PGND -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is V
BOOT to PGND, 38 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is V
BOOT to VPHASE, 8 V (< 20 ns) max.
(4) Output current rated with testing evaluation board at T = 25 °C with natural convection cooling. The rating is limited by the peak evaluation
A
board temperature, TJ
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input voltage (VIN)
MINIMUM
TYPICAL
MAXIMUM
4.5
-
18
Drive supply voltage (VDRV)
4.5
5
5.5
Control logic supply voltage (VCIN)
4.5
5
5.5
Switch node (VSWH, DC voltage)
-
-
18
BOOT to PHASE (VBOOT-PHASE, DC voltage)
4
4.5
5.5
Thermal resistance from junction to ambient
-
10.6
-
Thermal resistance from junction to case
-
1.6
-
S20-0486, Rev. C 29-Jun-2020
UNIT
V
°C/W
Document Number: 63589
3
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
VDSBL# = 0 V, no switching
-
12
-
VDSBL# = 5 V, no switching, VPWM = FLOAT
-
300
-
VDSBL# = 5 V, fS = 300 kHz, D = 0.1
-
380
-
fS = 300 kHz, D = 0.1
-
15
25
fS = 1 MHz, D = 0.1
-
50
-
VDSBL# = 0 V, no switching
-
25
-
VDSBL# = 5 V, no switching
-
60
-
UNIT
POWER SUPPLY
Control logic supply current
Drive supply current
IVCIN
IVDRV
μA
mA
μA
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage
VF
IF = 2 mA
0.4
V
PWM CONTROL INPUT (SiC620R)
Rising threshold
VTH_PWM_R
3.4
3.8
4.2
Falling threshold
VTH_PWM_F
0.72
0.9
1.2
Tri-state voltage
Tri-state rising threshold
Tri-state falling threshold
VTRI
-
2.3
-
VTRI_TH_R
VPWM = FLOAT
0.9
1.15
1.38
3.6
VTRI_TH_F
3
3.3
Tri-state rising threshold hysteresis
VHYS_TRI_R
-
225
-
Tri-state falling threshold hysteresis
VHYS_TRI_F
-
325
-
VPWM = 5 V
-
-
350
VPWM = 0 V
-
-
-350
PWM input current
IPWM
V
mV
μA
PWM CONTROL INPUT (SiC620AR)
Rising threshold
VTH_PWM_R
2.2
2.45
2.7
Falling threshold
VTH_PWM_F
0.72
0.9
1.1
Tri-state voltage
VTRI
-
1.8
-
Tri-state rising threshold
VTRI_TH_R
0.9
1.15
1.38
Tri-state falling threshold
VTRI_TH_F
1.95
2.2
2.45
Tri-state rising threshold hysteresis
VHYS_TRI_R
-
250
-
Tri-state falling threshold hysteresis
VHYS_TRI_F
-
300
-
PWM input current
VPWM = FLOAT
VPWM = 3.3 V
-
-
225
VPWM = 0 V
-
-
-225
tPD_TRI_R
-
30
-
IPWM
V
mV
μA
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
propagation delay
tTSHO
-
130
-
GH - turn off propagation delay
tPD_OFF_GH
-
15
-
GH - turn on propagation delay
(dead time rising)
tPD_ON_GH
-
10
-
GL - turn off propagation delay
tPD_OFF_GL
-
12
-
GL - turn on propagation delay
(dead time falling)
tPD_ON_GL
-
10
-
-
15
-
30
-
-
Tri-state hold-off time
DSBL# Lo to GH/GL falling
propagation delay
tPD_DSBL#_F
PWM minimum on-time
tPWM_ON_MIN
S20-0486, Rev. C 29-Jun-2020
No load, see fig. 4
Fig. 5
ns
Document Number: 63589
4
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER
SYMBOL
TEST CONDITION
VIH_DSBL#
Input logic high
LIMITS
MIN.
TYP.
MAX.
2
-
-
UNIT
DSBL# ZCD_EN# INPUT
DSBL# logic input voltage
ZCD_EN# logic input voltage
VIL_DSBL#
Input logic low
-
-
0.8
VIH_ZCD_EN#
Input logic high
2
-
-
VIL_ZCD_EN#
Input logic low
-
-
0.8
VCIN rising, on threshold
-
3.7
4.1
VCIN falling, off threshold
2.7
3.1
-
V
PROTECTION
Under voltage lockout
VUVLO
Under voltage lockout hysteresis
VUVLO_HYST
-
575
-
THWn flag set (2)
TTHWn_SET
-
160
-
THWn flag clear (2)
TTHWn_CLEAR
-
135
-
THWn flag hysteresis (2)
TTHWn_HYST
-
25
-
-
0.02
-
THWn output low
VOL_THWn
ITHWn = 2 mA
V
mV
°C
V
Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-State Function
Diode Emulation Mode (ZCD_EN#)
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low side is turned on and the high side is
turned on. When PWM input is driven below VPWM_TH_F the
high side is turned off and the low side is turned on. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs. However, there is an third state
that is entered as the PWM output of tri-state compatible
controller enters its high impedance state during shutdown.
The high impedance state of the controller’s PWM output
allows the SiC620R and SiC620AR to pull the PWM input
into the tri-state region (see PWM Timing Diagram). If the
PWM input stays in this region for the tri-state hold-off
period, tTSHO, both high side and low side MOSFETs are
turned off. This function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC620AR incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC620R thresholds are compatible with 5 V logic.
When ZCD_EN# pin is logic Low and PWM signal switches
Low, GL is forced on (after normal BBM time). During this
time, it is under control of the ZCD (zero crossing detect)
comparator. If, after the internal blanking delay, the inductor
current becomes zero, the low side is turned off. This
improves light load efficiency by avoiding discharge of
output capacitors. If PWM enters tri-state, then device will
go into normal tri-state mode after tri-state delay. The GL
output will be turned off regardless of Inductor current, this
is an alternative method of improving light load efficiency by
reducing switching losses.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high side and low side MOSFETs. In this state,
standby current is minimized. If DSBL# is left unconnected,
an internal pull-down resistor will pull the pin to CGND and
shut down the IC.
S20-0486, Rev. C 29-Jun-2020
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 k, to VCIN. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC620R and SiC620AR do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Voltage Input (VIN)
This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Document Number: 63589
5
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
Switch Node (VSWH and PHASE)
Bootstrap Circuit (BOOT)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC620R and SiC620AR have an internal adaptive logic
to avoid shoot through and optimize dead time. The shoot
through protection ensures that both high side and low side
MOSFETs are not turned on at the same time. The adaptive
dead time control operates as follows. The HS and LS gate
voltages are monitored to prevent the one turning on from
tuning on until the other’s gate voltage is sufficiently low
(< 1 V). Built in delays also ensure that one power MOS is
completely off, before the other can be turned on. This
feature helps to adjust dead time as gate transitions change
with respect to output current and temperature. Change
with respect to output current and temperature.
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected
to CGND (control signal ground). The layout of the printed
circuit board should be such that the inductance separating
CGND and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive holding high side and low side MOSFET gates low
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC620R,
SiC620AR also incorporates logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.
FUNCTIONAL BLOCK DIAGRAM
THWn
BOOT
GH
V IN
VDRV
Thermal monitor
and warning
VCIN
UVLO
DISB#
VCIN
PWM
PWM logic
control and
state
machine
Anti-cross
conduction
control
logic
+
GL
20K
Vref = 1 V
PHASE
VSWH
+
Vref = 1 V
VDRV
CGND
VSWH
PGND
ZCD_EN#
GL
PGND
Fig. 3 - SiC620R and SiC620AR Functional Block Diagram
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
6
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
DEVICE TRUTH TABLE
DSBL#
ZCD_EN#
PWM
GH
GL
Open
X
X
L
L
L
X
X
L
L
L
L
H, IL > 0 A
L, IL < 0 A
H
L
H
L
H
H
L
H
L
Tri-state
L
L
H
H
L
L
H
H
H
H
H
L
H
H
Tri-state
L
L
PWM TIMING DIAGRAM
VTH_PWM_R
VTH_TRI_F
VTH_TRI_R
VTH_PWM_F
PWM
t PD_OFF_GL
t TSHO
GL
t PD_ON_GL
t PD_TRI_R
t TSHO
t PD_ON_GH
t PD_OFF_GH
t PD_TRI_R
GH
Fig. 4 - Definition of PWM Logic and Tri-state
DSBL# PROPAGATION DELAY
PWM
PWM
Disable
DSBL#
DSBL#
GH
GH
GL
GL
t
t
DSBL#Low to GH Falling Propagation Delay
DSBL# Low to GL Falling Propagation Delay
Fig. 5 - DSBL# Falling Propagation Delay
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
7
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1.8 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C, natural convection
cooling (All power loss and normalized power loss curves show SiC620R and SiC620AR losses only unless otherwise stated)
65
96
60
94
300 kHz
Efficiency (%)
90
800 kHz
88
1 MHz
86
Complete converter efficiency
84
82
Power Output Purrent, IOUT (A)
92
300 kHz
55
500 kHz
50
1 MHz
45
40
35
30
25
20
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
15
POUT = VOUT x IOUT, measured at output capacitor
10
5
80
0
5
10
15
20
25
30
35
40
45
50
0
55
0
25
50
75
100
125
150
PCB Temperature, TPCB (°C)
Output Current, IOUT (A)
Fig. 9 - Safe Operating Area
Fig. 6 - Efficiency vs. Output Current
1.4
8
1 MHz
7
800 kHz
500 kHz
6
Normalized Power Loss
300 kHz
Power Loss, PL (W)
IOUT = 30 A
1.3
5
4
3
1.2
1.1
1
2
0.9
1
0.8
200
0
0
5
10
15
20 25 30 35 40
Output Current, IOUT (A)
45
50
55
400
500
600
700
800
900
1000 1100
Switching Frequency, fs (kHz)
Fig. 7 - Power Loss vs. Output Current
Fig. 10 - Power Loss vs. Switching Frequency
1.2
1.2
1.15
1.15
Power Loss
IOUT = 30 A
1.1
1.05
Normalized
Normalized Power Loss
300
1
0.95
1.1
IOUT = 30 A
1.05
1
0.95
0.9
0.9
4
6
8
10
12
14
Input Voltage, VIN (V)
16
Fig. 8 - Power Loss vs. Input Voltage
S20-0486, Rev. C 29-Jun-2020
18
4
4.2
4.4
4.6
4.8
5
5.2
Drive Supply Voltage, VDRV (V)
5.4
5.6
Fig. 11 - Power Loss vs. Drive Supply Voltage
Document Number: 63589
8
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
1.01
1.3
IOUT = 30 A
I OUT = 30 A
1.2
Normalized Power Loss
Normalized Power Loss
1
1.1
1
0.99
0.98
0.9
0.97
0.8
0.5
1
1.5
2
2.5
Output Voltage, VOUT (V)
3
3.5
200
250
Fig. 12 - Power Loss vs. Output Voltage
400
450
500
50
45
Driver Supply Current, IVDRV and ICVIN (mA)
40
Driver Supply Current, IVDRV& IVCIN (mA)
350
Fig. 15 - Power Loss vs. Output Inductor
45
35
30
IOUT = 0 A
25
20
15
10
I OUT = 0 A
40
35
30
25
20
15
10
5
5
4.00
4.25
4.50
4.75
5.00
5.25
Driver Supply Voltage, VDRV &VCIN (V)
0
300
5.50
400
500
600
700
800
900
1000
Switching frequency, fs (kHz)
Fig. 13 - Driver Supply Current vs. Driver Supply Voltage
Fig. 16 - Driver Supply Current vs. Switching Frequency
1.1
4.2
1.08
4.0
Control Logic Supply Voltage, VCIN (V)
Normalized Driver Supply Current, IVCIN and IVDRV
300
Output Inductor, L OUT (nH)
1.06
1.04
1.02
1 MHz
1
0.98
300 kHz
0.96
VUVLO_RISING
3.8
3.6
3.4
3.2
3.0
VUVLO_FALLING
2.8
2.6
0
5
10
15
20
25
30
35
40
45
50
55
Output Current, OI UT (A)
Fig. 14 - Driver Supply Current vs. Output Current
S20-0486, Rev. C 29-Jun-2020
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 17 - UVLO Threshold vs. Temperature
Document Number: 63589
9
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
3.20
2.85
VTH_PWM_R
2.50
VTRI_TH_F
2.15
1.80
VTRI
1.45
VTRI_TH_R
1.10
0.75
PWM Threshold Voltage, VPWM (V)
Control Logic Supply Voltage, VPWM (V)
3.20
0
20 40 60 80
Temperature (°C)
VTRI
1.45
VTRI_TH_R
1.10
VTH_PWM_F
4.5
4.6
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Driver Supply Voltage, VCIN (V)
5.4
5.5
Fig. 21 - PWM Threshold vs. Driver Supply Voltage (SiC620AR)
5.00
5.0
4.50
VTH_PWM_R
4.0
3.5
VTRI_TH_F
3.0
VTRI
2.5
2.0
VTRI_TH_R
1.0
PWM Threshold Voltage, VPWM (V)
4.5
Control Logic Supply Voltage, VPWM (V)
1.80
100 120 140
Fig. 18 - PWM Threshold vs. Temperature (SiC620AR)
VTH_PWM_F
VTH_PWM_R
4.00
3.50
VTRI_TH_F
3.00
VTRI
2.50
2.00
1.50
VTRI_TH_R
1.00
VTH_PWM_F
0.50
0
0.0
-60 -40 -20
0
20 40 60 80
Temperature (°C)
4.5
100 120 140
Fig. 19 - PWM Threshold vs. Temperature (SiC620R)
4.6
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Driver Supply Voltage, VCIN (V)
5.4
5.5
Fig. 22 - PWM Threshold vs. Driver Supply Voltage (SiC620R)
2.20
1.7
VIH_DSBL#
1.6
ZCD_EN# Threshold Voltage, VZCD_EN# (V)
DSBL# Threshold Voltage, VDSBL# (V)
VTRI_TH_F
2.15
0.40
-60 -40 -20
0.5
VTH_PWM_R
2.50
0.75
VTH_PWM_F
0.40
1.5
2.85
1.5
1.4
1.3
1.2
1.1
VIL_DSBL#
1.0
0.9
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 20 - DSBL# Threshold vs. Temperature
S20-0486, Rev. C 29-Jun-2020
2.00
1.80
VIH_ZCD_EN#_R
1.60
1.40
1.20
VIL_ZCD_EN#_F
1.00
0.80
0.60
4.5
4.6
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Driver Supply Voltage, VCIN (V)
5.4
5.5
Fig. 23 - ZCD_EN# Threshold vs. Driver Supply Voltage
Document Number: 63589
10
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
80
VIH_DSBL#
1.6
70
Driver Supply Current, IVDVR & IVCIN (V)
DSBL# Threshold Voltage, VDSBL# (V)
1.7
1.5
1.4
1.3
1.2
1.1
VIL_DSBL#
1.0
0.9
50
40
30
20
10
0
4.5
4.6
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Driver Supply Voltage, VCIN (V)
5.4
5.5
-60 -40 -20
Fig. 24 - DSBL# vs. Driver Input Voltage
10.8
390
10.7
380
10.6
10.5
10.4
10.3
10.2
10.1
10.0
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 27 - Driver Shutdown Current vs. Temperature
Driver Supply Current, IVDVR & IVCIN (V)
DSBL# Pull-Down Current, IDSBL# (uA)
VDSBL# = 0 V
60
370
360
350
VPWM = FLOAT
340
330
320
310
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 25 - DSBL# Pull-Down Current vs. Temperature
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 28 - Driver Supply Current vs. Temperature
0.40
BOOT Diode Forward Voltage, VF (V)
0.35
IF = 2 mA
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-60 -40 -20
0
20 40 60 80
Temperature (°C)
100 120 140
Fig. 26 - Boot Diode Forward Voltage vs. Temperature
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
11
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling
Step 3: VCIN/VDRV Input Filter
VSWH
P
G
N
D
PGND
CVDRV
CVCIN
VIN
CGND
VIN plane
PGND plane
1. Layout VIN and PGND planes as shown above
2. Ceramic capacitors should be placed right between VIN
and PGND, and very close to the device for best
decoupling effect
3. Difference values / packages of ceramic capacitors
should be used to cover entire decoupling spectrum e.g.
1210, 0805, 0603 and 0402
4. Smaller capacitance value, closer to device VIN pin(s)
- better high frequency noise absorbing
1. The VCIN/VDRV input filter ceramic cap should be placed
very close to IC. It is recommended to connect two caps
separately
2. CVCIN cap should be placed between pin 3 and pin 4
(CGND of driver IC) to achieve best noise filtering
3. CVDRV cap should be placed between pin 28 (PGND of
driver IC) and pin 29 to provide maximum instantaneous
driver current for low side MOSFET during switching
cycle
4. For connecting CVCIN analog ground, it is recommended
to use large plane to reduce parasitic inductance
Step 2: VSWH Plane
Step 4: BOOT Resistor and Capacitor Placement
VVSWH
SWH
Snubber
Cboot
Rboot
PPGND
Plane
GND plane
1. Connect output inductor to DrMOS with large plane to
lower the resistance
2. If any snubber network is required, place the
components as shown above and the network can be
placed at bottom
S20-0486, Rev. C 29-Jun-2020
1. These components need to be placed very close to IC,
right between PHASE (pin 7) and BOOT (pin 5)
2. To reduce parasitic inductance, chip size 0402 can be
used
Document Number: 63589
12
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
Step 5: Signal Routing
1. Thermal relief vias can be added on the VIN and PGND
pads to utilize inner layers for high current and thermal
dissipation
CGND
2. To achieve better thermal performance, additional vias
can be put on VIN plane and PGND plane
CGND
3. VSWH pad is a noise source and not recommended to put
vias on this plane
4. 8 mil drill for pads and 10 mils drill for plane can be the
optional via size. Vias on pad may drain solder during
assembly and cause assembly issue. Please consult
with the assembly house for guideline
Step 7: Ground Connection
PGND
CGND
VSWH
1. Route the PWM / ZCD_EN# / DSBL# / THWn signal
traces out of the top left corner next DrMOS pin 1
2. PWM signal is very important signal, both signal and
return traces need to pay special attention of not letting
this trace cross any power nodes on any layer
PGND
3. It is best to “shield” traces form power switching nodes,
e.g. VSWH, to improve signal integrity
4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally
Step 6: Adding Thermal Relief Vias
1. It is recommended to make single connection between
CGND and PGND and this connection can be done on top
layer
2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into CGND
and PGND plane
VSWH
3. These ground planes provide shielding between noise
source on top layer and signal trace on bottom layer
CGND
PGND
VIN
PGND
plane
VIN plane
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
13
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
Multi-Phases VRPower PCB Layout
Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with
decoupling caps next to them. The inductors are placed as close as possible to the SiC620R and SiC620AR to minimize the
PCB copper loss. Vias are applied on all PADs (VIN, PGND, CGND) of the SiC620R and SiC620AR to ensure that both electrical
and thermal performance are excellent. Large copper planes are used for all the high current loops, such as VIN, VSWH, VOUT
and PGND. These copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals
are routed from the SiC620R and SiC620AR to a controller placed to the north of the power stage through inner layers to avoid
the overlap of high current loops. This achieves a compact design with the output from the inductors feeding a load located to
the south of the design as shown in the figure.
VIN
PGND
VOUT
Fig. 29 - Multi-Phase VRPower Layout Top View
VIN
PGND
VOUT
Fig. 30 - Multi-Phase VRPower Layout Bottom View
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
14
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC620R, SiC620AR
www.vishay.com
Vishay Siliconix
PRODUCT SUMMARY
Part number
SiC620R
SiC620AR
Description
60 A power stage, 4.5 VIN to 18 VIN, 5 V PWM
with ZCD mode, dual side cooling
60 A power stage, 4.5 VIN to 18 VIN, 3.3 V
PWM with ZCD mode, dual side cooling
Input voltage min. (V)
4.5
4.5
Input voltage max. (V)
18
18
Continuous current rating max. (A)
60
60
Switch frequency max. (kHz)
1500
1500
Enable (yes / no)
Yes
Yes
Monitoring features
Protection
Light load mode
Pulse-width modulation (V)
Package type
Package size (W, L, H) (mm)
-
-
UVLO, THDN
UVLO, THDN
ZCD
ZCD
5
3.3
PowerPAK MLP55-31L double cooling
PowerPAK MLP55-31L double cooling
5.0 x 5.0 x 0.60
5.0 x 5.0 x 0.60
Status code
2
2
Product type
VRPower (DrMOS)
VRPower (DrMOS)
Applications
Computer, industrial, networking
Computer, industrial, networking
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63589.
S20-0486, Rev. C 29-Jun-2020
Document Number: 63589
15
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP55-31L Double Cooling Case Outline (for SiC620R)
4 5
Pin 1 dot
by marking
K7
D2-5
K12
K13
K1 D2-1 8 x
2x
0.10 C A
D
A
K4
A
2x
L
A1
0.10 C B
F1
24
D2-4
31
A2
1
23
K8
N2
3
E2-3
0.05 M C
E
0.1 M C A B
K11
K3
K10
B
M1
e
26 x
b1
31 x
8
15
Side view
0.10 C
9
K2
D2-3
K9
e2
e3
C
D2-6
0.08 C
DIM.
e1
E2-2
D2-2
16
M2
Top view
K5
3x
N1
b
31 x
E2-1
K6
E2-4
D2-7
Bottom view
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
A (7)
0.56
0.61
0.66
0.022
0.024
0.026
A1
0.00
-
0.05
0.000
-
0.002
A2
0.20 ref.
MAX.
0.008 ref.
b (3)
0.20
0.25
0.30
0.008
0.010
0.012
b1
0.15
0.20
0.35
0.006
0.008
0.014
D
4.90
5.00
5.10
0.193
0.197
0.201
e
E
0.50 BSC
4.90
5.00
0.019 BSC
5.10
0.193
0.197
e1
3.50 BSC
0.138 BSC
e2
1.50 BSC
0.059 BSC
e3
1.00 BSC
0.200
0.039 BSC
L
0.35
0.40
0.45
0.014
0.016
0.018
D2-1
0.98
1.03
1.08
0.039
0.041
0.043
D2-2
0.98
1.03
1.08
0.039
0.041
0.043
D2-3
1.87
1.92
1.97
0.074
0.076
0.078
D2-4
0.25
0.30
0.35
0.010
0.012
0.014
D2-5
0.98
1.03
1.08
0.039
0.041
0.043
D2-6
3.50 BSC
0.138 BSC
D2-7
0.70
0.75
0.80
0.028
0.030
0.032
E2-1
1.27
1.32
1.37
0.050
0.052
0.054
E2-2
1.93
1.98
2.03
0.076
0.078
0.080
E2-3
3.75
3.80
3.85
0.148
0.150
0.152
E2-4
0.50
0.55
0.60
0.020
0.022
0.024
F1
0.15
0.20
0.25
0.006
0.008
0.010
Revision: 11-Dec-17
Document Number: 75766
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
DIM.
Vishay Siliconix
MILLIMETERS
MIN.
NOM.
INCHES
MAX.
MIN.
NOM.
K1
0.67 ref.
0.026 ref.
K2
0.22 ref.
0.009 ref.
K3
1.40 ref.
0.006 ref.
K4
0.07 ref.
0.003 ref.
K5
0.38 ref.
0.015 ref.
K6
0.12 ref.
0.005 ref.
K7
0.40 ref.
0.016 ref.
K8
0.40 ref.
0.016 ref.
K9
0.40 ref.
0.016 ref.
K10
0.85 ref.
0.033 ref.
K11
0.55 ref.
0.022 ref.
K12
0.30 ref.
0.012 ref.
K13
0.75 ref.
0.030 ref.
M1
1.08 ref.
0.043 ref.
M2
2.34 ref.
0.092 ref.
N1
1.08 ref.
0.043 ref.
N2
4.10 ref.
0.161 ref.
MAX.
ECN: T17-0668-Rev. A, 11-Dec-17
DWG: 6060
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
Revision: 11-Dec-17
Document Number: 75766
2
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
www.vishay.com
Vishay Siliconix
Recommended Land Pattern
PowerPAK® MLP55-31L
Top side transparent view
(not bottom view)
Land pattern for MLP55-31L
5
(D2-5)
1.05 24
1.35 0.57
1 24
0.5
31
0.3
0.33
0.75
(D2-1)
31 1.03
(D2-4)
3.4
0.33
1.42
0.35
(D2-2)
1.03
(D2-3)
1.92
15
(L)
0.4
3.05
0.07
2.15
2.08
8
16
0.18
0.65
9
(L)
0.4
0.3
3.5
0.4
2.02
1.75
0.58
16
23
1.15
0.3
0.35
9
0.5
0.35
0.65
0.5
15
0.75
0.3
8
0.5
(E2-3)
1.98
(b)
0.25
5
(E2-1)
4.2
(K2) 0.22
(K1) 0.67
1.13
0.3
1
0.35
0.15
(E3)
0.45
(E2-2)
1.32
0.5 (e)
23
1.6
0.85
0.75
(D3) 0.3
1
All dimensions in millimeters
24
31
1
23
33
Component for MLP55-31L
32
Land pattern for MLP55-31L
35
33
8
16
9
Revision: 18-Oct-2019
15
Document Number: 66944
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 01-Jan-2021
1
Document Number: 91000
工商网监
湘ICP备2023018690号
