SIC473ED-T1-GE3

Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix 4.5 V to 55 V Input, 3 A, 5 A, 8 A, 12 A microBUCK® DC/DC Converter FEATURES DESCRIPTION The SiC47x is a family of wide input voltage, high efficiency synchronous buck regulators with integrated high side and low side power MOSFETs. Its power stage is capable of supplying high continuous current at up to 2 MHz switching frequency. This regulator produces an adjustable output voltage down to 0.8 V from 4.5 V to 55 V input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. SiC47x’s architecture allows for ultrafast transient response with minimum output capacitance and tight ripple regulation at very light load. The device enables loop stability regardless of the type of output capacitor used, including low ESR ceramic capacitors. The device also incorporates a power saving scheme that significantly increases light load efficiency. The regulator integrates a full protection feature set, including over current protection (OCP), output overvoltage protection (OVP), short circuit protection (SCP), output undervoltage protection (UVP) and over temperature protection (OTP). It also has UVLO for input rail and a user programmable soft start. The SiC47x family is available in 3 A, 5 A, 8 A, 12 A pin compatible 5 mm by 5 mm lead (Pb)-free power enhanced MLP55-27L package. TYPICAL APPLICATION CIRCUIT • Versatile - Single supply operation from 4.5 V to 55 V input voltage - Adjustable output voltage down to 0.8 V - Scalable solution 3 A (SiC474), 5 A (SiC473), 8 A (SiC472), 12 A (SiC471) - Output voltage tracking and sequencing with pre-bias start up - ± 1 % output voltage accuracy at -40 °C to +125 °C • Highly efficient - 98 % peak efficiency - 4 μA supply current at shutdown - 235 μA operating current, not switching • Highly configurable - Adjustable switching frequency from 100 kHz to 2 MHz - Adjustable soft start and adjustable current limit - 3 modes of operation, forced continuous conduction, power save or ultrasonic • Robust and reliable - Output over voltage protection - Output under voltage / short circuit protection with auto retry - Power good flag and over temperature protection - Supported by Vishay PowerCAD online design simulation • Design support tools - PowerCAD online design simulation (vishay.transim.com) - External component calculator (www.vishay.com/doc?75760) - Schematic, design, BOM, and gerber files (www.vishay.com/doc?75763) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • • • • • • • Industrial and automation Home automation Industrial and server computing Networking, telecom, and base station power supplies Unregulated wall transformer Robotics High end hobby electronics: remote control cars, planes, and drones • Battery management systems • Power tools • Vending, ATM, and slot machines 100 VIN = 24 V, VOUT = 12 V 97 VIN = 48 V, VOUT = 12 V 94 V IN CBOOT PHASE V DD CIN SiC47x V DRV Cy Cx Rup V FB ILIMIT COMP PGND fSW Rlimit AGND Css Rx V SNS ULTRASONIC MODE SS 91 V OUT SW COUT Rcomp Rdown Ccomp Efficiency (%) BOOT EN VCIN PGOOD INPUT 4.5 VDC to 55 VDC 88 85 VIN = 24 V, VOUT = 5 V 82 VIN = 48 V, VOUT = 5 V 79 76 Rfsw 73 70 0.01 Fig. 1 - Typical Application Circuit for SiC47x SPending-Rev. A, 04-Jul-2018 0.1 1 Output Current, IOUT (A) Fig. 2 - SiC472 Efficiency vs. Output Current Document Number: 75786 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix BOOT 4 PGND 17 16 VDRV VDRV 16 15 GL 29 PGND ķ 27 MODE 26 VDD 25 ILIM 24 fSW 23 AGND 22 VFB 21 COMP 4 BOOT GL 15 14 SW SW 14 13 SW SW 13 12 SW SW 12 30 PGND 29 VIN ķ PGND 10 PGND 11 PGND 9 VIN 8 VIN 7 PHASE 6 3 EN 5 PHASE 6 PHASE PGND 11 30 VIN PHASE 5 2 PGOOD VIN 7 EN 3 17 PGND 28 AGND VIN 8 28 AGND PGOOD 2 ULTRASONIC 18 PGND 9 18 ULTRASONIC 1 VCIN SS 19 19 SS PGND 10 IJ VCIN 1 20 VSNS 20 VSNS 21 COMP 22 VFB 23 AGND 24 fSW 25 ILIM 26 VDD 27 MODE PIN CONFIGURATION Fig. 3 - SiC47x Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION 1 VCIN Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators 2 PGOOD 3 EN Open-drain power good indicator - high impedance indicates power is good. An external pull-up resistor is required Enable pin. Tie high/low to enable/disable the IC accordingly. This is a high voltage compatible pin, can be tied to VIN 4 BOOT High side driver bootstrap voltage 5, 6 PHASE Return path of high side gate driver 7, 8, 29 VIN 9, 10, 11, 17, 30 PGND 12, 13, 14 SW Power stage switch node 15 GL Low side MOSFET gate signal 16 VDRV Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 18 ULTRASONIC Float to disable ultrasonic mode, connect to VDD to enable. Depending on the operation mode set by the mode pin, power save mode or forced continuous mode will be enabled when the ultrasonic mode is disabled 19 SS Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the capacitor 20 VSNS 21 COMP Output of the internal error amplifier. The feedback loop compensation network is connected from this pin to the AGND pin 22 VFB Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from VOUT to AGND 23, 28 AGND 24 fSW 25 ILIMIT 26 VDD 27 MODE SPending-Rev. A, 04-Jul-2018 Power stage input voltage. Drain of high side MOSFET Power ground Power inductor signal feedback pin for system stability compensation Analog ground Set the on-time by connecting a resistor to AGND Set the current limit by connecting a resistor to AGND Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND Set various operation modes by connecting a resistor to AGND. See specification table for details Document Number: 75786 2 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ORDERING INFORMATION PART NUMBER PACKAGE MARKING CODE PowerPAK® MLP55-27L SiC471ED-T1-GE3 SiC471EVB SiC471 Reference board PowerPAK® MLP55-27L SiC472ED-T1-GE3 SiC472EVB SiC472 Reference board PowerPAK® MLP55-27L SiC473ED-T1-GE3 SiC473EVB SiC473 Reference board PowerPAK® MLP55-27L SiC474ED-T1-GE3 SiC474EVB SiC474 Reference board PART MARKING INFORMATION = pin 1 indicator P/N P/N = = Siliconix logo LL = ESD symbol assembly factory code FYWW part number code F = Y = year code WW = week code LL = lot code ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) ELECTRICAL PARAMETER EN, VCIN, VIN CONDITIONS LIMITS Reference to PGND -0.3 to +60 SW / PHASE Reference to PGND -0.3 to +60 VDRV Reference to PGND -0.3 to +6 VDD Reference to AGND -0.3 to +6 Reference to PGND; 100 ns -10 to +66 SW / PHASE (AC) BOOT V -0.3 to VPHASE + VDRV AGND to PGND All other pins UNIT -0.3 to +0.3 Reference to AGND -0.3 to VDD + 0.3 Junction temperature TJ -40 to +150 Storage temperature TSTG -65 to +150 Temperature °C Power Dissipation Thermal resistance from junction-to-ambient 12 Thermal resistance from junction-to-case 2 °C/W ESD Protection Electrostatic discharge protection Human body model, JESD22-A114 2000 Charged device model, JESD22-A101 500 V  Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. SPending-Rev. A, 04-Jul-2018 Document Number: 75786 3 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V) PARAMETER MIN. TYP. MAX. Input voltage (VIN) 4.5 - 55 Control input voltage (VCIN) (1) 4.5 - 55 Enable (EN) 0 - 55 Bias supply (VDD) 4.75 5 5.25 Drive supply voltage (VDRV) 4.75 5.3 5.55 Output voltage (VOUT) 0.8 - 0.92 x VIN UNIT V Temperature Recommended ambient temperature -40 to +105 Operating junction temperature -40 to +125 °C Note (1) For input voltages below 5 V, provide a separate supply to V CIN of at least 5 V to prevent the internal VDD rail UVLO from triggering ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. VIN = VCIN = 6 V to 55 V VIN = VCIN = 5 V 4.75 5 5.25 4.7 5 - UNIT Power Supplies VDD supply VDD VDD dropout VDD_DROPOUT - 70 - VDD_UVLO 4 4.25 4.5 V VDD UVLO hysteresis VDD_UVLO_HYST - 225 - mV Maximum VDD current IDD mA VDD UVLO threshold, rising VIN = VCIN = 5 V, IVDD = 1 mA V VIN = VCIN = 6 V to 55 V 3 - - VIN = VCIN = 6 V to 55 V 5.1 5.3 5.55 VIN = VCIN = 5 V 4.8 5 5.2 mV VDRV supply VDRV VDRV dropout VDRV_DROPOUT VIN = VCIN = 5 V, IVDD = 10 mA - 160 - mV VDRV VIN = VCIN = 6 V to 55 V 50 - - mA VDRV_UVLO 4 4.25 4.5 V VDRV_UVLO_HYST - 295 - mV Maximum VDRV current VDRV UVLO threshold, rising VDRV UVLO hysteresis Input current Shutdown current V IVCIN Non-switching, VFB > 0.8 V - 235 325 IVCIN_SHDN VEN = 0 V - 4 8 TJ = 25 °C 796 800 804 TJ = -40 °C to +125 °C (1) 792 800 808 - 2 - pA mS μA Controller and Timing Feedback voltage VFB VFB input bias current IFB Transconductance COMP source current COMP sink current Minimum on-time tON accuracy On-time range m/V gm - 0.3 - ICOMP_SOURCE 15 20 - ICOMP_SINK 15 20 - tON_MIN. - 90 110 ns tON_ACCURACY -10 - 10 % ns tON_RANGE Frequency range fsw 110 - 8000 Ultrasonic mode enabled 20 - 2000 Ultrasonic mode disabled 0 - 2000 μA kHz Minimum off-time tOFF_MIN. 190 250 310 ns Soft start current ISS 3 5 7 μA Soft start voltage VSS - 1.5 - V SPending-Rev. A, 04-Jul-2018 When VOUT reaches regulation Document Number: 75786 4 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. High side on resistance RON_HS 13 - RON_LS SiC471 (12 A), VDRV = 5.3 V, TA = 25 °C - Low side on resistance - 5 - SiC472 (8 A), VDRV = 5.3 V, TA = 25 °C - 20 - - 8 - SiC473 (5 A), VDRV = 5.3 V, TA = 25 °C - 32 - - 22 - SiC474 (3 A), VDRV = 5.3 V, TA = 25 °C - 37 - - 27 - SiC471 (12 A), RILIM = 60 k, TJ = -10 °C to +125 °C 12 15 18 SiC472 (8 A), RILIM = 60 k, TJ = -10 °C to +125 °C 8 10 12 SiC473 (5 A), RILIM = 60 k, TJ = -10 °C to +125 °C 5.6 7 8.4 SiC474 (3 A), RILIM = 60 k, TJ = -10 °C to +125 °C 4 5 6 - 20 - - -80 - UNIT Power MOSFETs High side on resistance RON_HS Low side on resistance RON_LS High side on resistance RON_HS Low side on resistance RON_LS High side on resistance RON_HS Low side on resistance RON_LS m Fault Protections Valley current limit IOCP Output OVP threshold VOVP Output UVP threshold VUVP Over temperature protection VFB with respect to 0.8 V reference A TOTP_RISING Rising temperature - 150 - TOTP_HYST Hysteresis - 35 - VFB_RISING_VTH_OV VFB rising above 0.8 V reference - 20 - VFB_FALLING_VTH_UV VFB falling below 0.8 V reference - -10 - % °C Power Good Power good output threshold Power good hysteresis % VFB_HYST - 50 - Power good on resistance RON_PGOOD - 7.5 15  Power good delay time tDLY_PGOOD 15 25 35 μs EN logic high level VEN_H - 1.35 - EN logic low level VEN_L - 1.2 - EN hysteresis VHYST - 0.15 - REN - 5 - Ultrasonic mode high Level VULTRASONIC_H 2 - - Ultrasonic mode low level VULTRASONIC_L - - 0.8 mV EN / MODE / Ultrasonic Threshold EN pull down resistance Mode pull up current IMODE 3.75 5 6.25 Power save mode enabled, VDD, VDRV Pre-reg on 0 2 100 Power save mode disabled, VDD, VDRV Pre-reg on 298 301 304 Mode 3 Power save mode disabled, VDRV Pre-reg off, VDD Pre-reg on, provide external VDRV 494 499 504 Mode 4 Power save mode enabled, VDRV Pre-reg off, VDD Pre-reg on, provide external VDRV 900 1000 1100 Mode 1 Mode 2 RMODE V M V μA k Note (1) Guaranteed by design SPending-Rev. A, 04-Jul-2018 Document Number: 75786 5 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VCIN BOOT VDRV VDRV regulator VDD VDD regulator Sync rectifier VDD UVLO HS UVLO Enable EN fSW ULTRASONIC VIN On time generator VDD 5 μA tON Min. tOFF HS driver PHASE MODE MODE VSNS SW Control logic Ramp VDRV PWM COMP COMP VDD 0.8 V 5 μA LS driver Reference PHASE Zero crossing GL OTA SS PGOOD VFB Over voltage under voltage VFB ILIMIT PHASE Over current Over temperature Power good AGND PGND Fig. 4 - SiC47x Functional Block Diagram OPERATIONAL DESCRIPTION Device Overview Power Stage SiC47x is a high efficiency synchronous buck regulator family capable of delivering up to 12 A continuous current. The device has programmable switching frequency of 100 kHz to 2 MHz. The voltage mode, constant on time control scheme delivers fast transient response, minimizes the number of external components and enables loop stability regardless of the type of output capacitor used, including low ESR ceramic capacitors. The device also incorporates a power saving feature that enables diode emulation mode and frequency fold back as the load decreases. SiC47x integrates a high performance power stage with a n-channel high side MOSFET and a n-channel low side MOSFET optimized to achieve up to 98 % efficiency. SiC47x has a full set of protection and monitoring features: • Over current protection in pulse-by-pulse mode • Output overvoltage protection • Output undervoltage protection with auto retry • Over temperature protection with hysteresis • Dedicated enable pin for easy power sequencing • Power good open drain output • This device is available in MLP55-27L package to deliver high power density and minimize PCB area SPending-Rev. A, 04-Jul-2018 The power input voltage (VIN) can go up to 55 V and down as low as 4.5 V for power conversion. Control Scheme SiC47x employs a voltage mode COT control mechanism in conjunction with adaptive zero current detection which allows for power saving in discontinuous conduction mode (DCM). The switching frequency, fSW, is set by an external resistor to AGND, Rfsw. The SiC47x operates between 100 kHz to 2 MHz depending on VIN and VOUT conditions. V OUT R fsw = --------------------------------------------12 f sw  190  10 Note, as long as VIN and VCIN are connected together, fSW has no dependency on VIN as the on time is adjusted as VIN varies. During steady-state operation, feedback voltage (VFB) is compared with internal reference (0.8 V typ.) and the amplified error signal (VCOMP) is generated at the comp node by the external compensation components, RCOMP and CCOMP. An externally generated ramp signal and VCOMP feed into a comparator. Once VRAMP crosses VCOMP, an on-time Document Number: 75786 6 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com pulse is generated for a fixed time. During the on-time pulse, the high side MOSFET will be turned on. Once the on-time pulse expires, the low side MOSFET will be turned on after a dead time period. The low side MOSFET will stay on for a minimum duration equal to the minimum off-time (tOFF_MIN.) and remains on until VRAMP crosses VCOMP. The cycle is then repeated. Fig. 6 illustrates the basic block diagram for voltage mode, constant on time architecture with external ripple injection, VRAMP, while Fig. 5 illustrates the basic operational principle. Vishay Siliconix VIN Q1 Q2 CIN Ripple based controller L Rx Cx COUT Cy R_FB_H EA RCOMP CCOMP REF Load R_FB_L VRAMP Fig. 6 - SiC47x Control Block Diagram  Below is the equation for calculating the VRAMP amplitude. VCOMP  V IN – V OUT   V OUT V RAMP = ----------------------------------------------------- V IN  f sw  C x  R x  PWM Fixed on-time Fig. 5 - SiC47x Operational Principle  The need for ripple injection in this architecture is explained below. First, let us understand the basic principles of this control architecture: • The reference of a basic voltage mode COT regulator is replaced with a high gain error amplifier loop. The loop ensures the DC component of the output voltage follows the internal accurate reference voltage, providing excellent regulation • A second voltage feedback path via VSNS with a VRAMP scheme ensures rapid correction of the transient perturbation • This establishes two voltage loops, one is the steady state voltage feedback path (via the FB pin) and the other is the feed forward path (via the VSNS pin). The scheme gives the user the fast transient response of a COT regulator and the stable, jitter free, line and load regulation performance of a PWM controller Choosing the Ripple Injection Component Values For stability purposes the SiC47x requires adequate ripple injection amplitude. Adequate ripple amplitude is required for two main reasons: 1. To reduce jitter due to noise coupled into the system 2. To provide stable operation. Sub harmonic oscillation can occur with constant on time ripple control if below condition is not met t ON ESR  C OUT  --------2 Therefore, when the converter design uses an all ceramic output capacitor or other low ESR output capacitors, instability can occur. In order to avoid this, a VRAMP network is used to increase the equivalent RESR in order to satisfy the above condition. The VRAMP amplitude must be large enough to avoid instability or noise sensitivity but not too large that it degrades transient performance. To ensure stable operation under CCM, DCM and ultrasonic mode, minimum VRAMP amplitude of 100 mV is recommended for the SiC47x family of regulators. A maximum VRAMP of 900 mV is recommended so as not to degrade transient response. SPending-Rev. A, 04-Jul-2018 VRAMP amplitude is a function of VIN, VOUT, and switching frequency and should be adjusted whenever VIN, VOUT, or switching frequency is changed. For a given buck regulator design, VOUT and switching frequency is typically fixed, while the converter may be expected to work for a wide VIN range. The VRAMP amplitude will increase as VIN is increased and increase the power dissipated by Rx. A proper selection of RX, package size and value, should take into account the maximum power dissipation at the expected operating conditions. In order to optimize the VRAMP amplitude over a desired VIN range use the following procedure to calculate Rx, Cx, and Cy. 1. The equation below calculates RX as a function of VIN, VOUT, and maximum allowable power dissipated by RX.  V IN_MAX.  V OUT   1 – D  R x = -------------------------------------------------------------------P RX_MAX. where PRX_MAX. is the maximum allowed power dissipation in Rx. Note, the maximum power dissipation of a 0603 sized resistor is typically 25 mW. Power dissipation derating must be taken into account for high ambient temperatures 2. The equation below calculates CX_MIN. as a function of VIN and maximum allowed VRAMP amplitude. P RX_MAX. C X_MIN. = --------------------------------------------------------------------------V IN_MAX.  f sw  V RAMP_MAX. where VRAMP_MAX. = 900 mV 3. Using VRAMP equation, calculate VRAMP_MIN. at minimum VIN based on the Rx and the minimum Cx value calculated above 4. If VRAMP_MIN. is > 200 mV, set Cx to CX_MIN., otherwise set Cx to (Cx_MIN. x VRAMP_MIN./200 mV). If VRIPPLE_MIN. is < 100 mV, increase PRX_MAX. and recalculate RX and CX 5. Cy should be large enough not to distort the VRAMP and small enough not to load excessively the VRAMP network (Rx and Cx). Please use the follow formula: Cy = 1/(0.82 x fsw) This procedure allows for a maximum range of operation. In order to simplify the procedure for calculating VRAMP and compensation components, a calculator is provided (visit www.vishay.com/doc?65124). Document Number: 75786 7 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix Error Amplifier Compensation Value Selection (for reference only) RCOMP and CCOMP in the Fig. 6 are the components used to compensate the control loop. For optimal transient response, the crossover frequency should be: • Set typically at 1/10th to 1/5th of the converter switching frequency (Vishay’s component calculator tool uses 1/10th the converter switching frequency) • Be above the LC filter resonance frequency which is 1/2  LC The procedure to select the RCOMP and CCOMP such that the above conditions are met is as follows: 1. Plot the magnitude and phase of the control to output transfer function using the equation below. Control to output transfer function. 1 + sR C C o   1 + sR x C x    1 + sR y C y  H(s) = A  -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------sL 2 L 2  1 + ------ + s LC o   1 + sR x C x    1 + sRy C y  + AR y C y s  1 + s   R x C x + ------- + s   R x R c C x C o + LC o    Ro Ro Where A = (2VIN x Rx x Cx x f)/VOUT, Rx, Cx, Cy are components for ripple injection as shown in Fig. 6 and Ry is the internal impedance of the VSNS pin and is = 65 k. Co - output capacitance Rc - output capacitor ESR 2. From the plot of the control to output transfer function, determine the gain and phase at the crossover frequency 3. Calculate the RCOMP using the equation 1 R COMP = -------------------------------------G H  gm  r FB where GH is the gain of the transfer function at cross over frequency, “gm” is the transconductance of the error amplifier (300 μS) and rFB is the ratio of the feedback divider, rFB = R_FB_L/(R_FB_L + R_FB_H) 4. Select CCOMP based on the placement of the zero such that phase margin is sufficient at the cross over frequency. A phase margin of over 60° is sufficient for converter stability. A good starting point is to place the compensation zero at 1/5th of the LC pole 5 LC C COMP = ------------------R COMP Once the component values are calculated, it is now possible to calculate the total loop gain. The total loop gain is the product of the control to output transfer function and the error amplifier transfer function. The transfer function of the error amplifier is given by the equation below.  1 + sRCOMP C COMP   r FB G  s  = gmR o  ---------------------------------------------------------------------------------------------------- 1 + s   R COMP C COMP + R o C COMP   Where Ro = 40 M is the output resistance of the transconductance amplifier. Total loop transfer function = H(s)G(s) An automated calculator (visit www.vishay.com/doc?75760) is provided to assist the user to determine VRAMP components as well as error amplifier compensation components using user selected operating conditions. SPending-Rev. A, 04-Jul-2018 Document Number: 75786 8 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Power-Save Mode, Mode Pin, and Ultrasonic Pin Operation To improve efficiency at light-loads, SiC47x provides a set of innovative implementations to reduce low side re-circulating current and switching losses. The internal zero crossing detector monitors SW node voltage to determine when inductor current starts to flow negatively. In power saving mode, as soon as inductor current crosses zero, the device first deploys diode mode by turning off the low side MOSFET. If load further decreases, switching frequency is reduced proportional to the load condition to save switching losses while keeping output ripple within tolerance. If the ultrasonic pin is tied to VDD, the minimum switching frequency in discontinuous mode is > 20 kHz to avoid switching frequencies in the audible range. If this feature is not required ultrasonic mode can be disabled by floating the ULTRASONIC pin. When ultrasonic mode is disabled, the regulator will operate in forced continuous mode or power save mode where there is no limit to the lower frequency limit. In this state, at zero load, switching frequency can go as low as hundreds of hertz. Vishay Siliconix To improve the converter efficiency, the user can choose to disable the internal VDRV regulator by picking either mode 3 or mode 4 and connecting a 5 V supply to the VDRV pin. This reduces power dissipation in the SiC47x by eliminating the VDRV linear regulator losses. The mode pin supports several modes of operation as shown in table 1. An internal current source is used to set the voltage on this pin using an external resistor: TABLE 1 - OPERATION MODES MODE RANGE (k) 1 2 3 4 0 to 100 298 to 304 494 to 504 900 to 1100 POWER SAVE MODE Enabled Disabled Disabled Enabled INTERNAL VDRV REGULATOR ON ON OFF (1) OFF (1) Note (1) Connect a 5 V (± 5 %) supply to the V DRV pin The mode pin is not latched to any state and can be changed on the fly. OUTPUT MONITORING AND PROTECTION FEATURES Output Over-Current Protection (OCP) SiC47x has pulse-by-pulse over current limit control. The inductor current is monitored during low side MOSFET conduction time through RDS(on) sensing. After a pre-defined blanking time, the inductor current is compared with an internal OCP threshold. If inductor current is higher than OCP threshold, high side MOSFET is kept off until the inductor current falls below OCP threshold. OCP is enabled immediately after VDD passes UVLO level. OCP is set by an external resistor, RLIM to AGND. (See table 2) OCPthreshold Iload Iinductor GH Fig. 7 - Over-Current Protection Illustration Output Undervoltage Protection (UVP) UVP is implemented by monitoring the FB pin. If the voltage level at FB drops below 0.16 V for more than 25 μs, a UVP event is recognized and both high side and low side MOSFETs are turned off. After a duration equivalent to 20 soft start periods, the IC attempts to re-start. If the fault condition still exists, the above cycle will be repeated. UVP is only active after the completion of soft-start sequence. Output Over Voltage Protection (OVP) OVP is implemented by monitoring the FB pin. If the voltage level at FB rising above 0.96 V, a OVP event is recognized and both high side and low side MOSFETs are turned off. Normal operation is resumed once FB voltage drop below 0.91 V.   SPending-Rev. A, 04-Jul-2018 Over Temperature Protection (OTP) OTP is implemented by monitoring the junction temperature. If the junction temperature rises above 150 °C, a OTP event is recognized and both high side and low MOSFETs are turned off. After the junction temperature falls below 115 °C (35 °C hysteresis), the device restarts by initiating a soft start sequence. Sequencing of Input / Output Supplies SiC47x has no sequencing requirements on its supplies or enables (VIN, VCIN, VDD, VDRV, EN). Enable The SiC47x has an enable pin to turn the part on and off. Driving this pin above 1.4 V enables the device, while driving the pin below 0.4 V disables the device. The EN pin is internally pulled to AGND by a 5 M resistor to prevent unwanted turn on due to a floating GPIO. Soft-Start During soft start time period, inrush current is limited and the output voltage is ramped gradually. The following control scheme is implemented:  Once the VDD voltage reaches the UVLO trip point, an internal “Soft start Reference” (SR) begins to ramp up. The SR ramp rate is determined by the external soft start capacitor and an internal 5 μA current source tied to the soft start pin. The internal SR signal is used as a reference voltage to the error amplifier (see functional block diagram). The control scheme guarantees that the output voltage during the soft start interval will ramp up coincidently with the SR voltage. The soft-start time, tSS, is adjustable by calculating a capacitor value from the following equation. C ss x 0.8 V t ss = -----------------------------5 μA During soft-start period, OCP is activated. Short circuit protection is not active until soft-start is complete. Document Number: 75786 9 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix Pre-Bias Start-Up Power Good In case of pre-bias startup, output is monitored through FB pin. If the sensed voltage on FB is higher than the internal reference ramp value, control logic prevents high side and low side MOSFETs from switching to avoid negative output voltage spike and excessive current sinking through low side MOSFET. SiC47x’s power good is an open-drain output. Pull PGOOD pin high through a > 10K resistor to use this signal. Power good window is shown in Fig. 9. If voltage on FB pin is out of this window, PGOOD signal is de-asserted by pulling down to AGND. To prevent false triggering during transient events, PGOOD has a 25 μs blanking time. VFB_Rising_Vth_OV (typ. = 0.96 V) VFB_Falling_Vth_OV (typ. = 0.91 V) Vref (0.8 V) VFB_Falling_Vth_UV VFB_Rising_Vth_UV (typ. = 0.72 V) (typ. = 0.77 V) VFB Pull-high PG Pull-low Fig. 9 - PGOOD Window Fig. 8 - Pre-Bias Start-Up EXAMPLE SCHEMATIC OF SiC472 EN R_EN_H R_EN_L 560K Cin_D 0.1 μF 28 30 9 0.1 μF R_PGD 2 SS PGOOD 18 4 19 R_fsw VFB 8.66K Rx Cdrv 60.4 K 52.3 K 23 R_FB_L 22 10K 21 232K Rcomp VSNS SW3 52.3 k 2.2 nF Cy 470pF Ccomp AGND 20 14 SW2 13 VDRV SW1 12 Analog ground (AGND), and power ground (PGND) are tied internally in the SiC47x 15 GL COMP 16 47μF 2K 1 μF 24 AGND PGND 1 Cdd Rlim FSW PGND2 11 PGND3 17 PGND 26 ILIMIT 25 10 Cin 33nF Rmode Mode 27 VDD SiC472 PGND -PAD Css 102K BOOT 3.3 5 A GND -PAD PGOOD Zero Ohm ultrasonic select ULTRASONIC VIN-PAD 7 VIN 1 8 VIN 2 PHASE1 1 VCIN 29 C_boot R_boot 6 PHASE2 EN 3 Notes in small black text near component values refer to Vishay SiC47x spreadsheet calcualtor references. +VIN 6V to 55 V DNP R_U_SONIC R_FB_H 1.8 nF 4.7 μH Cx L +Vout = 5 V 0.1 μF 4.7 μF Cout_D 64 μF Cout_C 64 μF Cout_B PGND Fig. 10 - SiC472 Configured for 6 V to 55 V Input, 5 V Output at 6 A, 500 kHz Operation with Ultrasonic Power Save Mode Enabled all Ceramic Output Capacitance Design SPending-Rev. A, 04-Jul-2018 Document Number: 75786 10 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix EXTERNAL COMPONENT SELECTION FOR THE SiC47x This section explains external component selection for the SiC47x family of regulators. Component reference designators in any equation refer to the schematic shown in Fig. 10. An excel based calculator is available on the website to make external component calculation simple. The user simply needs to enter required operating conditions. Output Voltage Adjustment If a different output voltage is needed, simply change the value of VOUT and solve for R_FB_H based on the following formula: R _FB_L  V OUT - VFB  R _FB_H = ----------------------------------------------------V FB where VFB is 0.8 V. R_FB_L should be a maximum of 10 k to prevent VOUT from drifting at no load. Switching Frequency Selection The following equation illustrates the relationship between frequency, VIN, VOUT, and Rfsw value: V OUT R fsw = --------------------------------------------------– 12 f sw x  190 x 10  Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values allow for the use of smaller package sizes but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current and, for a given DC resistance, are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are all used in the selection process. The ripple current will also set the boundary for power save operation. The SiC47x will typically enter power save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 1.8 A, power save operation will be active for loads less than 0.9 A. If ripple current is set at 30 % of maximum load current, power save will typically start at a load which is 15 % of maximum current. The inductor value is typically selected to provide ripple current of 25 % to 50 % of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the on-time, voltage across the inductor is (VIN - VOUT). The equations for determining inductance are shown below. V OUT t ON = -----------------------V IN x f sw and  V IN - VOUT  x t ON L = -------------------------------------------------I OUT_MAX. x K where, K is the maximum percentage of ripple current. The designer can quickly make a choice of inductor if the ripple percentage is decided, usually no more than 30 % however higher or lower percentages of IOUT can be acceptable SPending-Rev. A, 04-Jul-2018 depending on application. This device allows choices larger than 30 %. Other than the inductance the DCR and saturation current parameters are key values. The DCR causes an I2R loss which will decrease the system efficiency and generate heat. The saturation current has to be higher than the maximum output current plus ½ of the ripple current. In an over current condition the inductor current may be very high. All this needs to be considered when selecting the inductor. Output Capacitor Selection The SiC47x is stable with any type of output capacitors by choosing the appropriate VRAMP components. This allows the user to choose the output capacitance based on the best trade off of board space, cost and application requirements. The output capacitors are chosen based upon required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple voltage requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus half of the peak-to-peak ripple. A change in the output ripple voltage will lead to a change in DC voltage at the output. The relationship between output voltage ripple, output capacitance and ESR of the output capacitor is shown by the following equation: 1 V RIPPLE = I RIPPLE  MAX.  x  --------------------------------- + ESR  8 x C o x f sw   (1) Where VRIPPLE is the maximum allowed output ripple voltage; IRIPPLE(MAX.) is the maximum inductor ripple current; fsw is the switching frequency of the converter; Co is the total output capacitance; ESR is the equivalent series resistance of the total output capacitors. In addition to the output ripple voltage requirement, the output capacitors need to meet transient requirements. A worst case load release condition (from maximum load to no load at the exact moment when inductor current is at the peak) determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero within 1 μs), the output capacitor must absorb all the energy stored in the inductor. The peak voltage on the capacitor, VPK, under this worst case condition can be calculated by following equation: 2 1 L x  I OUT + --- x I RIPPLE(MAX.)   2 = ------------------------------------------------------------------------------2 2  V PK  -  V OUT   (2) C OUT_MIN.   During the load release time, the voltage across the inductor is approximately -VOUT. This causes a down-slope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt of the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor; therefore a smaller capacitance can be used. The following can be used to calculate the required capacitance for a given diLOAD/dt. Document Number: 75786 11 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix Peak inductor current, ILPK, is shown by the next equation: I LPK 1 = I MAX. + --- x I RIPPLE(MAX.) 2 di LOAD The slew rate of load current = ------------------dt   (3) C OUT_MIN. = I LPK   Based on application requirement, either equation (2) or equation (3) can be used to calculate the ideal output capacitance to meet transition requirement. Compare this calculated capacitance with the result from equation (1) and choose the larger value to meet both ripple and transition requirement. I LPK I MAX. L x -------------- - ------------------- x dt V OUT dI LOAD x --------------------------------------------------------------2  V PK - V OUT  Enable Pin Voltage The EN pin has an internal 5 M pull down resistor connected to AGND. In order to enable the device, an external signal greater than 1.4 V is required. The enable can also be used to set the minimum VCIN, VIN startup voltage by connecting a voltage divider between VIN, EN, and PGND. An automated calculator is available to assist in component selection. Current Limit Resistor I VCIN  RMS  = IO x 2 V OUT 2 1 D x  1 – D  + ------   -------------------------------------   1 – D   D 12  L  ƒ sw  I OUT The minimum input capacitance can then be found, D x 1 - D C VIN_MIN. = I OUT x ----------------------------------------V IN_PK-PK x f sw  If high ESR capacitors are used, it is good practice to also add low ESR ceramic capacitance. A 4.7 μF ceramic input capacitance is a suitable starting point. Note, account for voltage derating of capacitance when using all ceramic input capacitors. Efficiency Measurement Fig. 11 to 39 in the following pages are the efficiency data for the SiC471, SiC472, SiC473, and SiC474. The measurements are taken based on the Vishay 6 layers, 2 ounce copper evaluation board. The inductors used in the measurement are tabulated below. TABLE 3 - INDUCTOR VALUES DEVICE PART The current limit is set by placing a resistor between ILIM and AGND. The values can be found using the following equation: SiC471 K LIM R LIM (k  = --------------------------------------------------------------------------------------- V IN – V OUT   V OUT I OUT_MAX. – -----------------------------------------------------2  f sw  V IN  L Where SiC472 INDUCTANCE (μH) INDUCTOR PART NUMBER DCR (m) 3.3 IHLP6767GZER3R3M11 2.79 4.7 IHLP6767GZER4R7M11 3.98 6.8 IHLP6767GZER6R8M11 5.86 8.2 IHLP6767GZER8R2M11 7.71 10 IHLP6767GZER100M11 8.89 5.6 IHLP5050FDER5R6M51 8.51 6.8 IHLP5050FDER6R8M51 11.30 8.2 IHLP5050FDER8R2M51 13.20 • IOUT_MAX. is desired DC current limit level 10 IHLP5050FDER100M51 16.60 • KLIM is determined by Table 2 15 IHLP5050FDER150M51 24.00 10 IHLP5050FDER100M51 16.60 15 IHLP5050FDER150M51 24.00 22 IHLP5050FDER220M51 31.30 10 IHLP5050FDER100M51 16.60 15 IHLP5050FDER150M51 24.00 22 IHLP5050FDER220M51 31.30 TABLE 2 - KLIM VALUE AND RLIM RANGE PART NUMBER KLIM RLIM MIN. / MAX. VALUE SiC471 900K 30K / 900K SiC472 600K 30K / 600K SiC473 420K 30K / 420K SiC474 300K 30K / 300K SiC473 SiC474 Note • It is suggested that the current limit setting not be higher than 2 times the rated current of the part. Be sure max. current limit is within the saturation current of the inductor Input Capacitance In order to determine the minimum capacitance the input voltage ripple needs to be specified; VIN_PK-PK  500 mV is a suitable starting point. This magnitude is determined by the final application specification. The input current needs to be determined for the lowest operating input voltage, SPending-Rev. A, 04-Jul-2018 Document Number: 75786 12 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC471 (12 A), unless otherwise noted) 100 100 VIN = 12 V, L = 3.3 μH 97 96 94 94 91 92 Efficiency (%) Efficiency (%) VIN = 12 V, L = 3.3 μH 98 VIN = 24 V, L = 4.7 μH 90 88 VIN = 36 V, L = 4.7 μH 86 85 VIN = 24 V, L = 4.7 μH 82 VIN = 36 V, L = 4.7 μH 79 VIN = 48 V, L = 4.7 μH 84 76 82 73 VIN = 48 V, L = 4.7 μH 70 80 0 1 2 3 4 5 6 7 8 9 10 11 12 0.01 0.1 Output Current, IOUT (A) Fig. 11 - SiC471 Efficiency vs. Output Current, VOUT = 5 V Fig. 14 - SiC471 Efficiency vs. Output Current - Light Load, VOUT = 5 V 100 100 98 97 96 94 VIN = 24 V, L = 6.8 μH 91 92 90 Efficiency (%) VIN = 36 V, L = 8.2 μH VIN = 48 V, L = 10 μH 88 VIN = 24 V, L = 6.8 μH 88 VIN = 36 V, L = 8.2 μH 85 VIN = 48 V, L = 10 μH 82 86 79 84 76 82 73 80 70 0 1 2 3 4 5 6 7 8 9 0.01 10 11 12 0.1 1 Output Current, IOUT (A) Output Current, IOUT (A) Fig. 12 - SiC471 Efficiency vs. Output Current, VOUT = 12 V Fig. 15 - SiC471 Efficiency vs. Output Current - Light Load, VOUT = 12 V Axis Title Axis Title 10000 100 10000 100 90 1000 1st line 2nd line 70 60 50 100 40 30 80 1000 70 1st line 2nd line 80 2nd line TC - Case Temperature (°C) 90 2nd line TC - Case Temperature (°C) 1 Output Current, IOUT (A) 94 Efficiency (%) 88 60 50 100 40 30 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12 IOUT - Output Current (A) Fig. 13 - SiC471 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 5 V SPending-Rev. A, 04-Jul-2018 10 20 0 1 2 3 4 5 6 7 8 9 10 11 12 IOUT - Output Current (A) Fig. 16 - SiC471 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 12 V Document Number: 75786 13 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC472 (8 A), unless otherwise noted) 100 VIN = 12 V, L = 5.6 μH VIN = 12 V, L = 5.6 μH 98 97 96 94 94 91 92 Efficiency (%) Efficiency (%) 100 VIN = 24 V, L = 6.8 μH 90 VIN = 36 V, L = 8.2 μH 88 VIN = 48 V, L = 8.2 μH 86 88 85 82 VIN = 36 V, L = 8.2 μH 79 84 76 82 73 80 VIN = 48 V, L = 8.2 μH 70 0 1 2 3 4 5 6 7 0.01 8 0.1 Output Current, IOUT (A) Fig. 17 - SiC472 Efficiency vs. Output Current, VOUT = 5 V Fig. 20 - SiC472 Efficiency vs. Output Current - Light Load, VOUT = 5 V 100 100 98 97 96 94 90 Efficiency (%) 92 VIN = 24 V, L = 10 μH 91 VIN = 24 V, L = 10 μH VIN = 36 V, L = 15 μH VIN = 48 V, L = 15 μH 88 88 VIN = 36 V, L = 15 μH 85 82 86 79 84 76 82 73 80 VIN = 48 V, L = 15 μH 70 0 1 2 3 4 5 6 7 8 0.01 0.1 1 Output Current, IOUT (A) Output Current, IOUT (A) Fig. 18 - SiC472 Efficiency vs. Output Current, VOUT = 12 V Fig. 21 - SiC472 Efficiency vs. Output Current - Light Load, VOUT = 12 V Axis Title Axis Title 10000 100 10000 100 90 1000 1st line 2nd line 70 60 50 100 40 30 80 1000 70 1st line 2nd line 80 2nd line TC - Case Temperature (°C) 90 2nd line TC - Case Temperature (°C) 1 Output Current, IOUT (A) 94 Efficiency (%) VIN = 24 V, L = 6.8 μH 60 50 100 40 30 10 20 0 1 2 3 4 5 6 7 8 IOUT - Output Current (A) Fig. 19 - SiC472 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 5 V SPending-Rev. A, 04-Jul-2018 10 20 0 1 2 3 4 5 6 7 8 IOUT - Output Current (A) Fig. 22 - SiC472 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 12 V Document Number: 75786 14 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC473 (5 A), unless otherwise noted) 100 100 VIN = 12 V, L = 10 μH 97 96 94 94 91 92 Efficiency (%) Efficiency (%) 98 VIN = 24 V, L = 15 μH VIN = 36 V, L = 15 μH 90 88 VIN = 48 V, L = 15 μH VIN = 12 V, L = 10 μH VIN = 24 V, L = 15 uH 88 85 82 86 79 84 76 82 73 VIN = 36 V, L = 15 μH VIN = 48 V, L = 15 μH 70 80 0 1 2 3 4 5 6 0.01 0.1 1 Output Current, IOUT (A) Output Current, IOUT (A) Fig. 23 - SiC473 Efficiency vs. Output Current, VOUT = 5 V Fig. 26 - SiC473 Efficiency vs. Output Current - Light Load, VOUT = 5 V 100 100 98 97 VIN = 24 V, L = 15 μH 96 94 VIN = 24 V, L = 15 μH VIN = 36 V, L = 22 μH 91 Efficiency (%) Efficiency (%) 94 92 VIN = 48 V, L = 22 μH 90 88 88 VIN = 48 V, L = 22 μH 82 86 79 84 76 82 73 80 VIN = 36 V, L = 22 μH 85 70 0 1 2 3 4 5 6 0.01 0.1 Output Current, IOUT (A) Output Current, IOUT (A) Fig. 24 - SiC473 Efficiency vs. Output Current, VOUT = 12 V Fig. 27 - SiC473 Efficiency vs. Output Current - Light Load, VOUT = 12 V Axis Title Axis Title 10000 100 10000 100 90 1000 1st line 2nd line 70 60 50 100 40 30 80 1000 70 1st line 2nd line 80 2nd line TC - Case Temperature (°C) 90 2nd line TC - Case Temperature (°C) 1 60 50 100 40 30 10 20 0 1 2 3 4 5 IOUT - Output Current (A) Fig. 25 - SiC473 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 5 V SPending-Rev. A, 04-Jul-2018 10 20 0 1 2 3 4 5 IOUT - Output Current (A) Fig. 28 - SiC473 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 12 V Document Number: 75786 15 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC474 (3 A), unless otherwise noted) 100 100 VIN = 12 V, L = 10 μH 97 96 94 94 91 92 Efficiency (%) Efficiency (%) 98 VIN = 24 V, L = 15 μH 90 VIN = 36 V, L = 15 μH 88 VIN = 48 V, L = 15 μH 86 88 85 VIN = 36 V, L = 15 μH 82 79 84 76 82 73 VIN = 48 V, L = 15 μH 70 80 0 1 2 3 4 0.01 0.1 Output Current, IOUT (A) Fig. 29 - SiC474 Efficiency vs. Output Current, VOUT = 5 V Fig. 32 - SiC474 Efficiency vs. Output Current - Light Load, VOUT = 5 V 100 100 98 97 VIN = 24 V, L = 15 μH 94 VIN = 24 V, L = 15 μH 94 91 92 Efficiency (%) VIN = 36 V, L = 22 μH VIN = 48 V, L = 22 μH 90 88 88 VIN = 36 V, L = 22 μH 85 VIN = 48 V, L = 22 μH 82 86 79 84 76 82 73 80 70 0 1 2 3 4 0.01 0.1 1 Output Current, IOUT (A) Output Current, IOUT (A) Fig. 30 - SiC474 Efficiency vs. Output Current, VOUT = 12 V Fig. 33 - SiC474 Efficiency vs. Output Current - Light Load, VOUT = 12 V Axis Title Axis Title 10000 100 10000 100 90 1000 1st line 2nd line 70 60 50 100 40 30 80 1000 70 1st line 2nd line 80 2nd line TC - Case Temperature (°C) 90 2nd line TC - Case Temperature (°C) 1 Output Current, IOUT (A) 96 Efficiency (%) VIN = 12 V, L = 10 μH VIN = 24 V, L = 15 μH 60 50 100 40 30 10 20 0 1 2 3 IOUT - Output Current (A) Fig. 31 - SiC474 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 5 V SPending-Rev. A, 04-Jul-2018 10 20 0 1 2 3 IOUT - Output Current (A) Fig. 34 - SiC474 Load Current vs. Case Temperature, VIN = 48 V, VOUT = 12 V Document Number: 75786 16 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC472 (8 A), unless otherwise noted) Axis Title Axis Title 10000 1.04 1.03 1.03 1.01 1.00 0.99 100 0.98 0.97 1000 1.01 1st line 2nd line 1000 2nd line Normalized Efficiency 1.02 1.02 1st line 2nd line 2nd line Normalized Efficiency 10000 1.04 1.00 0.99 100 0.98 0.97 0.96 0.96 0 0.95 10 100 200 300 400 500 600 700 800 900 1000 0 10 100 200 300 400 500 600 700 800 900 1000 fsw - Switching Frequency (kHz) fsw - Switching Frequency (kHz) Fig. 38 - SiC472 Efficiency vs. Switching Frequency Fig. 35 - SiC471 Efficiency vs. Switching Frequency Axis Title Axis Title 10000 1.04 1000 1.01 1.00 0.99 100 0.98 0.97 1.02 1000 1.01 1st line 2nd line 1.02 2nd line Normalized Efficiency 1.03 1st line 2nd line 2nd line Normalized Efficiency 1.03 1.00 0.99 100 0.98 0.97 0.96 0 10 100 200 300 400 500 600 700 800 900 1000 0.96 0 fsw - Switching Frequency (kHz) Fig. 39 - SiC474 Efficiency vs. Switching Frequency 808 1.75 806 Voltage Reference, VFB (mv) 2.00 1.50 1.25 1.00 0.75 804 802 800 798 0.50 796 0.25 794 0.00 10 100 200 300 400 500 600 700 800 900 1000 fsw - Switching Frequency (kHz) Fig. 36 - SiC473 Efficiency vs. Switching Frequency Normalized On-State Resistance, RDSON 10000 1.04 792 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) Fig. 37 - RDS(ON) vs. Temperature Fig. 40 - Voltage Reference vs. Temperature SPending-Rev. A, 04-Jul-2018 Document Number: 75786 17 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC472 (8 A), unless otherwise noted) Axis Title Axis Title 10000 0.8 0.6 1000 1st line 2nd line 0.2 0 -0.2 100 -0.4 -0.6 0.4 1000 0.2 1st line 2nd line 0.4 2nd line Load Regulation (%) 0.6 2nd line Line Regulation (%) 10000 0.8 0 -0.2 100 -0.4 -0.6 10 -0.8 0 6 12 18 24 30 36 42 48 54 10 -0.8 60 0 1 2 VIN - Input Voltage (V) 5 6 7 8 Fig. 44 - Load Regulation 8.0 Shutdown Current, IVCIN_SHDN + IVIN_SHDN (uA) 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 5 10 15 20 25 30 35 40 45 50 55 -60 -40 -20 0 Input Voltage, VCIN / VIN (V) 20 40 60 80 100 120 140 Temperature (°C) Fig. 45 - Shutdown Current vs. Junction Temperature Fig. 42 - Shutdown Current vs. Input Voltage 300 300 280 280 Input Current, IVCIN + IVIN (uA) Input Current, IVCIN + IVIN (uA) 4 IOUT - Output Current (A) Fig. 41 - Line Regulation Shutdown Current, IVCIN_SHDN + IVIN_SHDN (uA) 3 260 240 220 200 180 160 260 240 220 200 180 160 140 5 10 15 20 25 30 35 40 45 50 Input Voltage, VCIN / VIN (V) Fig. 43 - Input Current vs. Input Voltage SPending-Rev. A, 04-Jul-2018 55 140 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 46 - Input Current vs. Junction Temperature Document Number: 75786 18 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC472 (8 A), unless otherwise noted) Axis Title Axis Title 10000 1.5 1.4 10000 VEN = 5.0 V 1.2 100 VIL_EN 1.2 1000 1.1 1st line 2nd line 1.3 2nd line EN Current, IEN (µA) 1000 VIH_EN 1st line 2nd line 2nd line VEN - EN Logic Threshold (V) 1.3 1.4 1 0.9 100 0.8 1.1 0.7 10 1 -60 -40 -20 0 20 40 60 80 100 120 140 T - Temperature (°C) 10 0.6 -60 -40 -20 0 20 40 60 80 100 120 140 T - Temperature (°C) Fig. 47 - EN Logic Threshold vs. Junction Temperature Fig. 50 - EN Current vs. Junction Temperature Fig. 48 - Load Transient (3 A to 6 A), Time = 100 μs/div Fig. 51 - Line Transient (8 V to 48 V), Time = 10 ms/div Fig. 49 - Start-Up with EN, Time = 1 ms/div Fig. 52 - Start-up with VIN, Time = 5 ms/div SPending-Rev. A, 04-Jul-2018 Document Number: 75786 19 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC472 (8 A), unless otherwise noted) Fig. 53 - Output Ripple 2 A, Time = 5 μs/div Fig. 55 - Output Ripple 300 mA, Time = 5 μs/div Fig. 54 - Output Ripple PSM, Time = 10 ms/div SPending-Rev. A, 04-Jul-2018 Document Number: 75786 20 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix PCB LAYOUT RECOMMENDATIONS VIN Plane PGND Plane VIN Snubber Step 3: SW Plane Step 1: VIN/GND Planes and Decoupling VSWH PGND Plane VSWH Fig. 58 Fig. 56 1. Layout VIN and PGND planes as shown above 2. Ceramic capacitors should be placed between VIN and PGND, and very close to the device for best decoupling effect 1. Connect output inductor to device with large plane to lower resistance 2. If any snubber network is required, place the components on the bottom side as shown above Step 4: VDD/VDRV Input Filter 3. Various ceramic capacitor values and package sizes should be used to cover entire coupling spectrum e.g. 1210 and 0603 4. Smaller capacitance values, closer to VIN pin(s), provide better high frequency response Step 2: VCIN Pin AGND Vcin decouple cap P G N D AGND Plane Fig. 57 Fig. 59 1. VCIN is the input pin for both internal LDO and tON block. tON varies with input voltage and it is necessary to put a decoupling capacitor close to this pin 1. CVDD cap should be placed between VDD and AGND to achieve best noise filtering 2. The connection can be made through a via and the capacitor can be placed at bottom layer SPending-Rev. A, 04-Jul-2018 2. CVDRV cap should be placed close to VDRV and PGND pins to reduce effects of trace impedance and provide maximum instantaneous driver current for low side MOSFET during switching cycle Document Number: 75786 21 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Step 5: BOOT Resistor and Capacitor Placement Vishay Siliconix Step 6: Signal Routing AGND plane PGND F B Fig. 60 s i g Ripple n injection a l circuit 1. CBOOT and RBOOT need to be placed very close to the device, between PHASE and BOOT pins 2. In order to reduce parasitic inductance, it is recommended to use 0402 chip size for the resistor and the capacitor               Fig. 61 1. Separate the small analog signal from high current path. As shown above, the high current paths with high dv/dt, di/dt are placed on the left side of the IC, while the small control signals are placed on the right side of the IC. All the components for small analog signal should be placed closer to IC with minimum trace length 2. IC analog ground (AGND), pin 23, should have a single connection to PGND. The AGND ground plane connected to pin 23 helps to keep AGND quiet and improves noise immunity 3. Feedback signal can be routed through inner layer. Make sure this signal is far from SW node and shielded by inner ground layer 4. Ripple injection circuit can be placed next to inductor. Kelvin connection as shown above is recommended               SPending-Rev. A, 04-Jul-2018 Document Number: 75786 22 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Step 7: Adding Thermal Relief Vias and Duplicate Power Path Plane VIN Plane Vishay Siliconix Step 8: Ground Layer AGND Plane PGND Plane PGND Plane VSWH Fig. 62 1. Thermal relief vias can be added on the VIN and PGND pads to utilize inner layers for high current and thermal dissipation 2. To achieve better thermal performance, additional vias can be placed on VIN and PGND planes. It is also necessary to duplicate the VIN and ground plane at bottom layer to maximize the power dissipation capability of the PCB 3. SW pad is a noise source and it is not recommended to place vias on this pad 4. 8 mil vias on pads and 10 mil vias on planes are ideal via sizes. The vias on pad may drain solder during assembly and cause assembly issues. Please consult with the assembly house for guideline SPending-Rev. A, 04-Jul-2018 Fig. 63 1. It is recommended to make the entire inner layer (next to top layer) ground plane 2. This ground plane provides shielding between noise source on top layer and signal trace within inner layer 3. The ground plane can be broken into two sections, PGND and AGND Document Number: 75786 23 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix PACKAGE INFORMATION 2x 0.08 C K4 Top view K5 e1 x 3 K K7 e2 e D2-3 6 K4 E2-4 E2- 3 F1 Side view K2 D2-2 7 K6 12 F2 C K3 11 11 12 7 27 20 D2-4 L1 ex2 B ex2 e3 e1 K8 Bottom view 2x 0.10 C A e1 b1 b E MLP55-27L (5 mm x 5 mm) 6 DIM. 1 D2-1 ex4 (4) 19 K1 19 1 K4 ex7 L A2 K4 27 20 A1 E2-1 A D 0.10 M C A B 0.05 M C A E2- 2 0.10 C A Pin 1 dot by marking MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A (8) 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 A2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.008 0.010 0.012 b1 0.15 0.20 0.25 0.006 0.008 0.010 D 4.90 5.00 5.10 0.193 0.197 0.201 e 0.50 BSC 0.020 BSC e1 0.65 BSC 0.026 BSC e2 1.00 BSC 0.039 BSC e3 1.13 BSC 0.044 BSC E 4.90 5.00 5.10 0.193 0.197 0.201 L 0.35 0.40 0.45 0.014 0.016 0.018 L1 0.97 1.02 1.07 0.038 0.040 0.042 N (3) 28 28 D2-1 3.25 3.30 3.35 0.128 0.130 0.132 D2-2 0.95 1.00 1.05 0.037 0.039 0.041 D2-3 1.95 2.00 2.05 0.077 0.079 0.081 D2-4 1.37 1.42 1.47 0.054 0.056 0.058 E2-1 0.95 1.00 1.05 0.037 0.039 0.041 E2-2 2.55 2.60 2.65 0.100 0.102 0.104 E2-3 2.55 2.60 2.65 0.100 0.102 0.104 E2-4 1.58 1.63 1.68 0.062 0.064 0.066 F1 0.20 - 0.25 0.008 - 0.010 F2 SPending-Rev. A, 04-Jul-2018 min. 0.20 min. 0.008 Document Number: 75786 24 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com DIM. Vishay Siliconix MILLIMETERS MIN. NOM. INCHES MAX. MIN. NOM. K 0.40 BSC 0.016 BSC K1 0.70 BSC 0.028 BSC K2 0.70 BSC 0.028 BSC K3 0.30 BSC 0.012 BSC K4 0.75 BSC 0.030 BSC K5 0.80 BSC 0.0315 BSC K6 0.60 BSC 0.024 BSC K7 1.25 BSC 0.049 BSC K8 0.975 BSC 0.038 BSC MAX. ECN: T18-0037-Rev. A, 29-Jan-18 DWG: 6063 Notes (1) Use millimeters as the primary measurement (2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994 (3) N is the number of terminals Nd is the number of terminals in x-direction and Ne is the number of terminals in y-direction (4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip (5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body (6) Exact shape and size of this feature is optional (7) Package warpage max. 0.08 mm (8) Applied only for terminals SPending-Rev. A, 04-Jul-2018 Document Number: 75786 25 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Work-In-Progress SiC471, SiC472, SiC473, SiC474 www.vishay.com Vishay Siliconix PRODUCT SUMMARY Part number Description SiC471 SiC472 SiC473 SiC474 3 A, 4.5 V to 55 V input, 5 A, 4.5 V to 55 V input, 12 A, 4.5 V to 55 V input, 8 A, 4.5 V to 55 V input, 100 kHz to 2 MHz, 100 kHz to 2 MHz, 100 kHz to 2 MHz, 100 kHz to 2 MHz, synchronous microBUCK synchronous microBUCK synchronous microBUCK synchronous microBUCK regulator regulator regulator regulator Input voltage min. (V) 4.5 4.5 4.5 Input voltage max. (V) 55 55 55 4.5 55 Output voltage min. (V) 0.8 0.8 0.8 0.8 Output voltage max. (V) 0.92 x VIN 0.92 x VIN 0.92 x VIN 0.92 x VIN Continuous current (A) 12 8 5 3 Switch frequency min. (kHz) 100 100 100 100 Switch frequency max. (kHz) 2000 2000 2000 2000 Pre-bias operation (yes / no) Yes Yes Yes Yes Internal bias reg. (yes / no) Yes Yes Yes Yes External External External External Enable (yes / no) Yes Yes Yes Yes PGOOD (yes / no) Yes Yes Yes Yes Compensation Over current protection Yes Yes Yes Yes Protection OVP, OCP, UVP/SCP, OTP, UVLO OVP, OCP, UVP/SCP, OTP, UVLO OVP, OCP, UVP/SCP, OTP, UVLO OVP, OCP, UVP/SCP, OTP, UVLO Light load mode Selectable powersave / ultrasonic Selectable powersave / ultrasonic Selectable powersave / ultrasonic Selectable powersave / ultrasonic 98 98 98 98 PowerPAK MLP55-27L PowerPAK MLP55-27L PowerPAK MLP55-27L PowerPAK MLP55-27L 5 x 5 x 0.75 5 x 5 x 0.75 5 x 5 x 0.75 5 x 5 x 0.75 Status code 1 1 1 1 Product type microBUCK (step down regulator) microBUCK (step down regulator) microBUCK (step down regulator) microBUCK (step down regulator) Applications Computing, consumer, industrial, healthcare, networking Computing, consumer, industrial, healthcare, networking Computing, consumer, industrial, healthcare, networking Computing, consumer, industrial, healthcare, networking Peak efficiency (%) Package type Package size (W, L, H) (mm)                           Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?75786. SPending-Rev. A, 04-Jul-2018 Document Number: 75786 26 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000