SiC762CD
Vishay Siliconix
Integrated DrMOS Power Stage
• FEATURES
• Integrated Gen III MOSFETs and DrMOS
compliant gate driver IC
• Enables Vcore switching at 1 MHz
• Easily achieve > 90 % efficiency in multi-phase,
low output voltage solutions
• Low ringing on the VSWH pin reduces EMI
• Pin compatible with DrMOS 6 x 6 version 3.0
• Tri-state PWM input function prevents negative output
voltage swing
• 5 V logic levels on PWM
• MOSFET threshold voltage optimized for 5 V driver bias
supply
• Automatic skip mode operation (SMOD) for light load
efficiency
• Under-voltage lockout
• Built-in bootstrap schottky diode
• Adaptive deadtime and shoot through protection
• Thermal shutdown warning flag
• Low profile, thermally enhanced PowerPAK® MLP 6 x 6
40 pin package
• Halogen-free according to IEC 61249-2-21 definition
• Compliant to RoHS directive 2002/95/EC
DESCRIPTION
The SiC762CD is an integrated solution that contains PWM
optimized n-channel MOSFETs (high side and low side) and
a full featured MOSFET driver IC. The device complies with
the Intel DrMOS standard for desktop and server Vcore power
stages. The SiC762CD delivers up to 35 A continuous output
current and operates from an input voltage range of 3 V to
27 V. The integrated MOSFETs are optimized for output
voltages in the ranges of 0.8 V to 2.0 V with a nominal input
voltage of 24 V. The device can also deliver very high power
at 5 V output for ASIC applications.
The SiC762CD incorporates an advanced MOSFET gate
driver IC. This IC accepts a single PWM input from the VR
controller and converts it into the high side and low side
MOSFET gate drive signals. The driver IC is designed to
implement the skip mode (SMOD) function for light load
efficiency improvement. Adaptive dead time control also
works to improve efficiency at all load points. The SiC762CD
has a thermal warning (THDN) that alerts the system of
excessive junction temperature. The driver IC includes an
enable pin, UVLO and shoot through protection.
The SiC762CD is optimized for high frequency buck
applications. Operating frequencies in excess of 1 MHz can
easily be achieved.
The SiC762CD is packaged in Vishay Siliconix high
performance PowerPAK MLP6 x 6 package. Compact
co-packaging of components helps to reduce stray
inductance, and hence increases efficiency.
APPLICATIONS
• CPU and GPU core voltage regulation
• Server, computer, workstation, game console, graphics
boards, PC
SIC762CD APPLICATION DIAGRAMM
5V
VIN
VIN
GH
VDRV
VCIN
SMOD
BOOT
Gate Driver
PWM
Controller
DSBL#
PWM
VSWH
VO
PHASE
THDN
SiC762CD
PGND
GL
CGND
Figure 1
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
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SiC762CD
Vishay Siliconix
ORDERING INFORMATION
Part Number
Package
SiC762CD-T1-GE3
PowerPAK MLP66-40
SiC762DB
Reference board
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Min.
Max.
VIN
- 0.3
30
Switch Node Voltage (DC)
VSW
- 0.3
30
Drive Input Voltage
VDRV
- 0.3
7.0
Input Voltage
Control Input Voltage
Logic Pins
Boot Voltage DC (referenced to CGND)
Boot to Phase Voltage DC
VCIN
- 0.3
7.0
VPWM, VDSBL#,
VTHDN, VSMOD
- 0.3
VCIN + 0.3
VBS
- 0.3
33
- 0.3
7
VBS_PH
Boot to Phase Voltage < 200 ns
TA
Ambient Temperature Range
- 0.3
9
- 40
125
TJ
Maximum Junction Temperature
150
TSTG
Storage Junction Temperature
- 65
Soldering Peak Temperature
Note:
a. TA = 25 °C and all voltages referenced to PGND = CGND unless otherwise noted.
150
Unit
V
°C
260
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min.
Typ.
Max.
VIN
3.0
12
24
Control Input Voltage
VCIN
4.5
5.5
Drive Input Voltage
VDRV
4.5
5.5
Input Voltage
Switch Node
VSW_DC
12
Unit
V
24
Note:
a. Recommended operating conditions are specified over the entire temperature range, and all voltages referenced to PGND = CGND unless
otherwise noted.
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Maximum Power Dissipation at TPCB = 25 °C
PD_25C
25
Maximum Power Dissipation at TPCB = 100 °C
PD_100C
10
Thermal Resistance from Junction to Top
Rth_J_TOP
15
Thermal Resistance from Junction to PCB
Rth_J_PCB
5
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Typ.
Max.
Unit
W
°C/W
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VDSBL# = VSMOD = 5 V,
VIN = 12 V, VVDRV = VVCIN = 5 V,
TA = 25 °C
Min.
Typ.a
Max.
Unit
Power Supplies
VCIN Control Input Current
Drive Input Current (Dynamic)
IVCIN
IVDRV
VDSBL# = 0 V, no switching
21
VDSBL# = 5 V, no switching
350
VDSBL# = 5 V, fs = 300 kHz, D = 0.1
500
µA
fs = 300 kHz, D = 0.1
14
18
fs = 1000 kHz, D = 0.1
40
54
VVCIN = 5 V, forward bias current 2 mA
0.60
0.75
mA
Bootstrap Supply
Bootstrap Switch Forward Voltage
VBS Diode
V
Control Inputs (PWM, DSBL#, SMOD)
PWM Rising Threshold
Vth_pwm_r
3.5
3.9
4.2
PWM Falling Threshold
Vth_pwm_f
0.8
1.0
1.2
Vth_tri_r
0.9
1.3
1.8
PWM Tristate Falling Threshold
Vth_tri_f
3.4
3.7
4.0
PWM Tristate Rising Threshold Hysteresis
Vhys_tri_r
280
PWM Tristate Falling Threshold Hysteresis
Vhys_tri_f
180
PWM Tristate Rising Threshold
Tristate Hold-Off Timeb
PWM Input Current
SMOD, DSBL# Logic Input Voltage
tTSHO
IPWM
250
VPWM = 0 V
- 250
VLOGIC_LH
Rising (low to high)
VLOGIC_LH
Falling (high to low)
Pull Down Impedance
RTHDN
THDN Output Low
VTHDNL
mV
150
VPWM = 5 V
ns
µA
2.0
0.8
5 kΩ resistor pull-up to VCIN
V
V
40
Ω
0.04
V
Protection
Thermal Warning Flag Set
150
Thermal Warning Flag Clear
135
Thermal Warning Flag Hysteresis
15
Under Voltage Lockout VCIN
Under Voltage Lockout VCIN
VUVLO
Under Voltage Lockout Hysteresis VCIN
VUVLO_HYST
High Side Gate Discharge Resistorb
RHS_DSCRG
Rising, on threshold
Falling, off threshold
VVDRV = VVCIN = 0 V; VIN = 12 V
3.3
2.3
2.95
°C
3.9
V
400
mV
20.2
kΩ
Notes:
a. Typical limits are established by characterization and are not production tested.
b. Guaranteed by design.
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
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SiC762CD
Vishay Siliconix
TIMING SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
VVDRV = VVCIN = VDSBL# = 5 V,
VVIN = 12 V, TA = 25 °C
Turn Off Propagation Delay
High Sidea
td_off_HS
25 % of PWM to 90 % of GH
Rise Time High Side
tr_HS
10 % to 90 % of GH
10
Fall Time High Side
tf_HS
90 % to 10 % of GH
8
td_off_LS
75 % of PWM to 90 % of GL
Rise Time Low Side
tr_LS
10 % to 90 % of GL
Fall Time Low Side
tf_LS
90 % to 10 % of GL
5
Dead Time Rising
tdead_on
10 % of GL to 10 % of GH
27
Dead Time Falling
tdead_off
10 % of GH to 10 % of GL
19
Turn Off Propagation Delay
Low Sidea
Min.
Typ.
Max.
10
20
35
10
37
45
Unit
ns
6
Note:
a. Min. and Max. are not 100 % production tested.
TIMING DEFINITIONS
PWM
75 %
25 %
GH
90 %
90 %
GL
10 %
10 %
SW
1 2 3 4
Region
1
5 6
Definition
Turn off propagation delay LS
7 8
Symbol
td_off_LS
2
Fall time LS
tf_LS
3
Dead time rising
tdead_on
4
Rise time HS
tr_HS
5
Turn off propagation delay HS
td_off_HS
6
Fall time HS
tf_HS
7
Dead time falling
tdead_off
8
Rise time LS
Note:
GH is referenced to the high side source. GL is referenced to the low side source.
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tr_LS
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
SIC762CD BLOCK DIAGRAM
VDRV
VCIN
GH
UVLO
VIN
BOOT
DSBL#
Thermal
Warning
THDN
PHASE
AST CNTL
DCM DETECT
VSWH
Tristate
PWM
PWM
PGND
SMOD
GL
CGND
Figure 2
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tristate Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate Tristate logic (H, L and
Tristate) on the PWM output. For two state logic, the PWM
input operates as follows. When PWM is driven above
Vth_pwm_r the low side is turned off and the high side is turned
on. When PWM input is driven below Vth_pwm_f the high side
turns off and the Low side turns on. For Tristate logic, the
PWM input operates as above for driving the MOSFETs.
However, there is an third state that is entered into as the
PWM output of Tristate compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller's PWM output allows the SiC762CD to
pull the PWM input into the Tristate region (see the Tristate
Voltage Threshold Diagram below). If the PWM input stays in
this region for the Tristate Hold-Off Period, tTSHO, both high
side and low side MOSFETs are turned off. This function
allows the VR phase to be disabled without negative output
voltage swing caused by inductor ringing and saves a
Schottky diode clamp. The PWM and Tristate regions are
separated by hysteresis to prevent false triggering. The
SiC762CD incorporates PWM voltage thresholds that are
compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFET. In this state,
the standby current is minimized. If DSBL# is left
unconnected an internal pull-down resistor will pull the pin
down to CGND and shut down the IC.
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
Diode Emulation Mode (SMOD) Skip Mode
When SMOD pin is low the diode emulation mode is enabled.
This is a non-synchronous conversion mode that improves
light load efficiency by reducing switching losses. Conducted
losses that occur in synchronous buck regulators when
inductor current is negative are also reduced. Circuitry in the
gate drive IC detects when inductor current crosses zero and
automatically stops switching the low side MOSFET. See
SMOD Operation Diagram for additional details. This
function can also be used for a pre-biased output voltage. If
SMOD is left unconnected, an internal pull up resistor will pull
the pin up to VCIN (Logic High) to disable the diode emulation
function.
Thermal Shutdown Warning (THDN)
The THDN pin is an open drain signal that flags the presence
of excessive junction temperature. Connect a maximum of
20 kΩ to pull this pin up to VCIN. An internal temperature
sensor detects the junction temperature. The temperature
threshold is 150 °C. When this junction temperature is
exceeded the THDN flag is set. When the junction
temperature drops below 135 °C the device will clear the
THDN signal. The SiC762CD does not stop operation when
the flag is set. The decision to shutdown must be made by an
external thermal control function.
Voltage Input (VIN)
This is the power input to the drain of the high-side Power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (VSWH and PHASE)
The Switch node VSWH is the circuit PWM regulated output.
This is the output applied to the filter circuit to deliver the
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SiC762CD
Vishay Siliconix
regulated high output for the buck converter. The PHASE pin
is internally connected to the switch node VSWH. This pin is
to be used exclusively as the return pin for the BOOT
capacitor. A 20.2 kΩ resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
Ground connections (CGND and PGND)
PGND (power ground) should be externally connected to
CGND (control signal ground). The layout of the Printed
Circuit Board should be such that the inductance separating
the CGND and PGND should be a minimum. Transient
differences due to inductance effects between these two pins
should not exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV,VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap switch and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one leg
tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC762CD has an internal adaptive logic to avoid shoot
through and optimize dead time. The shoot through
protection ensures that both high-side and low-side
MOSFET are not turned on the same time. The adaptive
dead time control operates as follows. When PWM input
goes high the LS gate starts to go low after a few ns. When
this signal crosses through 1.7 V the logic to switch the HS
gate on is activated. When PWM goes low the HS gate goes
low. When the HS gate-to-source drive signal crosses
through 1.7 V the logic to turn on the LS gate is activated.
This feature helps to adjust dead time as gate transitions
change with respect to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the logic
circuitry can be safely activated. The SiC762CD also
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of the
device. As an added precaution, a 20.2 kΩ resistor is
connected between GH and PHASE to provide a discharge
path for the HS MOSFET.
DEVICE TRUTH TABLE
DSBL#
SMOD
PWM
GH
GL
Open
X
X
L
L
L
X
X
L
L
H (IL > 0), L (IL ≤ 0)
H
L
L
L
H
L
H
H
L
H
H
H
H
L
H
H
L
L
H
TRISTATE PWM VOLTAGE THRESHOLD DIAGRAM
PWM
Vth_pwm_r
Vth_tri_f
Vth_tri_r
Vth_pwm_f
GH
t TSHO
GL
t TSHO
Figure 3
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Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
SMOD OPERATION DIAGRAM
DSBL
SMOD
PWM
GH
IL = 0
IL > 0
GL
VSW
td(ON)
td(OFF)
Figure 4
31 VSWH
32 VSWH
33 VSWH
34 VSWH
35 VSWH
37 CGND
36 GL
39 DSBL#
38 THDN
40 PWM
PIN CONFIGURATION
30 VSWH
SMOD 1
VCIN 2
29 VSWH
AGND
P1
VDRV 3
28 PGND
27 PGND
BOOT 4
CGND 5
26 PGND
VSWH
P3
GH 6
25 PGND
24 PGND
PHASE 7
VIN
P2
VIN 8
VIN 9
23 PGND
22 PGND
21 PGND
VIN 10
20 PGND
19 PGND
18 PGND
17 PGND
15 VSWH
16 PGND
14 VIN
13 VIN
12 VIN
11 VIN
Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top View
PIN DESCRIPTION
Pin Number
Symbol
1
SMOD
Description
Disable low side gate operation. Active low.
2
VCIN
This will be the bias supply input for control IC (5 V).
3
VDRV
IC bias supply and gate drive supply voltage (5 V).
4
BOOT
High side driver bootstrap voltage pin for external bootstrap capacitor.
5, 37, PAD1
CGND
Control signal ground. It should be connected to PGND externally. All pins internally connected.
6
GH
7
PHASE
Return pin for the HS bootstrap capacitor. Connect a 0.1 µF ceramic capacitor from this pin to the boot pin (4).
8 to 14, PAD2
15, 29 to 35,
PAD3
16 to 28
VIN
Input voltage for power stage. It is the drain of the high-side MOSFET.
It is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected
to an output inductor. All pins internally connected.
Power ground.
VSWH
PGND
Gate signal output pin for high side MOSFET. Pin for monitoring.
36
GL
38
THDN
Thermal shutdown open drain output. Use a 10K pull up resistor to VCIN.
39
DSBL#
Disable pin. Active low.
40
PWM
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
Gate signal output pin for low side MOSFET. Pin for monitoring.
PWM input logic signal. Compatible with Tristate controller function.
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SiC762CD
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ELECTRICAL CHARACTERISTICS
1.0
20
18
0.8
0.6
IDRV (mA)
ICIN (mA)
16
0.4
14
12
10
0.2
8
0.0
- 40 - 25 - 10
5
6
- 40 - 25 - 10
20 35 50 65 80 95 110 125 140
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
Temperature (°C)
ICIN (mA) vs. Temperature at Frequency = 300 kHz
D = 10 %, VCIN = VDRV = 5 V
IDRV (mA) vs. Temperature at Frequency = 300 kHz
D = 10 %, VCIN = VDRV = 5 V
1.3
4.4
4.2
PWM TSH (V)
PWM TSH (V)
1.2
1.1
1.0
4.0
3.8
3.6
3.4
0.9
3.2
0.8
- 40 - 25 - 10
5
3.0
- 40 - 25 - 10
20 35 50 65 80 95 110 125 140
5
Temperature (°C)
Temperature (°C)
PWM Falling Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
PWM Rising Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
1.6
1.80
1.5
1.75
1.70
DSBL TSH (V)
1.4
DSBL TSH (V)
20 35 50 65 80 95 110 125 140
1.3
1.2
1.1
1.65
1.60
1.55
1.50
1.0
1.45
0.9
- 40 - 25 - 10
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
DSBL Falling Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
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1.40
- 40 - 25 - 10
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
DSBL Rising Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
1.6
1.80
1.5
1.75
1.70
SMOD TSH (V)
SMOD TSH (V)
1.4
1.3
1.2
1.1
1.65
1.60
1.55
1.50
1.0
1.45
0.9
- 40 - 25 - 10
5
1.40
- 40 - 25 - 10
20 35 50 65 80 95 110 125 140
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
Temperature (°C)
SMOD Falling Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
SMOD Rising Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
50
60
50
45
IDRV (mA)
ICIN (mA)
40
30
40
35
20
30
10
0
- 40 - 25 - 10
5
25
- 40 - 25 - 10
20 35 50 65 80 95 110 125 140
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
Temperature (°C)
ICIN + IDRV (mA) vs. Temperature at Frequency = 1 MHz
D = 10 %, VCIN = VDRV = 5 V
IDRV (mA) vs. Temperature at Frequency = 1 MHz
D = 10 %, VCIN = VDRV = 5 V
4.4
1.6
4.2
1.5
4.0
PWM TSH (V)
PWM TSH (V)
1.4
1.3
3.8
3.6
1.2
3.4
1.1
3.2
1.0
- 40 - 25 - 10
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
PWM Falling Tristate (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
3.0
- 40 - 25 - 10
5
20 35 50 65 80 95 110 125 140
Temperature (°C)
PWM Rising Tristate Threshold (V) vs. Temperature (°C)
VCIN = VDRV = 5 V
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SiC762CD
Vishay Siliconix
2.5
2.5
2.3
2.3
2.1
2.1
1.9
1.9
DSBL TSH (V)
DSBL TSH (V)
ELECTRICAL CHARACTERISTICS
1.7
1.5
1.3
1.7
1.5
1.3
1.1
1.1
0.9
0.9
0.7
0.7
0.5
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
0.5
4.7
5.6
4.8
4.9
5.0
VCIN (V)
2.3
2.3
2.1
2.1
1.9
1.9
SMOD TSH (V)
DSBL TSH (V)
2.5
1.7
1.5
1.3
0.9
0.7
0.7
5.2
5.6
1.3
0.9
5.1
5.5
1.5
1.1
5.0
5.4
1.7
1.1
4.9
5.3
DSBL Rising Threshold vs. VCIN
2.5
4.8
5.2
VCIN (V)
DSBL Falling Threshold vs. VCIN
0.5
4.7
5.1
5.3
5.4
5.5
0.5
4.7
5.6
4.8
4.9
5.0
VCIN (V)
5.1
5.2
5.3
5.4
5.5
5.6
VCIN (V)
SMOD Falling Threshold vs. VCIN
SMOD Rising Threshold vs. VCIN
1.15
4.4
4.2
1.10
PWM TSH (V)
PWM TSH (V)
4.0
1.05
1.00
3.8
3.6
3.4
0.95
3.2
0.90
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
VCIN (V)
PWM Falling Threshold vs. VCIN
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5.5
5.6
3.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
5.6
VCIN (V)
PWM Rising Threshold vs. VCIN
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
VDRV/VCIN: 2 V/div
VDRV/VCIN: 2 V/div
VO: 0.5 V/div
VIN: 5 V/div
VO: 0.5 V/div
t: 2 ms/div
PWM: 3 V/div
Startup with VIN ramping up
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
DSBL#:
2 V/div
PWM: 3 V/div
t: 20 ms/div
Power Off with VIN ramping down
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
VO: 0.5 V/div
VO: 0.5 V/div
VSWH: 5 V/div
DSBL#: 2 V/div
VSWH: 5 V/div
t: 20 µs/div.
t: 0.5 ms/div
Enable with VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
VDRV/VCIN: 2 V/div
Disable with VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
VDRV/VCIN: 2 V/div
VIN: 5 V/div
VIN: 5 V/div
PWM: 3 V/div
VO: 0.5 V/div
PWM: 3 V/div
VO: 0.5 V/div
t: 50 µs/div
PWM Start with VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
t: 500 µs/div
PWM Turn-off with VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
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11
SiC762CD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
VIN: 5 V/div
VIN: 5 V/div
VDRV/VCIN: 2 V/div
VDRV/VCIN: 2 V/div
t: 2 ms/div
VO: 0.5 V/div
VO: 0.5 V/div
PWM: 3 V/div
PWM: 3 V/div
t: 10 ms/div
Startup with VDRV/VCIN ramping up
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
Power Off with VDRV/VCIN ramping down
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz
GH: 10 V/div
GH: 10 V/div
GL: 5 V/div
GL: 5 V/div
VSWH: 8 V/div
VSWH: 8 V/div
IL: 4 A/div
IL: 4 A/div
t: 0.5 µs/div.
Switching Waveforms with SMOD enabled
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz, IOUT = 1.5 A
t: 0.5 µs/div.
Switching Waveforms with SMOD disabled
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz, IOUT = 4 A
PWM: 2 V/div
PWM: 2 V/div
GH: 5 V/div
GH: 5 V/div
VSWH: 5 V/div
VSWH: 5 V/div
GL: 2 V/div
t: 10 ns/div.
Switching Waveforms at PWM rising edge
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz, IOUT = 0 A
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12
GL: 2 V/div
t: 10 ns/div
Switching Waveforms at PWM falling edge
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz, IOUT = 0 A
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
PWM: 2 V/div
PWM: 2 V/div
GH: 5 V/div
GH: 5 V/div
VSWH: 5 V/div
VSWH: 5 V/div
GL: 2 V/div
GL: 2 V/div
t: 20 ns/div.
Switching Waveforms at PWM rising edge
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz, IOUT = 30 A
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
t: 10 ns/div.
Switching Waveforms at PWM falling edge
VIN = 12 V, VOUT = 1.2 V, FS = 500 kHz, IOUT = 30 A
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13
SiC762CD
Vishay Siliconix
TYPICAL SYSTEM EFFICIENCY WITH SIC762CD
92
92
VIN = 12 V, VOUT = 1.2 V
VIN = 19.5 V, VOUT = 1.2 V
90
90
300 kHz
88
400 kHz
88
400 kHz
84
500 kHz
82
Efficiency (%)
Efficiency (%)
300 kHz
86
86
500 kHz
84
82
80
80
78
78
76
76
0
3
6
9
12
15
18
21
24
27
30
0
33
3
6
9
12
15
18
21
24
27
30
33
30
33
Load Current (A)
Load Current (A)
VIN = 12 V and 19.5 V, VOUT = 1.2 V, VDRV = VCIN = 5 V; No Air Flow
IHLP5050FDERR33M01 Inductor
L = 330 nH, DER = 0.83 mΩ
Figure 6 - System Efficiency with SiC762
TYPICAL SYSTEM POWER LOSS WITH SIC762CD
12
12
VIN = 12 V, VOUT = 1.2 V
VIN = 19.5 V, VOUT = 1.2 V
10
10
500 kHz
500 kHz
6
300 kHz
4
Power Loss (W)
Power Loss (W)
400 kHz
8
8
400 kHz
6
4
300 kHz
2
2
0
0
0
3
6
9
12
15
18
21
24
27
30
33
0
3
Load Current (A)
6
9
12
15
18
21
24
27
Load Current (A)
VIN = 12 V and 19.5 V, VOUT = 1.2 V, VDRV = VCIN = 5 V; No Air Flow
IHLP5050FDERR33M01 Inductor
L = 330 nH, DER = 0.83 mΩ
Figure 7 - System Power Loss with SiC762
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14
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
SiC762CD
Vishay Siliconix
PACKAGE DIMENSIONS
K1
2x
5 6
Pin 1 dot
by marking
0.10 C A
D
A
K2
0.08 C
A
A1
Pin #1 dent
D2-1
0.41
A2
31
40
2x
30
1
21
10
E2-3
E2-1
4
E
0.10 M C A B
MLP66-40
(6 mm x 6 mm)
(Nd-1)X e
ref.
E2-2
e
0.10 C B
B
20
D2-2
D2-3
11
C
(Nd-1)X e
ref.
Top View
DIM
Bottom View
Side View
MILLIMETERS
INCHES
Min.
Nom.
Max.
Min.
Nom.
Max.
A(8)
0.70
0.75
0.80
0.027
0.029
0.031
A1
0.00
-
0.05
0.000
-
0.002
A2
b(4)
0.20 ref.
0.20
0.25
0.008 ref.
0.30
0.078
0.098
D
6.00 BSC
0.236 BSC
e
0.50 BSC
0.019 BSC
E
6.00 BSC
L
0.35
0.40
0.011
0.236 BSC
0.45
0.013
0.015
N(3)
40
40
Nd(3)
10
10
Ne(3)
10
0.017
10
D2-1
1.45
1.50
1.55
0.057
0.059
0.061
D2-2
1.45
1.50
1.55
0.057
0.059
0.061
D2-3
2.35
2.40
2.45
0.095
0.094
0.096
E2-1
4.35
4.40
4.45
0.171
0.173
0.175
E2-2
1.95
2.00
2.05
0.076
0.078
0.080
E2-3
1.95
2.00
2.05
0.076
0.078
0.080
K1
0.73 BSC
0.028 BSC
K2
0.21 BSC
0.008 BSC
Notes:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M-1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction .
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body .
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Figure 8 - PowerPAK MLP 66-40
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
www.vishay.com
15
SiC762CD
Vishay Siliconix
LAND PATTERN DIMENSIONS
2.200
2.200
0.200 0.276
0.276
0.025
40
0.100
1.700
0.025
1
40
0.100
0.100
0.320
0.310
2.600
0.100 0.100
0.100
0.600
1
0.100 0.100
0.100
4.600
0.100
Figure 9 - PowerPAK MLP 66-40
TAPE AND REEL CARRIER TAPE DIMENSIONS
+ 0.1
Ø 1.5 - 0.0
12.00
Ø 1.50 min.
2.00 ± 0.10 see note 3
0.30 ± 0.05
1.75 ± 0.1
4.00 see note 1
A
R 0.3 max.
7.5 ± 0.1
see note 3
Bo
16.0 ± 0.3
A
Ko
Ao
0.25
Section A-A
Ao = 6.30
R 0.25
Bo = 6.30
Ko = 1.10
Notes:
1. 10 sprocket hole pitch cumulative tolerance ± 0.2.
2. Camber in compliance with EIA 481.
3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
Figure 10 - PowerPAK MLP 66-40
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65727.
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16
Document Number: 65727
S10-0275-Rev. A, 08-Feb-10
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP66-40 Case Outline
2x
5 6
Pin 1 dot
by marking
K1
0.08 C
A
0.10 C A
D
A
K2
A1
D2-1
0.41
A2
31
40
2x
30
1
21
10
E2-3
E2-1
4
E
0.10 M C A B
MLP66-40
(6 mm x 6 mm)
(Nd-1)X e
ref.
E2-2
e
0.10 C B
B
20
D2-2
D2-3
11
C
(Nd-1)X e
ref.
Top View
DIM.
Bottom View
Side View
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
A (8)
0.70
0.75
0.80
0.027
0.029
0.031
A1
0.00
-
0.05
0.000
-
0.002
0.30
0.078
A2
b (4)
0.20 ref.
0.20
0.25
0.008 ref.
0.098
D
6.00 BSC
0.236 BSC
e
0.50 BSC
0.019 BSC
E
6.00 BSC
0.236 BSC
L
0.35
0.40
MAX.
0.45
0.013
0.015
N (3)
40
40
Nd (3)
10
10
Ne (3)
10
0.011
0.017
10
D2-1
1.45
1.50
1.55
0.057
0.059
0.061
D2-2
1.45
1.50
1.55
0.057
0.059
0.061
D2-3
2.35
2.40
2.45
0.095
0.094
0.096
E2-1
4.35
4.40
4.45
0.171
0.173
0.175
E2-2
1.95
2.00
2.05
0.076
0.078
0.080
E2-3
1.95
2.00
2.05
0.076
0.078
0.080
K1
0.73 BSC
0.028 BSC
K2
0.21 BSC
0.008 BSC
ECN: T14-0826-Rev. B, 12-Jan-15
DWG: 5986
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
Document Number: 64846
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Revision: 12-Jan-15
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Revision: 08-Feb-17
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Document Number: 91000
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