SIHB22N60E-GE3

SiHB22N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D D2PAK (TO-263) • • • • • • G G D S S N-Channel MOSFET APPLICATIONS • • • • Server and telecom power supplies Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) max. () at 25 °C 650 VGS = 10 V Qg max. (nC) 0.18 86 Qgs (nC) 11 Qgd (nC) 24 Configuration Low figure-of-merit (FOM) Ron x Qg Low input capacitance (Ciss) Reduced switching and conduction losses Ultra low gate charge (Qg) Avalanche energy rated (UIS) Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Single ORDERING INFORMATION D2PAK (TO-263) Package SiHB22N60E-GE3 Lead (Pb)-free and Halogen-free SiHB22N60ET1-GE3 SIHB22N60ET5-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID UNIT V 21 13 A IDM 56 1.8 W/°C Single Pulse Avalanche Energy b EAS 367 mJ Maximum Power Dissipation PD 227 W TJ, Tstg -55 to +150 °C Linear Derating Factor Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dt d Soldering Recommendations (Peak temperature) c For 10 s dV/dt 70 11 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 5.1 A. c. 1.6 mm from case. d. ISD  ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S16-1704-Rev. J, 29-Aug-16 Document Number: 91472 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB22N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 0.55 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current VDS VGS = 0 V, ID = 250 μA 600 - - V VDS/TJ Reference to 25 °C, ID = 250 μA - 0.71 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 10 IGSS IDSS μA - 0.15 0.18  gfs VDS = 8 V, ID = 5 A - 6.4 - S Input Capacitance Ciss VGS = 0 V, VDS = 100 V, f = 1 MHz - 1920 - - 90 - - 6 - - 73 - - 263 - - 57 86 - 11 - - 24 - Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 10 V ID = 11 A Dynamic Output Capacitance Coss Reverse Transfer Capacitance Crss Effective Output Capacitance, Energy Related a Co(er) Effective Output Capacitance, Time Related b Co(tr) pF VDS = 0 V to 480 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 11 A, VDS = 480 V nC - 18 36 VDD = 380 V, ID = 11 A, VGS = 10 V, Rg = 4.7  - 27 54 - 66 99 - 35 70 f = 1 MHz, open drain 0.3 0.77 1.2 - - 21 - - 56 - - 1.2 V - 344 - ns - 5.3 - μC - 28 - A ns  Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the  integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 11 A, VGS = 0 V TJ = 25 °C, IF = IS = 11 A, dI/dt = 100 A/μs, VR = 25 V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S16-1704-Rev. J, 29-Aug-16 Document Number: 91472 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB22N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 60 TJ = 25 °C ID = 11 A RDS(on), Drain-to-Source On Resistance (Normalized) 8V 40 7V 20 6V 5V 0 0 5 10 15 20 25 2.5 2 1.5 VGS = 10 V 1 0.5 0 - 60 - 40 - 20 0 30 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 30 20 10 000 TJ = 150 °C Ciss Capacitance (pF) ID, Drain-to-Source Current (A) 40 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) VDS, Drain-to-Source Voltage (V) 7V 6V 5V 10 1000 Coss 100 Crss 10 0 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 1 0 10 5 20 15 25 30 0 VDS, Drain-to-Source Voltage (V) 100 200 300 500 400 600 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 14 5000 50 12 10 40 Coss (pF) ID, Drain-to-Source Current (A) 60 30 TJ = 150 °C 8 Coss Eoss 500 6 Eoss (μJ) ID, Drain-to-Source Current (A) 80 20 4 TJ = 25 °C 10 2 0 50 0 5 10 15 20 25 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S16-1704-Rev. J, 29-Aug-16 0 0 100 200 300 VDS 400 500 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 91472 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB22N60E www.vishay.com Vishay Siliconix 25 VDS = 480 V VDS = 300 V VDS = 120 V 20 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 4 0 20 15 10 5 0 0 60 30 120 90 25 Qg, Total Gate Charge (nC) 50 75 100 125 150 TJ, Case Temperature (°C) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature 725 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 1000 100 10 TJ = 150 °C 1 TJ = 25 °C 0.1 0.01 700 675 650 625 600 575 0.001 VGS = 0 V 550 0.0001 0.2 0 0.4 0.6 0.8 1.0 - 60 - 40 - 20 0 1.2 1.4 VSD, Source-Drain Voltage (V) Fig. 8 - Typical Source-Drain Diode Forward Voltage 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Temperature vs. Drain-to-Source Voltage ID, Drain Current (A) 1000 Operation in this Area Limited by RDS(on) IDM = Limited 100 10 100 μs Limited by RDS(on)* 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 10 ms 0.1 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S16-1704-Rev. J, 29-Aug-16 Document Number: 91472 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB22N60E www.vishay.com Vishay Siliconix Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS 10 % VGS QGD VG td(on) td(off) tf tr Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L Vary tp to obtain required IAS VDS 50 kΩ D.U.T RG 12 V + - IAS 0.2 µF 0.3 µF V DD + D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S16-1704-Rev. J, 29-Aug-16 Document Number: 91472 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB22N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel           Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91472. S16-1704-Rev. J, 29-Aug-16 Document Number: 91472 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000