SIHS20N50C-E3

SiHS20N50C www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • Low figure-of-merit Ron x Qg SUPER-247 • 100 % avalanche tested • High peak current capability G • dv/dt ruggedness S • Improved trr/Qrr D G • Improved gate charge S • High power dissipations capability N-Channel MOSFET • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912     PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) () 560 VGS = 10 V Qg max. (nC) 0.270 76 Qgs (nC) 21 Qgd (nC) 34 Configuration Single ORDERING INFORMATION Package Super-247 Lead (Pb)-free SiHS20N50C-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 500 Gate-source voltage VGS ± 30 Continuous drain current (TJ = 150 °C) a VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current b UNIT V 20 ID 11 A IDM 80 1.8 W/°C Single pulse avalanche energy c EAS 361 mJ Maximum power dissipation PD 250 W dv/dt 5 V/ns TJ, Tstg -55 to +150 Linear derating factor Reverse diode dv/dt d Operating junction and storage temperature range Soldering recommendations (peak temperature) d For 10 s 300 °C Notes a. Limited by maximum junction temperature b. Repetitive rating; pulse width limited by maximum junction temperature c. VDD = 50 V, starting TJ = 25 °C, L = 2.5 mH, Rg = 25 , IAS = 17 A d. ISD  18 A, di/dt  380 A/μs, VDD  VDS, TJ  150 °C e. 1.6 mm from case THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 40 Maximum junction-to-case (drain) RthJC - 0.5 S17-1726-Rev. C, 20-Nov-17 UNIT °C/W Document Number: 91424 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS20N50C www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage (N) VDS VGS = 0 V, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.7 - V/°C VGS(th) VDS = VGS, ID = 250 μA 3.0 - 5.0 V Gate-source leakage IGSS VGS = ± 30 V - - ± 100 nA Zero gate voltage drain current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 μA - 0.225 0.270  gfs VDS = 50 V, ID = 10 A - 6.4 - S Input capacitance Ciss 2451 2942 Coss - 300 360 Reverse transfer capacitance Crss VGS = 0 V, VDS = 25 V, f = 1 MHz - Output capacitance - 26 32 Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 10 A Dynamic Total gate charge Qg Gate-source charge Qgs Gate-drain charge Turn-on delay time Rise time Turn-off delay time pF - 65 76 - 21 - Qgd - 29 - td(on) - 80 - VDD = 250 V, ID = 18 A, Rg = 9.1  - 27 - - 32 - - 44 - f = 1 MHz, open drain - 1.1 - - - 20 S - - 80 TJ = 25 °C, IS = 18 A, VGS = 0 V - - 1.5 V - 503 - ns - 6.7 - μC - 30 - A tr td(off) Fall time tf Gate input resistance Rg VGS = 10 V ID = 18 A, VDS = 400 V nC ns  Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM S17-1726-Rev. C, 20-Nov-17 MOSFET symbol showing the  integral reverse p - n junction diode D A G TJ = 25 °C, IF = IS, di/dt = 100 A/μs, VR = 35 V Document Number: 91424 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS20N50C www.vishay.com Vishay Siliconix 70 VGS Top 15 V 14 V 13 V 12 V 11 V 10 V 9.0 V 8.0 V 7.0 V 6.0 V Bottom 5.0 V ID, Drain Current (A) 60 50 40 30 TJ = 25 °C 20 7.0 V 10 0 0 6 12 18 24 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 30 3 ID = 17 A 2.5 2 1.5 VGS = 10 V 1 0.5 0 - 60 - 40 - 20 Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature 40 105 VGS 15 V 14 V 13 V 12 V 30 11 V 10 V 9.0 V 8.0 V 7.0 V 20 6.0 V Bottom 5.0 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Capacitance (pF) TJ = 150 °C Top ID, Drain Current (A) 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) VDS, Drain-to-Source Voltage (V) 7.0 V 10 0 104 Ciss 103 102 Coss Crss 10 0 6 12 18 24 30 1 VDS, Drain-to-Source Voltage (V) 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 100 VGS, Gate-to-Source Voltage (V) 20 TJ = 150 °C ID, Drain Current (A) 0 10 TJ = 25 °C 1 0.1 ID = 17 A VDS = 400 V VDS = 250 V VDS = 100 V 16 12 8 4 0 0.01 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S17-1726-Rev. C, 20-Nov-17 10 0 30 60 90 120 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91424 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS20N50C www.vishay.com Vishay Siliconix 1000 Operation in this area limited by RDS(on) TJ = 150 °C 10 ID, Drain Current (A) ISD, Reverse Drain Current (A) 100 TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.5 0.8 1.1 100 10 100 µs 1 ms 1 TC = 25 °C TJ = 150 °C Single Pulse 10 ms 0.1 100 10 1.4 1000 10 000 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area ID, Drain Current (A) 20 15 10 5 0 25 50 75 100 125 150 TC, Case Temperature (°C) Fig. 9 - Maximum Drain Current vs. Case Temperature Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 0.1 1 Pulse Time (s) Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case (Super-247) S17-1726-Rev. C, 20-Nov-17 Document Number: 91424 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS20N50C www.vishay.com Vishay Siliconix RD VDS QG 10 V VGS D.U.T. QGS RG QGD + - VDD VG 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 15 - Basic Gate Charge Waveform Fig. 11 - Switching Time Test Circuit Current regulator Same type as D.U.T. VDS 90 % 50 kΩ 12 V 0.2 µF 0.3 µF + D.U.T. 10 % VGS td(on) VDS VGS td(off) tf tr - 3 mA Fig. 12 - Switching Time Waveforms IG ID Current sampling resistors L Vary tp to obtain required IAS Fig. 16 - Gate Charge Test Circuit VDS D.U.T RG + - IAS V DD 10 V 0.01 Ω tp Fig. 13 - Unclamped Inductive Test Circuit VDS tp VDD VDS IAS Fig. 14 - Unclamped Inductive Waveforms S17-1726-Rev. C, 20-Nov-17 Document Number: 91424 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHS20N50C www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 17 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91424. S17-1726-Rev. C, 20-Nov-17 Document Number: 91424 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-274AA (High Voltage) VERSION 1: FACILITY CODE = Y B A E E4 A D2 E1 A1 R D1 D L1 L Detail “A” C b e A2 0.10 (0.25) M B A M 10° b4 b2 Lead Tip 5° Detail “A” Scale: 2:1 MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. A 4.70 5.30 0.185 0.209 D1 15.50 16.10 0.610 0.634 A1 1.50 2.50 0.059 0.098 D2 0.70 1.30 0.028 0.051 A2 2.25 2.65 0.089 0.104 E 15.10 16.10 0.594 0.634 13.30 13.90 0.524 0.547 b 1.30 1.60 0.051 0.063 E1 b2 1.80 2.20 0.071 0.087 e 5.45 BSC MAX. 0.215 BSC b4 3.00 3.25 0.118 0.128 L 13.70 14.70 0.539 0.579 c (1) 0.38 0.89 0.015 0.035 L1 1.00 1.60 0.039 0.063 D 19.80 20.80 0.780 0.819 R 2.00 3.00 0.079 0.118 Notes • Dimensioning and tolerancing per ASME Y14.5M-1994 • Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outer extremes of the plastic body • Outline conforms to JEDEC® outline to TO-274AA (1) Dimension measured at tip of lead Revision: 19-Oct-2020 Document Number: 91365 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = N A E A E3 B D D1 D2 E2 Q A2 L1 F F H H C G L G A1 e b 3x 0.25 M B A M b1 C b3 E4 E1 b’, b2, b4 C C’ Base metal b, b1, b3 Plating SECTION "F-F", "G-G" AND "H-H" SCALE: NONE MILLIMETERS MILLIMETERS DIM. MIN. MAX. DIM. MIN. MAX. A 4.83 5.21 D1 16.25 17.65 A1 2.29 2.54 D2 0.50 0.80 A2 1.91 2.16 E 15.75 16.13 b’ 1.07 1.28 E1 13.10 14.15 b 1.07 1.33 E2 3.68 5.10 b1 1.91 2.41 E3 1.00 1.90 b2 1.91 2.16 E4 12.38 13.43 b3 2.87 3.38 e b4 2.87 3.13 N c’ 0.55 0.65 L 19.81 c 0.55 0.68 L1 3.70 4.00 D 20.80 21.10 Q 5.49 6.00 5.44 BSC 3 20.32 ECN: E20-0538-Rev. C, 19-Oct-2020 DWG: 5975 Notes • Dimensioning and tolerancing per ASME Y14.5M-1994 • Outline conforms to JEDEC® outline to TO-274AD • Dimensions are measured in mm, angles are in degree • Metal surfaces are tin plated, except area of cut Revision: 19-Oct-2020 Document Number: 91365 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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