TFDU8108
Vishay Semiconductors
Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s)
IrDA® Serial Interface Compatible
2.7 V to 5.5 V Supply Voltage Range
Description
The TFDU8108 transceiver is part of a family of low
power consumption infrared transceiver modules. It is
compliant to the IrDA physical layer standard for VFIR
infrared data communication, supporting IrDA speeds
up to 16 Mbit/s (VFIR) and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power control IC.
At a minimum, a Vcc bypass capacitor is the only
external component required implementing a complete solution. For limiting the transceiver’s internal
power dissipation one additional resistor might be
necessary. The transceiver can be operated with
logic I/O voltages as low as 1.8 V.
Features
• Compliant to the latest IrDA physical
layer standard (up to 16 Mbit/s), HP-SIR®,
Sharp ASK® and TV Remote Control
e3
• Compliant to the IrDA "Serial Interface
Specification for Transceivers"
• Surface mount Soldering to side and top view orientation
• Surface Mount package 9.7 x 4.7 x 4.0 mm3
for side view and top view applications
• Operating supply voltage from 2.7 V to 5.5 V
• Compliant to all logic levels between 1.8 V and 5 V
• TV Remote Control support
• Low Power consumption (2 mA idle supply current)
• Power Shutdown mode (1 µA shutdown current)
20110
• Tri-State-receiver output, weak pull-up when in
output is disabled
• Built - In EMI Protection - No external shielding
necessary
• Pin to Pin compatible to legacy Vishay SIR and
FIR infrared transceivers
• Eye safety class 1 (IEC60825-1, ed. 2001), limited
LED on-time, LED current is controlled, no single
fault to be considered
• Lead (Pb)-free device
• Qualified for lead (Pb)-free and Sn/Pb processing
(MSL4)
• Device in accordance with RoHS 2002/95/EC and
WEEE 2002/96/EC
• Split power supply, can be driven by a separate
power supply not loading the regulated supply.
U.S. Pat. No. 6,157,476
Applications
• Notebook Computers, Desktop PCs, Palmtop
computers (Win CE, Palm PC), PDAs
• Digital still and video cameras
• Printers, fax machines, photocopiers,
screen projectors
• MP3 players
• Telecommunication products (Cellular Phones,
Pagers)
• Internet TV boxes, Video Conferencing Systems
• External infrared adapters (dongles)
• Medical and industrial data collection devices
Package
TFDU8108
Baby Face
(Universal)
weight 200 mg
19497
www.vishay.com
360
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Ordering Information
Part Number
Description
Qty / Reel
TFDU8108-TR3
Oriented in carrier tape for side view surface mounting
1000 pcs
TFDU8108-TT3
Oriented in carrier tape for top view surface mounting
1000 pcs
TFDU8108
In tube
50 pcs
Functional Block Diagram
Vcc1
ASIC
VCC1: Analog supply voltage
Vlogic: Digital supply voltage, I/O reference voltage
VCC2: Independent supply voltage for the LED driver
Vlogic
Voltage
Regulator
RXD
+
+
+
Driver
V
Serial Interface according the IrDA standard "Serial
Interface for Transceiver Control"
SCLK: Clock line as timing reference*)
TXD: TX/SWDAT - line*)
RXD: RX/SRDAT - line*)
Vcc2
Logic
IRKAT
AGC
SCLK
Serial Interface
TXD
GND
*) see Appendix A for definitions
GND
19493
Figure 1. Functional Block Diagram
Definitions:
In the Vishay transceiver data sheets the following nomenclature is
• VFIR: 16 Mbit/s
used for defining the IrDA operating modes:
MIR and FIR were implement with IrPhy 1.1, followed by IrPhy 1.2,
• SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the ba-
adding the SIR Low Power Standard. IrPhy 1.3 extended the Low
sic serial infrared standard with the physical layer
Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.
A new version of the standard in any case obsoletes the former ver-
version IrPhy 1.0
• MIR: 576 kbit/s to 1152 kbit/s
sion.
• FIR: 4 Mbit/s
Pin Description
Pin Number
Function
Description
1
IRED Anode
IRED anode to be externally connected to VCC2 This pin is allowed
to be supplied from an uncontrolled power supply seperated from
the controlled VCC1 - supply.
2
IRED Cathode
IRED Cathode, internally connected to driver transistor
3
TXD
4
RXD
5
SCLK
Serial Clock, dynamically loaded
6
VCC
Supply Voltage
7
Vlogic
Supply voltage for digital part, 1.8 V to 5.5 V, defines logic swing for
TXD, SCLK, and RXD
8
GND
Ground
Document Number 82558
Rev. 1.8, 16-Mar-07
I/O
Active
Transmit Data Input, dynamically loaded
I
HIGH
Received Data Output, Tri-State CMOS driver output capable of
driving a standard CMOS or TTL load. No external pull-up or pulldown resistor is required. Pin is current limited for protection against
programming errors. The output is loaded with a weak 500 kΩ pullup, when in SD mode. The RXD echoes the optical TXD signal
duration transmission.
O
LOW
I
HIGH
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361
TFDU8108
Vishay Semiconductors
BabyFace (Universal)
"U" Option BabyFace
(Universal)
IRED
1
Detector
2 3 4 5 6
7 8
17087
Figure 2. Pinning
Absolute Maximum Ratings
Reference point Ground (pin 8) unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Symbol
Min
Max
Unit
Supply voltage range,
transceiver
Parameter
0 V < VCC2 < 6 V
Test Conditions
VCC1
- 0.5
6
V
Supply voltage range,
transmitter
0 V < VCC1 < 6 V
VCC2
- 0.5
6
V
Supply voltage range,
transceiver logic
0 V < VCC1 < 6 V
Vlogic
- 0.5
6
V
VIREDA
- 0.5
6
V
VTXD
- 0.5
Vlogic + 0.5
V
VRXD
- 0.5
Vlogic + 0.5
V
10
mA
IRED anode voltage
Transmitter data input voltage
Receiver data output voltage
Input currents
Typ.
For all pins, except IRED anode
pin
Output sinking current
Power dissipation
See derating curve, figure 7
Junction temperature
Storage temperature range
Average output current
< 90 µs, ton < 20 %
Virtual source size
Method: (1 - 1/e) encircled
energy
125
°C
+ 85
°C
Tstg
- 40
+ 100
°C
260
°C
IIRED (DC)
130
mA
IIRED (RP)
600
mA
d
2.5
2.8
IrDA® specified maximum limit
Due to the internal limitation measures the device is a "class1" device. It will not exceed the
362
mm
Internal
limitation to
class 1
500
Maximum Intensity for Class 1 Operation of IEC825-1 or
EN60825-1, edition Jan. 2001
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mA
mW
0
See recommended solder
profile (see figures 4 to 6)
Repetitive pulse output current
25
350
Tamb
TJ
Ambient temperature range
(operating)
Soldering temperature
PD
IrDA®
mW/sr
intensity limit of 500 mW/sr.
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Electrical Characteristics
Transceiver
Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Symbol
Min
Max
Unit
Supply voltage VCC1
Parameter
Test Conditions
VCC1
2.7
Typ
5.5
V
Supply voltage Vlogic
Vlogic
1.8
5.5
V
Dynamic supply current
Receive mode only. In transmit mode, add the averaged programmed current of IRED current as ICC2
Dynamic supply current
Active, SIR, Ee = 0 klx (idle)
T = - 25 °C to 85 °C
ICC1
Dynamic supply current
Active, VFIR, Ee = 0 klx, (idle)
T = - 25 °C to 85 °C
Dynamic supply current
Dynamic supply current
0.8
2.5
mA
ICC1
10
mA
active, no load Ee = 0 klx, (idle)
T = - 25 °C to 85 °C
Ilogic
5
µA
Ee = 1 klx*) receive mode,
Ilogic
1
mA
2
2
µA
µA
5
µA
+ 85
°C
0.4
V
EEo = 100 mW/m2
(9.6 kbit/s to 4.0 Mbit/s),
RL = 10 kΩ to Vlogic = 5 V,
CL = 15 pF
T = - 25 °C to 85 °C
Standby supply current
Standby supply current
Inactive, set to shutdown mode
T = 25 °C, Ee = 0 klx
T = 25 °C, Ee = 1 klx*) **)
ISD
Shutdown mode, **)
T = 85 °C
ISD
Operating temperature range
TA
0
Output voltage low
Cload = 15 pF,
Vlogic = 3 V, IOLO < + 500 µA
VOLO
Output voltage high
Cload = 15 pF,
Vlogic = 5 V, IOHI < - 250 µA
VOHI
0.8 x Vlogic
Input voltage high (TXD, SCLK)
VIL
- 0.5
Input voltage high (TXD, SCLK)
VIH
Vlogic - 0.3
logic decision level
(TXD, SCLK) ***)
VIL
Input leakage current
(TXD, SCLK)
IL
Input capacitance
CI
V
0.5
6
0.5 x Vlogic
- 10
V
V
+ 10
µA
5
pF
*) Standard illuminant A.
**) In shutdown condition the device is not ambient light sensitive.
***) The device will work with less tight levels than specified min/max values of the logic input voltage. It is recommended to use the specified min/max values to minimize operating/standby supply currents.
Document Number 82558
Rev. 1.8, 16-Mar-07
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363
TFDU8108
Vishay Semiconductors
Optoelectronic Characteristics
Receiver
Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Typ.
Max
Unit
Minimum detection threshold
irradiance
Parameter
9.6 kbit/s to 115.2 kbit/s, SIR
λ = 850 nm to 900 nm
Test Conditions
Ee
25
40
mW/m2
Minimum detection threshold
irradiance
1.152 Mbit/s, MIR
λ = 850 nm to 900 nm
Ee
65
90
mW/m2
Minimum detection threshold
irradiance
4 Mbit/s, FIR
λ = 850 nm to 900 nm
Ee
85
90
mW/m2
Minimum detection threshold
irradiance
16 Mbit/s, VFIR
λ = 850 nm to 900 nm
Ee
160
200
mW/m2
Maximum detection threshold
irradiance
λ = 850 nm to 900 nm
Ee
5
Ee
4
Logic LOW receiver input
irradiance
Symbol
Min
10
kW/m2
mW/m2
RXD pulse width of output
signal, 50 % SIR mode
Input pulse length 20 μs,
9.6 kbit/s
tPW
1.3
2.6
µs
RXD pulse width of output
signal, 50 % SIR mode
Input pulse length 1.41 μs,
115.2 kbit/s
tPW
1.3
2.6
µs
RXD pulse width of output
signal, 50 % MIR mode
Input pulse length 217 ns,
1.152 Mbit/s
tPW
200
260
ns
RXD pulse width of output
signal, 50 % FIR mode
Input pulse length 125 ns,
4 Mbit/s
tPW
105
145
ns
RXD pulse width of output
signal, 50 % FIR mode
Input pulse length 250 ns,
4 Mbit/s
tPW
225
285
ns
RXD pulse width of output
signal, 50 %
Input pulse length 16 Mbit/s,
VFIR
39.5 ns < Pwopt < 43 ns
tPW
32
42
52
ns
125
RXD rise time of output signal
20 % to 80%, CL = 15 pF
tr (RXD)
2
5
15
ns
RXD fall time of output signal
20 % to 80%, CL = 15 pF
tr (RXD)
2
5
15
ns
RXD fall time of output signal
90 % to 10%, CL = 15 pF
tr (RXD)
5
30
ns
350
ns
Input irradiance = 100 mW/m2,
1.152 Mbit/s
40
ns
RXD Jitter, leading edge, FIR
mode
Input irradiance = 100 mW/m2,
4 Mbit/s
20
ns
RXD Jitter, leading edge
Input irradiance = 200 mW/m2,
16 Mbit/s, VFIR mode
7
ns
1
µs
RXD Jitter, leading edge, SIR
mode
Input irradiance = 40
115.2 kbit/s
RXD Jitter, leading edge, MIR
mode
RXD output pulse delay
mW/m2,
5
tRXDdel
Latency
tLAT
55
100
µs
Receiver Startup Time
tPOR
100
500
µs
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364
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Transmitter
Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted.
Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Conditions
Symbol
IRED operating current
internally controlled*)
Parameter
VCC1 = 3.3 V, the maximum
current is limited internally. An
external resistor can be used to
reduce the power dissipation at
higher operating voltages, see
derating curve.
ID
8
16
32
64
128
256
512
Max. output radiant intensity
VCC = 3.3 V, α = 0°,15°
TXD = High, R1 = 0 Ω
programmed to max. power
level
Ie
0.3
Output radiant intensity
VCC = 5.0 V, α = 0°, 15°
TXD = Low, programmed to
shutdown mode
Ie
TXD pulse width of output
signal, 50 %
Input pulse length 1.63 µs,
115.2 kbit/s
tPW
TXD pulse width of output
signal, 50 %
Input pulse width 0.1 µs < tTXD
< 60 μs
tPW
Input pulse width tTXD ≥ 60 µs
Min
Typ.
Max
Unit
mA
600
mW/sr/mA
0.04
mW/sr
2.20
µs
20
60
µs
1.45
tTXD
TXD pulse width of output
signal, 50 %
Input pulse length 250 ns,
(FIR, double pulse)
tPW
240
260
ns
TXD pulse width of output
signal, 50 %
Input pulse length 217.0 (MIR)
tPW
115
260
ns
TXD pulse width of output
signal, 50 %
FIR mode
Input pulse length 125 ns (FIR)
tPW
115
135
ns
TXD pulse width of output
signal, 50 %
Input pulse length 41.7 ns
tPW
38.3
45.0
ns
Output radiant intensity, angle of
half intensity
α
Peak - emission wavelength
λp
Spectral bandwidth
Optical rise time, fall time
Optical overshoot
125
± 24
870
°
900
40
tropt, tfopt
nm
nm
19
ns
15
%
*) Programmable using the"serial interface“ programming sequence, see Appendix A for implementation guidance and Appendix B for intensity values and range.
Document Number 82558
Rev. 1.8, 16-Mar-07
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365
TFDU8108
Vishay Semiconductors
Recommended Circuit Diagram
Operated with a low impedance power supply the
TFDU8108 series devices need no external components. However, depending on the entire system
design and board layout, additional components may
be required (see figure 3).
VCC2
Recommended Application Circuit
Components
Component
Recommended Value
C1
4.7 µF, 16 V
C2
0.1 µF, Ceramic
R1
Recommended for VCC2 ≥ 4 V
Depending on current limit
R2
< 10 Ω, 0.125 W
R1
VCC1
IRED
Cathode
R2
Rxd
C1
GND
C2
I/O and Software
IRED
Anode
Rxd
Txd
Vcc
SCLK
GND
Vlogic
For operating the device from a Controller I/O a driver
software must be implemented.
Mode Switching and Programming
Vlogic
SCLK
Txd
17089
The generic IrDA "Serial Interface programming"
needs no special settings for the device. Only the current control table must be taken into account. For the
description see the Appendix A, B and C and the IrDA
document "Serial Interface specification for transceivers"
Figure 3. Recommended Application Circuit
All external components (R, C) are optional
Vishay transceivers integrate a sensitive receiver and
a built-in power driver. The combination of both needs
a careful circuit board layout. The use of thin, long,
resistive and inductive wiring must be avoided. The
inputs (TXD, SCLK) and the output RXD should be
directly DC-coupled to the I/O circuit.
R1 is used for reducing the power dissipation when
operating the device at a supply voltage of VCC2 > 4 V.
For increasing the max. output power of the IRED, the
value of the resistor should be reduced. It should be
dimensioned to keep the IRED anode voltage below
4 V for using the full temperature range. For device
and eye protection the pulse duration and current are
internally limited.
R2, C1 and C2 are optional and dependent on the
quality of the supply voltage VCC1 and injected noise.
An unstable power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver.
The placement of these parts is critical. It is strongly
recommended to position C2 as near as possible to
the transceiver power supply pins. An electrolytic
capacitor should be used for C1 while a ceramic
capacitor is used for C2.
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366
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Recommended Solder Profiles
The data for the drying procedure is given on labels
on the packing and also in the application note
"Taping, Labeling, Storage and Packing"
(http://www.vishay.com/docs/82601/82601.pdf).
260
240
220
200
180
160
140
120
100
80
60
40
20
0
10 s max. at 230 °C
240 °C max.
2...4 °C/s
160 °C max.
275
90 s max.
225
50
Tpeak = 260 °C
T ≥ 217 °C for 70 s max
200
2...4 °C/s
0
T ≥ 255 °C for 10 s....30 s
250
120 s...180 s
100
19535
150
200
250
300
350
Time/s
Temperature/°C
Temperature (°C)
Solder Profile for Sn/Pb Soldering
175
150
30 s max.
125
100
90 s...120 s
70 s max.
2 °C...4 °C/s
75
Figure 4. Recommended Solder Profile for Sn/Pb soldering
2 °C...3 °C/s
50
25
0
0
Storage
The storage and drying processes for all VISHAY
transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4.
Document Number 82558
Rev. 1.8, 16-Mar-07
100
150
200
Time/s
250
300
350
Figure 5. Solder Profile, RSS Recommendation
280
Tpeak = 260 °C max
260
240
220
200
180
< 4 °C/s
160
1.3 °C/s
140
120
Time above 217 °C t ≤ 70 s
Time above 250 °C t ≤ 40 s
Peak temperature Tpeak = 260 °C
100
80
< 2 °C/s
60
40
20
0
0
50
100
150
200
250
300
Time/s
Figure 6. RTS Recommendation
Current Derating Diagram
Wave Soldering
For TFDUxxxx and TFBSxxxx transceiver devices
wave soldering is not recommended.
600
Peak Operating Current (mA)
Manual Soldering
Manual soldering is the standard method for lab use.
However, for a production process it cannot be recommended because the risk of damage is highly
dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned
application note, describing manual soldering and
desoldering.
50
19532
Temperature/°C
Lead (Pb)-Free, Recommended Solder Profile
The TFDU8108 is a lead (Pb)-free transceiver and
qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu,
there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow
ovens heated by infrared radiation. With widespread
use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 5 and 6 are VISHAY's recommended profiles for
use with the TFDU8108 transceivers. For more
details please refer to the application note
“SMD Assembly Instructions”
(http://www.vishay.com/docs/82602/82602.pdf).
A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could
damage an optical part because the thermal conductivity is less than compared to a standard IC.
500
400
300
200
Current derating as a function of
the maximum forward current of
IRED. Maximum duty cycle: 25 %.
100
0
- 40 - 20
14875
0
20 40 60 80 100 120 140
Temperature (°C)
Figure 7. Current Derating Diagram
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367
TFDU8108
Vishay Semiconductors
TFDU8108 - BabyFace (Universal) Package
(Mechanical Dimensions)
18473-1
Figure 8. Mechanical drawing, dimensions in mm, tolerance ± 0.2 mm if not otherwise shown
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368
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Recommended SMD Pad Layout
7x1=7
0.6 ( 0.7)
2.5 ( 2.0)
1
8
1
16524-1
Figure 9. Mechanical drawing, dimensions in mm, tolerance ± 0.2 mm if not otherwise shown
Reel Dimensions
Drawing-No.: 9.800-5090.01-4
Issue: 1; 29.11.05
14017
Figure 10. Reel dimensions, dimensions in mm, tolerance ± 0.2 mm
Tape Width
A max.
N
mm
mm
mm
mm
mm
mm
mm
24
330
60
24.4
30.4
23.9
27.4
Document Number 82558
Rev. 1.8, 16-Mar-07
W1 min.
W2 max.
W3 min.
W3 max.
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TFDU8108
Vishay Semiconductors
Tape Dimensions
19822
Drawing-No.: 9.700-5251.01-4
Issue: 3; 02.09.05
Figure 11. Tape drawing,TFDU8108 for top view mounting, tolerance ± 0.1 mm
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370
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
19875
Drawing-No.: 9.700-5297.01-4
Issue: 1; 04.08.05
Figure 12. Tape drawing, TFDU8108 for side view mounting
after mounting, tolerance ± 0.1 mm
Document Number 82558
Rev. 1.8, 16-Mar-07
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371
TFDU8108
Vishay Semiconductors
Tube drawing
19496
Figure 13. Tube drawing
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372
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Appendix A
Serial Interface Implementation
Basics of the IrDA Definitions
The data lines are multiplexed with the transmitter
and receiver signals and separate clocks are used
since the transceivers respond to the same address.
When no infrared communication is in progress and
the serial bus is idle, the IRTX line is kept low and
IRRX is kept high.
OFE A
IRTX/SWDAT
TX/SWDAT
IRRX/SRDAT
Infrared
Controller
RX/SRDAT
SCLK1
Optical
Transceiver
SCLK
SCLK2
VCC
OFE B
TX/SWDAT
RX/SRDAT
Optical
Transceiver
SCLK
17092
Figure 14. Interface to Two Infrared Transceivers
Connector
Infrared
Controller
IRTX+/SWDAT+
IRTX-/SWDATIRRX+/SRDAT+
IRRX-/SRDATSCLK+
SCLK-
Shielded Cable
VCC
GND
VCC
LVDS
Transceiver
GND
TX/SWDAT
RX/SRDAT
SCLK
Optical
Transceiver
A_SL
GND
17093
Figure 15. Infrared Dongle with Differential Signaling
Functional description
The serial interface is designed to interconnect two or
more devices. One of the devices is always in control
of the serial interface and is responsible for starting
every transaction. This device functions as the bus
master and is always the infrared controller. The infrared transceivers act as bus slaves and only respond
to transactions initiated by the master. A bus transaction is made up of one or two phases. The first phase
is the Command Phase and is present in every transaction. The second phase is the Response Phase
and is present only in those transactions in which data
must be returned from the slave. If the operation
involves a data transfer from the slave, there will be a
Response Phase following the Command Phase in
which the slave will output the data.
The Response Phase, if present, must begin 4 clock
cycles after the last bit of the Command Phase, as
shown in figures 16 and 17, otherwise it is assumed
that there will be no response phase and the master
can terminate the transaction.
Document Number 82558
Rev. 1.8, 16-Mar-07
The SCLK line is always driven by the master and is
used to clock the data being written to or read from
the slave.
This line is driven by a totem-pole output buffer. The
SCLK line is always stopped when the serial interface
is idle to minimize power consumption and to avoid
any interference with the analog circuitry inside the
slave. There are no gaps between the bytes in either
the Command or Response Phase. Data is always
transferred in Little Endian order (least significant bit
first). Input data is sampled on the rising edge of
SCLK. IRTX/SWDAT output data from the controller
is clocked by SCLK falling edge. IRRX/SRDAT output
data from the slave is clocked by SCLK rising edge.
Each byte of data in both Command and Response
Phases is preceded by one start bit. The data to be
written to the slave is carried on the IRTX/SWDAT
line. When the control interface is idle, this line carries
the infrared data signal used to drive the transmitter
LED. When the first low-to-high transition on SCLK is
detected at the beginning of the command sequence,
the slave will disable the transmitter LED. When the
first low-to-high transition on SCLK is detected at the
beginning of the command sequence, the slave will
disable the transmitter LED. The infrared controller
then outputs the command string on the IRTX/
SWDAT line. On the last SCLK cycle of the command
sequence the slave re-enables the transmitter LED
and normal infrared transmission can resume. No
transition on SCLK must occur until the next command sequence otherwise the slave will disable the
transmitter LED again. Read data is carried on the
IRRX/SRDAT line. The slave disables the internal signal from the receiver photo diode during the response
phase of a read transaction. The addressed slave will
output the read data on the IRRX/SRDAT line regardless of the setting of the Receiver Output Enable bit in
the main control register (main-ctrl-0). Non addressed
slaves will tri-state the IRRX/SRDAT line. When the
transceiver is powered up, the IRTX/SWDAT line
should be kept low and SCLK should be cycled at
least 30 times by the infrared controller before the first
command is issued on the IRTX/SWDAT line, see figure 18. This guarantees that the transceiver interface
circuitry will properly initialize and be ready to receive
commands from the controller. In case of a multiple
transceiver configuration, only one transceiver should
have the receiver output enabled.
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A series resistor (approx. 200 Ω) should be placed on
the receiver output from each transceiver to prevent
large currents in case a conflict occurs due to a programming error.
Note: Generally the abbreviations IRTX/IRRX and TXD/RXD are
used for the data transmission lines for the optical communication.
IRTX/IRRX is mostly used at the controller, TXD/RXD at the transceiver
19505
Figure 19. Write Data Waveform with Extended Index
START ADDRESS & CONTROL
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
19506
Figure 20. Read Data Waveform
19502
Figure 16. Special Command Waveform
START
ADDRESS,INDEX, DIR. START
DATA
SCLK
IRTX/
SWDAT
19507
Figure 21. Read Data Waveform with Extended Index
IRRX/
SRDAT
Note: During a read transaction the infrared controller sets the
19503
IRTX/SWDAT line high after sending the address and index byte
Figure 17. Write Data Waveform
(or bytes). It will then set it low two clock cycles before the end of
the transaction. It is strongly recommended that optical transceiv-
Note: If the APEN bit in control register 0 is set to 1, the internal sig-
ers monitor this line instead of counting clock cycles in order to
nal from the receiver photo diode is disconnected and the IRRX/
detect the end of the read transaction. This will always guarantee
SRDAT line is pulsed low for one clock cycle at the end of a write
correct operation in case two or more transceivers from different
or special command.
manufacturers are sharing the serial interface.
> 30 CLOCK CYCLES
SCLK
IRTX/
SWDAT
IRRX/
SRDAT
19504
Figure 18. Initial Reset Timing
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Switching Characteristics
Maximum capacitive load = 20 pF*)
Parameters
Test Conditions
Min.
Max.
Unit
tCKp
Symbol
SCLK Clock Period
Rising edge of SCLK to next rising edge
of SCLK
250
infinity
ns
tCKh
SCLK Clock High Time
At 2.0 V for single-ended signals
60
tCKI
SCLK Clock Low Time
At 0.8 V for single-ended signals
80
ns
tDOtv
Output Data Valid
(from infrared controller)
After falling edge of SCLK
tDOth
Output Data Hold
(from infrared controller)
After falling edge of SCLK
tDOrv
Output Data Valid
(from optical transceiver)
After rising edge of SCLK
40
ns
tDOrh
Output Data Hold
(from optical transceiver)
After rising edge of SCLK
40
ns
tDOrf
Line Float Delay
After rising edge of SCLK
60
ns
tDIs
Input Data Setup
Before rising edge of SCLK
10
ns
tDIh
Input Data Hold
After rising edge of SCLK
5
ns
ns
40
0
ns
ns
*)
Maximum capacitive load = 20 pF. That is is different from "Serial interface - specification". For the bus protocol see "RECOMMENDED
SERIAL INTERFACE FOR TRANSCEIVER CONTROL, Draft Version 1.0a, March 29, 2000, IrDA". In Appendix B the transceiver related
data are given.
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Appendix B
Application Guideline
In the following some guideline is given for handling
the TFDU8108 in an application ambient, especially
for testing. It is also a guideline for interfacing with a
controller. We recommend to use for first evaluation
the Vishay IRM1802 controller. For more information
see the special data sheet. Driver software is available on request. Contact irdc@vishay.com.
Serial Interface Capability of the Vishay
IrDA Transceivers
Abstract
A serial interface allows an infrared controller to communicate with one or more infrared transceivers. The
basic specification of the IrDA specified interface is
described in "Serial Interface for Transceiver Control,
v 1.0a", IrDA.
This part of the document describes the capabilities of
the serial interface implemented in the Vishay IrDA
transceivers TFDU8108. The VFIR (16 Mbit/s) device
TFDU8108 and the FIR device TFDU6108 (4 Mbit/s)
are using the same interface specification (with specific identification and programming).
IrDA Serial Interface Basics
The "Serial Interface for Transceiver Control" is a
master/slave synchronous serial bus, which uses the
TXD and RXD as data lines and the SCLK as clock
line with a minimum period of 250 ns. The transceiver
works always as slave and jumps into a control mode
on the first rising edge of the clock line remaining
there until the command phase is finished. After
power-on, it is required to initialize the transceiver by
at least 30 clock cycles of SCLK with TXD continuously low before starting programming.
If TXD gets active (high) during the initialization period
the initialization must be repeated.
A data word consists of one byte preceded by one
start bit.
The specified serial interface allows the communication between infrared controller and transceiver
through write and read transactions. In two register
blocks with different functions all data is stored for
operating the interface. The Main Control Registers
allow write and read transactions and here the executable configuration of the device is stored. The
Extended Indexed Registers contain the description
of the supported functionality of the device and can be
read only.
Power-on
After power on the transceiver is in the default mode
shown in table B1.
Addressing
The transceiver is addressable by three address bits.
There are individual and common addresses with the
values shown in table B2.
Registers Data Depth
In general data registers use a data depth of eight
bits. Sometimes it is not necessary to implement the
full depth. In such cases the invisible bits are considered as a zero.
Registers
The register content is listed in the tables B4 to B7.
Data Acknowledgment
Data acknowledgement generated by the slave is
available if the APEN bit is set to 1 in the common
control register, see the "main_ctrl_0" register values
table B4. In IrDA default state this functionality is disabled. It is recommended to enable this function.
Table B1: Power-on default mode
Function
sleep
RXD (Receive)
disable (floating tri-state)
TXD_LED (Emitter driver):
disable
APEN (Acknowledgment)
disable
Infrared Operating Mode (Speed)
SIR
Transmitter Power (Intensity setting)
max. SIR power level
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TFDU8108
Power Mode (active or sleep)
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Table B2: Addressing
Description
Address value ADDR [2:0]
Individual address
010
Common (broadcast) address
111
Table B3: Index Commands
Commands INDEX
[3:0]
Mode
write/read
Actions
Register Name
Data Bits
Data
TFDU8108
default
0h
W/R
Common control
main-ctrl-0 register
[4:0]
00h
1h
W/R
Infrared mode
main-ctrl-1 register
[7:0]
00h
2h
W/R
TXD power level
main-ctrl-2 register
[7:4]
70h
3h - Bh
X
Not used
Ch
X
Not used
Dh
W
Reset transceiver,
Only one byte!
R
Not used
Eh
X
Not used
Fh
W
Not used
R
Extended indexing
Note: The main_ctrl_1 register is written software dependent on the offset value stored in ext_ctrl_7 and ext_ctrl_8 registers.
The main_ctrl_1 register can be set to the following values, shown in the table.
Tables B4 to B7: Control Register Values
The status of the entire transceiver is stored in the
control registers.
Table B4: Register main-ctrl-0
Command structure:
C
0
0
0
0
bit 0
INDEX [3:0], 0h
bit 1
bit 2
1
bit 0
ADDR [0:2]
C is the transfer direction:
bit 1
bit 2
0
bit 4
0
0
0
DATA [7:0]
• C = 1: WRITE or RESET transaction
• C = 0: READ transaction
Main-ctrl-0, register values
Value
Function
bit 0
PM SL - Power Mode Select
low power-mode (shutdown
(sleep) mode)
normal operation power mode
shutdown
Default
bit 1
RX OEN - Receiver Output Enable
IRRX/SRDAT line disable
(tristated)
IRRX/SRDAT line enabled
disabled
bit 2
TLED EN - Transmitter LED Enable
disabled
enabled
bit 3
not used
bit 4
APEN*)
disabled
not used
don’t acknowledge
acknowledge
disabled
*)
APEN - Acknowledge Pulse Enable, (optional)
This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will
be set low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast)
transceiver address. The internal signal from the receiver photo diode is disconnected when this bit is set to 1.
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Table B5: Register main-ctrl-1
Command structure:
C
1
0
0
0
bit 0
INDEX [3:0], 1h
bit 1
bit 2
1
bit 0
bit 1
bit 2
bit 3
ADDR [0:2]
bit 4
bit 5
bit 6
bit 7
DATA [7:0]
Main-ctrl-1, register values
DATA [7:0]
Function
00h
SIR (default)
01h
MIR
02h
FIR
03h
Apple Talk® (FIR functionality)
05h
VFIR - 16
08h
Sharp IR® (SIR functionality)
20h
IrDA CIR
Depending on the values of "ext_ctrl_7" and "ext_ctrl_8" check for correct main_ctrl_1. In case of an error, the transceiver will load 00h
into the main_ctrl_1 register and will not give an acknowledgement.
Table B6: Register main-ctrl-2
Command structure:
C
1
0
0
bit 0
INDEX [3:0], 1h
bit 1
bit 2
1
bit 0
bit 1
bit 2
bit 3
ADDR [0:2]
bit 4
bit 5
bit 6
bit 7
DATA [7:0]
Main-ctrl-2, DATA [7:0], bit 4 to bit 7
DATA
[7:0]
bit
7
bit
6
bit
5
bit
4
bit
3
bit
2
bit
1
bit
0
TXD IRED [mA]
le [mW/sr]
15°
(typ. on axis)
Link distance on axis
Recommended for
8xhFxh
1
x
x
x
x
x
x
x
512
140 (240)
VFIR > 0.7 m,
FIR > 1 m (link distance
limited by receiver
sensitivity)
VFIR/FIR standard
7xh*)
0
1
1
1
x
x
x
x
256
> 70 (120) *)
SIR >1 m
FIR > 0.7 m, VFIR > 0.5 m
SIR, More Ext.
FIR LP
6xh
0
1
1
0
128
35 (60)
SIR > 0.70 m
FIR > 0.50 m
VFIR > 0.30 m
Extended FIR
Low Power
5xh
0
1
0
1
64
16 (30)
SIR > 0.5 m
FIR > 0.30 m
VFIR > 0.30 m
VFIR Low Power/
FIR Low Power
4xh
0
1
0
0
(48)
3xh
0
0
1
1
32
8 (19)
SIR > 0.35 m
FIR > 0.20 m
VFIR > 0.20 m
SIR Low Power
2xh
0
0
1
0
16
40 (10)
1xh
0
0
0
1
8
(5)
0xh
0
0
0
0
x
x
x
x
0
SIR Low Power, min
without optical
windows
SIR > 0.15 m
FIR > 0.10 m
VFIR > 0.10 m
Close distance, e.g.
Docking station
0
*) Device is tested under this condition. Default setting is 7xh.
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TFDU8108
Vishay Semiconductors
IRED current If
[mA]
Intensity Ie
[mW/sr]
d[m] at Ee =
d[m] at Ee =
d[m] at Ee =
d[m] at Ee =
100 mW/m2
40 mW/m2
90 mW/m2
225 mW/m2
512
240
1.55
2.45
1.63
1.03
256
120
1.10
1.73
1.15
0.73
128
60
0.77
1.22
0.82
0.52
64
30
0.55
0.87
0.58
0.37
48
22.5
0.47
0.75
0.50
0.32
32
15
0.39
0.61
0.41
0.26
16
7.5
0.27
0.43
0.29
0.18
8
3.75
0.19
0.31
0.20
0.13
Note: Calculated expected range in dependence of IRED drive current for the case that the receiver sensitivity is not limiting the range, on
axis, for information only.
IRED current If
[mA]
Intensity Ie
[mW/sr]
d[m] at Ee =
d[m] at Ee =
d[m] at Ee =
d[m] at Ee =
100 mW/m2
40 mW/m2
90 mW/m2
225 mW/m2
512
140.0
1.18
1.87
1.25
0.79
256
70.0
0.15
0.23
1.16
0.10
128
35.0
0.59
0.94
0.62
0.39
64
17.5
0.42
0.66
0.44
0.28
48
13.1
0.36
0.57
0.38
0.24
32
8.8
0.30
0.47
0.31
0.20
16
4.4
0.21
0.33
0.22
0.14
8
2.2
0.15
0.23
0.16
0.10
Note: Calculated expected range in dependence of IRED drive current for the case that the receiver sensitivity is not limiting the range;
15° off-axis, for information only.
Table B7: Reading Extended Indexed Registers
Note: Read Data with Extended Index E_INDX is one of the Extended Indexed Registers. It must be addressed via a precursor of writing
all 1s into the normal index location, thus INDEX[3:0] = Fh. It is an 8 bit address value, which must be followed by 3 SCLK cycles plus a
start clock before reading the DATA value. As in the normal Read Transaction, the input signal, TXD, must be set one clock cycle on LOW
(master ready to receive) and then on HIGH for the next 3 SCLKs and continuing through the entire Response Phase. The corresponding
reaction of the RXD line and the 8 bit DATA value is then read out as depicted below, noting that the Read Data value comes after the 3
SCLK cycles.
Read Command structure:
0
1
C
1
1
1
bit 0
INDEX [3:0], Fh
bit 1
bit 2
1
bit 0
bit 1
bit 2
ADDR [0:2]
bit 3
bit 4
bit 5
bit 6
bit 7
E_INDEX [0:7]
Response:
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
DATA [0:7]
Extended Indexed Registers
Action
E_INDEX [7:0]
Register name
DATA [7:0]
in TFDU8108
Definition default
in the TFDU8108
Manufacture ID
00h
ext_ctrl_0
0Bh
Chip information
(Factory reserved)
Read Support, Device ID
01h
ext_ctrl_1
C6h
Device ID
Receiver Recovery Time
Power On Stabilization
04h
ext_ctrl_4
23h
100 µs to 500 µs
Receiver Stabilization
05h
ext_ctrl_5
30h
0
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Action
E_INDEX [7:0]
Register name
DATA [7:0]
in TFDU8108
SCLK Max. Frequency
(4MHz)
Definition default
in the TFDU8108
4 MHz
Common Capabilities
06h
ext_ctrl_6
03h
Low Power Mode and
Programmable Transmitter
Power supported
Supported Infrared Modes
07h
ext_ctrl_7
2Fh
All listed in Receive Mode
Supported Infrared Modes
08h
ext_ctrl_8
01h
Sharp IR
Mask ID: Released Ver. Set,
followed by Revision Letter
F0h
ext_ctrl_240
0Ah
Chip information
(Factory reserved)
Invalid Commands Handling
Reset
Commands and register addresses, which cannot be
encoded by the Serial Interface, are ignored by the
internal logic as invalid data. Below the different types
invalid command handling and the slave reaction is
shown.
Two ways to set the serial interface into a defined
state are available: The brute force method is to
switch the power off and on and let the device recover
in the default state. The software method is to set the
IRTX/SWDAT line low for ≥ 30 clock cycles of the
clock line. If this line is detected as low for ≥ 30 clock
cycles the transceiver is set into the command start
state and all registers are set to the as default implemented values.
Table B8: Invalid Commands Handling
Description
Master Command
Slave Reaction on RXD/SRDAT
Invalid command in read mode
Index [3:0] & C = 0
no reaction
Invalid command in write mode
Index [3:0] & C = 1
No acknowledgement generating
independent of the value of APEN
Valid command in invalid read mode
Index [3:0] & C = 0
no reaction
Valid command in invalid write mode
Index [3:0] & C = 1
No acknowledgement generating
independent of the value of APEN
Valid command in valid write mode and
invalid data
Index [3:0] & C = 1
No acknowledgement generating
independent of the value of APEN
ADDR [2:0] = 111 & C = 0
no reaction
Broadcast address in read mode
No reaction means that the slave does not start the respond phase.
C is the transfer direction:
• C = 1: WRITE or RESET transaction
• C = 0: READ transaction
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Appendix C
SCLK
Serial Interface Programming Guide
The serial interface port of TFDU8108 enables an
interface controller to communicate using a standardized protocol, recall module ID and capability information, and implement receiver bandwidth mode switching, LED power control, shutdown and some other
functions.
This interface requires three signal lines: a clock line
(SCLK) that is used for timing, and two unidirectional
lines multiplexed with the transmitter (TXD, write) and
receiver (RXD, read) signal lines.
Programming sequence formats supported are
• one-byte special commands
• two-byte write commands
• two-byte read commands
• three-byte read commands
One-byte special command sequences are reserved
for time-critical actions, while the two-byte write command is predominantly used to set basic transceiver
characteristics. More information can be found in the
IrDA document "Serial Interface for Transceiver Control, v 1.0a" on http://www.IrDA.org.
Serial Interface Timing Specifications
In general, serial interface programming sequences
are similar to any clocked-data protocol:
• there is a range of acceptable clock rates, measured from rising edge to rising edge
• there is a minimum data setup time before clock
rising edges
• there is a minimum data hold time after clock rising
edges
Recommended programming timing:
• fSCLK < 8 MHz (according to the Serial Interface
Standard, quasi-static programming is possible)
• TSCLK > 125 ns,
• Tsetup > 10 ns,
• Thold > 10 ns
The timing diagrams, see figure 22, show the setup
and hold time for the serial interface programming
sequences.
TX
125 ns < Tclk
18496
Tsetup > 10 ns
Thold > 10 ns
s
Figure 22. Programming Sequence
Protocol Specifications
The serial interface protocol is a command-based
communication standard and allows for the communication between controller and transceiver by way of
serial programming sequences on the clock (SCLK),
transmit (TXD), and receive (RXD) lines. The SCLK
line is used as a clocking signal and the transmit/
receive lines are used to write/read data information.
The protocol requires all transceivers to implement
the write commands, but does not require the readportion of the protocol to be implemented (though all
transceivers must at least follow the various commands, even if they perform no internal action as a
result). This serial interface follows but does not support all read/ write commands or extended commands, supporting only the special commands and
basic write/read commands. Write commands to the
transceiver take place on the SCLK and TXD lines
and may use the RXD line for acknowledgment. A
command may be directed to a single transceiver on
the SCLK, TXD and RXD bus by specifying a unique
three-bit transceiver address, or a command may be
directed to all transceivers on the bus by way of a special three-bit broadcast address code. The Vishay
VFIR transceiver TFDU8108 will respond to transceiver address 010 and the broadcast address 111
only; it ignores all other transceiver addresses.
All commands have a common "header" or series of
leading bits, which take the form shown below.
first bit sent to transceiver
0
1
0/1
Sync.
Bits
R/W
0/1
I0
I1
last bit sent to transceiver.
I2
I3
Commands Index
A0
A1
A2
...
...
Transceiver
Address
The bits shown are placed on the TXD (DATA) line
and clocked into the transceiver using the rising edge
of the SCLK signal. Only the data bits are shown as it
is assumed that a clock is always present, and that
the transceiver samples the data on the rising edge of
each clock pulse.
Note: as illustrated in the diagram above, the protocol uses "Little
Endian" ordering of bits, so that the LSB is sent first, and the MSB
is sent last for register addresses, transceiver addresses, and read/
write data bytes. The notation that follows presents all addresses
and data in LSB-to-MSB order (bits 0, 1, 2, 3, ... 7) unless otherwise
stated.
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One-byte Special Commands
One-byte special commands are used for time-critical
transceiver commands, such as full transceiver reset.
A total of six special commands are possible, although only one command is available on the
TFDU8108.
0
1
1
I0
Sync.
Bits
W
Special Command
Code
I1
I2
I3
A0
A1
A2
Transceiver
Address
0
0
Stop
Bits
Command
Programming Sequence
(Binary)
RESET
(Set all registers to default value)
011 1011 010 00
Two-byte Write Commands
Two-byte write commands are used for setting the
contents of transceiver registers which control transceiver such as shutdown/enable, receiver mode, LED
power level, etc. The register space requires four register address bits (INDEX), although three codes are
used for controlling the transceiver (see above). The
1111 escape code is for extended commands. The 3bit transceiver address (ADDR) is for selecting the
destination, e.g. 010 to TFDU8108 and 001 to
TFDU6108. The second byte is data field (DATA) for
setting the characteristics of the transceiver module,
e.g. SIR mode (00) or VFIR (05) when the register
address is 0001.
The basic two-byte write command is illustrated
below:
1
1
Sync.
Bits
0
W
I0
I1
I2
Commands
Index
I3
A0 A1 A2 A3 D0..07
Transceiver
Address
8 Data
Bits
Some important serial interface
sequences are shown in table C1.
0
0
Stop
Bits
programming
Table C1: Serial interface programming sequences
Command
DATA
Normal (Enable all)
0Fh
01 1 0000 010 1 11110000 00
Shutdown
00h
01 1 0000 010 1 00000000 00
Receiver Mode
main_ctrl_1
DATA
SYNC/C/INDEX/ADDR/1/DATA/STOP
SIR
00h
01 1 1000 010 1 00000000 00
MIR
01h
01 1 1000 010 1 10000000 00
FIR
02h
01 1 1000 010 1 01000000 00
Apple Talk
03h
01 1 1000 010 1 11000000 00
VFIR
05h
01 1 1000 010 1 10100000 00
Sharp-IR
08h
01 1 1000 010 1 00010000 00
LED Intensity
main_ctrl_2
DATA
8 mA
1xh
01 1 0100 010 1 00001000 00
16 mA
2xh
01 1 0100 010 1 00000100 00
32 mA
3xh
01 1 0100 010 1 00001100 00
64 mA
5xh
01 1 0100 010 1 00001010 00
128 mA
6xh
01 1 0100 010 1 00000110 00
256 mA
7xh
01 1 0100 010 1 00001110 00
512 mA
Fxh
01 1 0100 010 1 00001111 00
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TFDU8108 Programming Sequence (Transceiver address: 010)
Common Ctrl
main_ctrl_0
Document Number 82558
Rev. 1.8, 16-Mar-07
TFDU8108
Vishay Semiconductors
Ozone Depleting Substances Policy Statement
It is the policy of Vishay Semiconductor GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating
systems with respect to their impact on the health and safety of our employees and the public, as well as
their impact on the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are
known as ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs
and forbid their use within the next ten years. Various national and international initiatives are pressing for an
earlier ban on these substances.
Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use
of ODSs listed in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments
respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting
substances and do not contain such substances.
We reserve the right to make changes to improve technical design
and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or
unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages,
and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated
with such unintended or unauthorized use.
Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Document Number 82558
Rev. 1.8, 16-Mar-07
www.vishay.com
383
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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