VCUT07B1-HD1-G4-08

VCUT07B1-HD1 www.vishay.com Vishay Semiconductors Bidirectional Symmetrical (BiSy) Single Line ESD Protection Diode in LLP1006-2L FEATURES • Ultra compact LLP1006-2L package • Low package profile < 0.4 mm 2 1 • 1-line ESD protection 21129 • Working range ± 7 V • Low leakage current IR < 0.1 μA 20855 • Low load capacitance CD = 14 pF MARKING (example only) • ESD immunity acc. IEC 61000-4-2 ± 30 kV contact discharge ± 30 kV air discharge XY • Soldering can be checked by standard vision inspection; no X-ray necessary 21121 Bar = pin 1 marking X = date code Y = type code (see table below) • Pin plating NiPdAu (e4) no whisker growth • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) DESIGN SUPPORT TOOLS • PATENT(S): www.vishay.com/patents click logo to get started • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Models  Available ORDERING INFORMATION DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VCUT07B1-HD1 VCUT07B1-HD1-G4-08 8000 8000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING VCUT07B1-HD1 LLP1006-2L U 0.72 mg UL 94 V-0 MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS MSL level 1 Peak temperature max. 260 °C (according J-STD-020) ABSOLUTE MAXIMUM RATINGS VCUT07B1-HD1 PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current Acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 4 A Peak pulse power Pin 1 to pin 2 acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 60 W ESD immunity Operating temperature Storage temperature Contact discharge acc. IEC 61000-4-2; 10 pulses Air discharge acc. IEC 61000-4-2; 10 pulses Junction temperature ± 30 kV ± 30 kV TJ -40 to +125 °C Tstg -55 to +150 °C VESD PATENT(S): www.vishay.com/patents This Vishay product is protected by one or more United States and international patents. Rev. 1.7, 04-Jan-2019 Document Number: 84137 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT07B1-HD1 www.vishay.com Vishay Semiconductors ELECTRICAL CHARACTERISTICS VCUT07B1-HD1 (pin 1 to pin 2 or pin 2 to pin1) (Tamb = 25 °C, unless otherwise specified) PARAMETER Protection paths TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected Nchannel - - 1 lines Reverse stand-off voltage Max. reverse working voltage VRWM - - 7 V Reverse voltage At IR = 0.1 μA VR 7 - - V Reverse current At VRWM = 7 V IR - - 0.1 μA At IR = 1 mA VBR 7.3 - - V - 9 12 V Reverse breakdown voltage At IPP = 1 A Reverse clamping voltage VC At IPP = IPPM = 4 A At VR = 0 V; f = 1 MHz Capacitance CD At VR = 2.5 V; f = 1 MHz - - 15 V - 14 16 pF - 11 - pF CUT THE SPIKES WITH VCUT07B1-HD1: The VCUT07B1-HD1 is a bidirectional and symmetrical (BiSy) ESD protection device which clamps positive and negative overvoltage transients to ground. Connected between the signal or data line and the ground the VCUT07B1-HD1 offers a high isolation (low leakage current, low capacitance) within the specified working range. Due to the short leads and small package size of the tiny LLP1006-2L package the line inductance is very low, so that fast transients like an ESD strike can be clamped with minimal over- or undershoots. TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Axis Title Axis Title 10000 10000 120 100 Rise time = 0.7 ns to 1 ns 8 µs to 100 % 100 80 53 20 µs to 50 % 40 100 40 60 1st line 2nd line 60 2nd line IPPM (%) 1st line 2nd line 2nd line IESD (%) 1000 1000 80 27 100 20 20 0 0 10 -10 0 t (ns) 2nd line 20557 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Rev. 1.7, 04-Jan-2019 10 0 10 20 30 40 50 60 70 80 90 100 20548 10 20 30 40 t (µs) 2nd line Fig. 2 - 8/20 μs Peak Pulse Current Wave Form acc. IEC 61000-4-5 Document Number: 84137 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT07B1-HD1 www.vishay.com Vishay Semiconductors 16 70 f = 1 MHz Pin 2 to 1 14 Acc. IEC 61000-4-2 +8 kV contact discharge 50 12 40 VC-ESD (V) 10 CD (pF) Pin 2 to 1 60 8 6 30 2 20 10 4 0 2 -10 0 -8 -6 -4 -2 0 2 4 6 VR (V) 22630 -20 -10 0 8 Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR 10 20 8 10 Pin 2 to 1 Acc. IEC 61000-4-2 -8 kV contact discharge 0 4 -10 0 VC-ESD (V) 2 VR (V) t (ns) Fig. 6 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 6 Pin 2 to 1 -2 -20 -30 -4 -40 -6 -50 -8 -60 -10 0.01 -70 0.1 1 10 100 1000 10 000 IR (µA) 22631 -10 0 10 20 30 40 50 60 70 80 90 t (ns) 22634 Fig. 4 - Typical Reverse Voltage VR vs. Reverse Current IR Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 15 60 Measured acc. IEC 6100-4-5 (8/20 μs - wave form) 10 Positive surge Acc. IEC 61000-4-2 contact discharge Pin 2 to 1 Positive discharge 40 5 20 0 Pin 2 to 1 VC-ESD (V) VC (V) 10 20 30 40 50 60 70 80 90 22633 VC -5 -10 0 VC-ESD 30 ns -20 -40 Negative surge -15 Negative discharge -60 0 22632 1 2 3 4 5 IPP (A) Fig. 5 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP Rev. 1.7, 04-Jan-2019 0 22635 5 10 15 20 25 VESD (kV) Fig. 8 - Typical Peak. Clamping Voltage at ESD Contact Discharge (acc. IEC 61000-4-2) Document Number: 84137 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VCUT07B1-HD1 www.vishay.com Vishay Semiconductors 0.25 [0.010] 0.15 [0.006] PACKAGE DIMENSIONS in millimeters (inches): LLP1006-2L 0.65 [0.026] 0.55 [0.022] Orientation identification 0.05 [0.002] 0 [0.000] 0.4 [0.016] 0.33 [0.013] 0.45 [0.018] 0.35 [0.014] 0.125 [0.005] ref. 0.55 [0.022] 0.45 [0.018] 0.3 [0.012] 0.2 [0.008] 1.05 [0.041] 0.95 [0.037] 1 [0.039] Solder resist mask 0.2 [0.008] 0.5 [0.020] 0.6 [0.024] Foot print recommendation: Solder pad 0.5 [0.020] 0.05 [0.002] 0.25 [0.010] Pad Design Patented: ( P US 9.018.537 B2) Document no.: S8-V-3906.04-005 (4) Rev. 7 - Date: 11.May 2016 20812 Unreeling direction LLP1006-2X Orientation identification Top view S8-V-3906.04-017 (4) 02.05.2017 22965 Rev. 1.7, 04-Jan-2019 Pad layout - view from top seen at bottom side Document Number: 84137 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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