TB1328FG
TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB1328FG
Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1328FG includes Audio and video SW blocks, pre-filters for AD converter, sync separations and an H/V format detector for TV signals. The TB1328FG contributes to a reduction in the proportion of PCB occupied by LCR filters and to the simplification of designs in analog interfaces. 2 The TB1328FG is equipped with an I CBUS interface through which various functions can be controlled. LQFP64-P-1010-0.50A Weight: 0.34 g (typ.)
Features
AUDIO SW BLOCK ・ Audio (L/R) inputs: 8 channels ・ Audio (L/R) output: 2 channels VIDEO SW BLOCK ・ CVBS inputs ・ Y/C inputs ・ Component video inputs (co-use as RGB inputs) ・ Output: 1 channel (Y/CVBS/G,C/Cb/B,Cr/R) ・ Monitor output (SY/Y/C/CVBS) VIDEO BLOCK ・ Gain switching: -3 dB / 0 dB / +3 dB(Output: 1 channel) ・ GCA-Amp for only CVBS: 4 to –6dB,6bit(Output: 1 channel) ・ Bandwidth filter: pre-filter for ADC; 5 to 46 MHz variable(Output: 1 channel) ・ +6dB Amp, No pre-filter (Monitor output) SYNC SEPARATION BLOCK ・ Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i, VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60 ・ HD/VD input: 1 channel; positive and negative input acceptable ・ HD/VD output: positive and negative output selectable ・ Masking pseudo-sync for copyguard signal OTHERS ・ Line detector for Japanese D-pin ・ S2, S1, insertion detection for S-pin ・ Horizontal and vertical frequency counter ・ Input signal format detection circuit ・ No-input detection ・ Automatic sync process switching mode ・ Programmable number of video inputs
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TB1328FG
Block Diagram 1 (simplified complete diagram)
This IC will not function with non-standard signals such as weak signals, ghost signals, etc. Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
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TB1328FG
Block Diagram 2 (Video block)
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
"YCbCr OUT" "CbCr PIN1" "CbCr PIN2" "CbCr PIN3" "MON OUT" "YCbCr1 OUT"
as R/G/B as Cb/Cr as C as Y as CVBS
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TB1328FG
Block Diagram 3 (Audio block)
AR1 IN AL1 IN AR2 IN AL2 IN AR3 IN AL3 IN AR4 IN AL4 IN AR5 IN AL5 IN AR6 IN AL6 IN AR7 IN AL7 IN AR8 IN AL8 IN
26 28 30 32 33 35 37 39 41 43 45 47 57 59 61 63
ATT
ATT
ATT Total 0dB
5
AR1 OUT
ATT
ATT
3
ATT Total 0dB
AL1 OUT
ATT
ATT
15
ATT Total 0dB
AR2 OUT
ATT
ATT Total 0dB ATT
13
AL2 OUT
ATT
ATT
ATT
ATT
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
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TB1328FG
Block Diagram 4 (Other blocks)
DC2(S1) DC1(S2)
14 1
TEST
DC DET DC DET
“DC2” 3.3V (typ.)
REG
21 19
Vdd (3.3V) Vss XTAL
“DC1”
clock
XO
20
DC4(LINE3-1) DC5(LINE2-1) DC8(LINE3-2) DC9(LINE2-2)
29
TEST
DC DET DC DET DC DET DC DET
“DC4”
31 51 53
“DC5”
“DC8”
“DC9”
I2CBUS
18 17
SCL SDA
DC3(SW LINE1) DC6(LINE1-1) DC7(SW LINE2) DC10(LINE1-2)
27
TEST
DC DET DC DET DC DET
TEST
“DC3”
34 49 55
“DC6”
“DC7”
DC DET
“DC10”
POL DET
POL DET
TEST
HD IN VD IN SYNC2 IN
23 22 11
BIAS BIAS SYNC TIP H/V SEP H-C/D H DUMMY V-C/D V DUMMY
“HV DUMMY”
POL POL HD WIDTH
"HV OUT" TEST
8 9
HD OUT VD OUT
V SEP
SYNC1 IN
25
SYNC TIP
H/V SEP
FREQ COUNTER
I2CBUS
V SEP
"HV DET"
H/V SEP
"SIG SW"
NO-SIGNAL DET
10
“SIG DET”
SYNC FILTER
This IC will not function with non-standard signals such as weak signals, ghost signals, etc. Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AL4 IN
AL6 IN SY1 IN AR3 IN
AL5 IN
AL3 IN
AR6 IN
AR5 IN
AR4 IN
SC1 IN
Pin Assignment
CVBS3 IN
Cr2/r2 IN Y1/G1 IN Cb1/B1 IN DC6(LINE1-1)
Cr1/R1 IN
49 DC7(SW LINE2) 50 Cb2/B2 IN 51 DC8(LINE3-2) 52 Y2/G2 IN 53 DC9(LINE2-2) 54 Cr3/R3 IN 55 DC10(LINE1-2) 56 Cb3/B3 IN 57 AR7 IN 58 Y3/G3 IN 59 AL7 IN 60 SY2 IN 61 AR8 IN 62 SC2 IN 63 AL8 IN
AL2 IN
32
DC5(LINE2-1) 31 AR2 IN
30
DC4(LINE3-1) 29 AL1 IN DC3 (SW LINE1) AR1 IN
28 27 26
SYNC1 IN 25
6
CVBS/Y/G OUT V/S Vcc (5V) Cr/R OUT Cb/B OUT AL1 OUT AR1 OUT DC1(S2)
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TB1328FG
AU GND 24 HD IN 23 VD IN 22 Vdd (3.3V) 21 XTAL 20 Vss 19 SCL 18 V/S GND DC2(S1) VD OUT SYNC FILTER AU Vcc (9V) AR2 OUT AL2 OUT SYNC2 IN HD OUT SDA 17
64 MONITOR OUT
TB1328FG
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2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TB1328FG
Pin Functions
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Pin No. Pin Name Function VCC pin for the logical circuits. 21 Vdd (3.3 V) Supply power through a resistor from pin 11 as in the Application Circuit. This pin voltage is clipped to 3.3 V (typ.) by the internal regulator. GND pin for the logical circuits. VCC pin for the sync and video circuits. Connect 5.0 V (typ.) GND pin for the sync and video circuits. VCC pin for the audio circuits. Connect 9.0 V (typ.) GND pin for the audio circuits. − − − − −
7
Interface Circuit
Input Signal/Output Signal
3.3 V (typ.)
19 7 12 16 24
Vss V/S VCC (5 V) V/S GND AU VCC (9 V) AU GND
− 5.0 V (typ.) − 9.0 V (typ.) −
42 46 60
SY1 IN CVBS3 IN SY2 IN
CVBS or Y input pin. Input the CVBS or Y signal in NTSC, PAL or SECAM via a clamp capacitor.
42 46 60
200Ω 200Ω
Sync tip level: 2.3 V (typ.) Y/CVBS signal amplitude: 1.0 Vp-p (with sync)
12
Chroma signal input pin. 44 62 SC1 IN SC2 IN
100.2kΩ
Input C signal via a capacitor. This pin’s voltage is detected and the status is returned to I2CBUS Read functions S2 or S6. It is used for detecting whether S-pin is connected or not.
2.9 V bias (typ.) Burst signal amplitude: 0.3 Vp-p
1V
3V
7
100.2kΩ 200Ω
40 52 58
Y1/G1 IN Y2/G2 IN Y3/G3 IN
Y, G or CVBS input pin. Input the signal via a clamp capacitor. The clamp system is selectable by CLAMP1, 2 or 3 registers.
40 52 58
3V/1.5V
Sync tip level: 2.3 V (typ.)
200Ω
Bias level: 2.9 V (typ.) Y/G/CVBS signal amplitude: 1.0 Vp-p (with sync)
3V
12
2.9 V bias (typ.)
100.2kΩ
38 50 56
Cb1/B1 IN Cb2/B2 IN Cb3/B3 IN Cb, B or C input pin. Input the signal via a capacitor.
1V
Cb/B signal amplitude: 0.7 Vp-p (without sync) Burst signal amplitude: 0.3 Vp-p
3V
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TB1328FG
Pin No.
Pin Name
Function
Interface Circuit
7
Input Signal/Output Signal
Sync tip level: 2.3 V (typ.)
100.2kΩ 200Ω
Bias level: 2.9 V (typ.)
200Ω
36 54
Cr1/R1 IN Cr3/R3 IN
Cr, R or CVBS input pin. Input the signal via a capacitor.
36 54
3V/1.5V
Cr/R signal amplitude: 0.7 Vp-p (without sync) CVBS/Y signal amplitude: 1.0 Vp-p (with sync)
12
3V
2.9 V bias (typ.)
100.2kΩ
48
Cr2/R2 IN
Cr, R or C input pin. Input the signal via a capacitor.
1V
Cr/R signal amplitude: 0.7 Vp-p (without sync) Burst signal amplitude: 0.3 Vp-p
26 28 30 32 33 35 37 39 41 43 45 47 57 59 61 63
AR1 IN AL1 IN AR2 IN AL2 IN AR3 IN AL3 IN AR4 IN AL4 IN AR5 IN AL5 IN AR6 IN AL6 IN AR7 IN AL7 IN AR8 IN AL8 IN Audio input pin. Input the signal via a resistor and a capacitor. When the resistor value is 5.6 kΩ , the internal gain becomes 0 dB (typ.). Bias level: 4.4 V (typ.) Audio input: 2.8Ｖp-p (100%)
14 31 34 51 53 55
DC2(S1) DC5(LINE2-1) DC6(LINE1-1) DC8(LINE3-2) DC9(LINE2-2) DC10(LINE1-2) DC voltage input. Input the signal via a resistor for protection purposes.
1V 3V 1V
1V
49
DC7(SW LINE2)
This pin is also used as test signal output pin for shipping only.
150.2Ω
1
DC1(S2)
Input the signal via a resistor for protection purposes.
720.5Ω
DC voltage input.
3V
DC voltage input.
1kΩ
27 29
DC3(SW LINE1) DC4(LINE3-1)
This pin is also used as test signal output pin for shipping only.
150.2Ω
3.25kΩ
Input the signal via a resistor for protection purposes.
3V
3V
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TB1328FG
Pin No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal Sync tip level: 1.8 V (typ.)
Composite SYNC input pin to separate into H- and V-SYNC. 11 25 SYNC IN 2 SYNC IN 1 Input the signal via a clamp capacitor. Remark: SYNC1 IN is not available when A-SYNC = 1 (ON).
1Vp-p
or
HD or VD input pin. 23 22 HD IN VD IN Input a separated horizontal or vertical sync signal (1.0 to 2.0 Vp-p) via a resistor and a coupling capacitor. The polarity of the input signal is detected and its leading edge becomes a timing trigger.
1.45 V bias (typ.)
or
2 4 6
CVBS/Y/GOUT Cb/B OUT Cr/R OUT
Video signal output pin. Refer to Bus Control Functions for the output from each pin. AC: -3, 0 or +3 dB (typ.)
3 5 13 15
AL1 OUT AR1 OUT AL2 OUT AR2 OUT Audio signal output pin. Refer to Bus Control Functions for the output from each pin.
7
Video signal output pin for a monitor output. 64 MONITOR OUT Refer to Bus Control Functions for the output from the pin.
64
AC: +6 dB (typ.)
12
HD or VD output pin. 8 9 HD OUT VD OUT The polarity of the output is selectable by HV-POL register. The tailing edge of the VD-OUT has a jitter. Use the leading edge only.
or
A filter pin for sync detection. 10 SYNC FILTER Connect a capacitor between this pin and GND. −
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TB1328FG
Pin No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
Crystal connection pin. 20 XTAL Connect a 3.579545 MHz crystal for NTSC demodulation to generate internal clocks. −
7
17
SDA
SDA pin for I2CBUS.
17
5kΩ 50Ω ACK
H to L: 1.3 V (typ.) L to H: 2.1 V (typ.)
19 7
18
SCL
SCL pin for I CBUS.
2
18
5kΩ
H to L: 1.3 V (typ.) L to H: 2.1 V (typ.)
19
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TB1328FG
BUS Control Map
Write Mode
SA 00 01 02 03 D7 (0) (0) (0) f0 SW GCA SW (0) CbCr PIN3 (0) CbCr PIN2 (0) CbCr PIN1
Slave address: DEH
D6 (0) (0) (0) D5 (0) (0) FILPASS D4 fc HALF (0) YC MIX BANDWIDTH1 GCA GAIN(D5～D0) CVBS/ＹGAIN (0) CLAMP3 CbCr GAIN CLAMP2 CLAMP1 (0) D3 D2 D1 D0 PRESET 00000000 (0) 00000000 00000000 00000000 00000000 00000000 00000000 00000000 AU1 OUT (0) (0) (0) HV-SEP1 (0) V-DET (0) (0) (0) HD WIDTH (0) (0) (0) (0) (0) (0) (0) (0) HV POL (0) (0) (0) (0) (0) (0) HV FREQ2 H COUNT MIN SIG RESET N SIG SW SIG DET IMPE SIG DET LVL (0) (0) (0) (0) (0) (0) 00010001 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 YCbCrOUT (0) MON OUT (0)
04 GCA V timing 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 (0)TEST1 (0) (0) (0) (0) (0)
(00000000)TEST0 AU2 OUT (0) (0) (0) HV-SEP2 A-SYNC (0) H DMY SIG LPF PS MASK V DMY
SYNC LPF2 SYNC LPF1 (0) HV DET (0) HV OUT
H COUNT MAX SIG DET N (0) SIG RESET
(00000000)TEST2 (00000000)TEST3
NOTE:To activate GCA V timing without V separation (input V sync signal to SYNC2 IN(11 pin)), set D7=1(SA 12H,13H 14H). After changing GCA SW, GCA gain, set D7=0(SA:12H,13H, 14H).
Read Mode
D7 0 1 2 3 4 5 6 7 8 ∗ S6(62Pin) SC2in ＊ POR
Slave address: DFH
D6 H FM2 D5 V FM2 D4 H IN D3 V IN D2 V-SYNC-W V FORMAT HV-OUT FORMAT DC2(14PIN) DC6(34Pin) ∗ S3(48Pin) Cr2in DC10(55Pin) S2(44Pin) SC1in S1(38Pin) Cb1in ∗ DC1(1PIN) DC5(31Pin) DC9(53Pin) ∗ D1 HD-POL D0 VD-POL ∗
H FORMAT ＊ SIG DET DC3(27Pin) DC7(49Pin) ∗ S5(56Pin) Cb3in ∗ S4(50Pin) Cb2in
DC4（29Pin） DC8(51Pin)
H FREQ DET V FREQ DET
∗: Undefined
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TB1328FG
Bus Control Functions
Write Mode
Register Name Function Switches the frequency of bandwidth limit filters for Cb/Cr fc HALF The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y. 0: OFF (same for 3 outputs) 1: ON (1/2 fc for Cb/Cr) Preset Value OFF (0)
Selects the output form Y/Cb/Cr OUT (pins 2,4,6). (Y OUT, Cb OUT, Cr OUT)= 0000: Mute (mute, mute, mute) 0001: SY1 (pin 42), SC1 (pin 44), mute 0010: SY2 (pin 60), SC2 (pin 62), mute 0011~0101: Not available 0110: CVBS3 (pin 46), mute, mute 0111: Y1 (pin 40), Cb1 (pin 38), Cr1 (pin 36) (mute, when CbCr PIN1=1) 1000: Y2 (pin 52), Cb2 (pin 50), Cr2 (pin 48) (mute, when CbCr PIN2=1) 1001: Y3 (pin 58), Cb3 (pin 56), Cr3 (pin 54) (mute, when CbCr PIN3=1) 1010: Not available 1011: Cr1(as CVBS) (pin 36), mute, mute(when CbCr PIN1=1) 1100: Cr3(as CVBS) (pin 54), mute, mute(when CbCr PIN3=1) 1101 ~ 1111: Not available Refer also to Function Descriptions. FILPASS Switches the bandwidth limit filter. 0: OFF (filters active) YC MIX 1: ON (bypass) OFF (0) OFF (0)
Mute (0000)
YCbCrOUT
Mixes Y with C for MONITOR OUT (pin64). 0: OFF (for CVBS) 1: MIX (Y+C)
Selects the output form MONITOR OUT (pin 64) . When YC MIX=1, a mixed signal is outputted. 0000: Mute 0001: SY1 (pin 42) (+SC1 (pin 44)) 0010: SY2 (pin 60) (+SC2 (pin 62)) 0011~0101: Not available 0110: CVBS3 (pin 46) (+Cr2 (pin 48), when CbCr PIN2=1) 0111: Y1 (pin 40) (+Cb1 (pin 38)) 1000: Y2 (pin 52) (+Cb2 (pin50)) 1001: Y3 (pin 58) (+Cb3 (pin 56)) 1010: Not available 1011: Cr1((CVBS) (pin 36),when CbCr PIN1=1 ) 1100: Cr3((CVBS) (pin 54) when CbCr PIN3=1 ) 1101 ~ 1111: Not available Refer also to Function Descriptions. Switches the f0 of bandwidth limit filter for YCbCr(RGB) f0 SW 0: LOW 1: HIGH (0) MIN （0000000） 0: GCA V timing OFF 0: GCA OFF 111111: Gain MIN (low) Max (000000) NOTE: If GCA SW is GCA OFF, set GCA Gain to minimum. After setting D7=1(SA:04H,12H,13H,14H) and GCA Gain to MIN(3FH), set D7=0(SA:04H,12H,13H,14H). Switches the f0 of bandwidth limit filter for YCbCr(RGB) and CVBS output form Y/Cb/Cr OUT (pins 2,4,6) 0000000: MIN (low) GCA V timing GCA SW GCA Gain 0: GCA V timing OFF 0: GCA OFF 1111111: MAX (high) LOW
Mute (0000)
MONITOR OUT
BANDWIDTH
1:GCA V timing ON 1:GCA ON
000000: Gain MAX (high)
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Register Name Switches output gain. Gain of CVBS / Y / G OUT outputs (pins 2) is controlled. CVBS / Y GAIN 00: 0dB 01: -3dB 10: +3dB 11: Not available Function Preset Value
Remark: GAIN = 01 (-3dB) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. Switches output gain. Gain of CbCr(B/R) OUT outputs (pins 4,6) is controlled. CbCr GAIN 00: 0dB 01: -3dB 10: +3dB 11: Not available 0dB (00)
Remark: GAIN = 01 (-3dB) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. Changes CbCr1-IN pins function. 0: Component Cb/Cr input (pin 40: Y/G, pin 38: Cb/B, pin 36: Cr/R ) CbCr PIN1 1: Separated C and CVBS input (pin 40: Y, pin 38: C, pin 36: CVBS) * If ”1: Separated C and CVBS input” is selected for CbCr PIN1, then CLAMP1 mode is set for “SYNC TIP CLAMP (for CVBS/Y) & SYNC TIP CLAMP (for CVBS)” Changes CbCr2-IN pins function. CbCr PIN2 0: Component Cb/Cr input (pin 52: Y/G, pin 50: Cb/B, pin 48: Cr/R, pin 46: CVBS) 1: Separated C input (pin 52: Y, pin 50: C, pin 48:C,pin 46: Y) Changes CbCr3-IN pins function. 0: Component Cb/Cr input (pin 58: Y/G, pin 56: Cb/B, pin 54: Cr/R) CbCr PIN3 1: Separated C and CVBS input t (pin 58: Y, pin 56: C, pin 54: CVBS) * If ”1: Separated C and CVBS input” is selected for CbCr PIN3, then CLAMP3 mode is set for “SYNC TIP CLAMP (for CVBS/Y) & SYNC TIP CLAMP (for CVBS)” Switches Y1 (3)/G1(G3) & Cr1(3)/R1(3) clamping mode. The clamping mode for pin 40(58) & pin 36(54) is set. CLAMP1(3) 0: SYNC TIP CLAMP (for Y/G with sync) & BIAS (Cr/R ) 1: BIAS (for RGB without sync) * If ”1: Separated C and CVBS input” is selected for CbCr PIN1(3), then CLAMP mode is set for “SYNC TIP CLAMP (for CVBS/Y) & SYNC TIP CLAMP (for CVBS/Y)” Switches Y2 clamping mode. CLAMP2 The clamping mode for pin 52 is set. 0: SYNC TIP CLAMP (for Y/G with sync) 1: BIAS (for RGB without sync) TEST0 TEST modes for shipping test. Set all to zero. Switches audio outputs from AL/AR1 (2)-OUT (pins 3/5 (13/15)). AU1(2) OUT 0000: MUTE 0010: AL/AR2 (pins32/30) 0100: AL/AR4 (pins39/37) 0110: AL/AR6 (pins 47/45) 1000: AL/AR8 (pins63/61) 0001: AL/AR1 (pins28/26) 0011: AL/AR3 (pins35/33) 0101: AL/AR5 (pins43/41) 0111: AL/AR7 (pins59/57) 1001～1111: Not available AL/AR1 (0001) SYNC TIP (0) SYNC TIP (0) Cb/Cr input (0) Cb/Cr input (0) Cb/Cr input (0)
all 0
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TB1328FG
Register Name Switches the separation level. The H/V sync separation level to SYNC1(2)-IN (pin 25 (11)) is switched. HV-SEP1(2) 00: LOW 11: HIGH LOW (00) Function Preset Value
Remark: The separation level is changed according to the ratio of negative sync width per 1H period. Turns on the LPF for the sync-tip clamp. SYNC LPF1(2) SYNC LPF1(2) for SYNC1(2)-IN pin changes the speed of sync-tip clamp response. Turn this function on for no input detection. 0: OFF Automatic sync processing mode. Sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. Format detection is performed for SYNC2-IN or HD/VD-IN signal selected by HV DET. The result of detection is returned to H,V FORMAT, H,V FM2 and FORMAT. HV FREQ setting is invalid when this mode is active. 0: OFF (Manual switching mode by HV FREQ setting) 1: ON Remark: SYNC1-IN (pin25) is not available when A-SYNC=1(ON). In this case, format detection and H/V separation are applied to SYNC2-IN (pin11). Turns on the LPF for the sync input pin (pin25; SYNC1-IN). SIG LPF When no input detection for weak strength signals is required, turn this function on to reduce noise on the input. Turn this function off for detections such as H, V FORMAT and H, V FREQ DET. 0: OFF 1: ON ON (0) OFF (0) 1: ON OFF (0)
A-SYNC
OFF (0)
Switches the mask mode for pseudo-sync. PS MASK 0: ON (Normal) 1: OFF (for “Sync on G”)
(1)OFF mode is used for “Sync on G” input.
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TB1328FG
Register Name V-DET Function Switches the V format detection mode. 0: 50/60Hz only 1: Full detection Preset Value 50/60 only (0)
Switches the width of HD-OUT (pin 8) from SYNC2-IN (pin11). 0: WIDE HD WIDTH 1: NARROW WIDE (0)
Remark: HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur. Switches the polarity of HD/VD output.
Positive (0) 1: Negative
HV-POL
The polarity of HD/VD OUT (pin 8, 9) is set. 0: Positive Selects the input for format detection.
HV DET
When A-SYNC=0 (Manual mode) 0: SYNC1-IN (pin 25)
SYNC 1: HD/VD-IN (pins 23/22) (0)
When A-SYNC=1 (Automatic mode) This function is invalid. The input is selected by HV OUT. HV OUT Switches the outputs from HD/VD-OUT (pin 8/9). 0: SYNC2-IN (pin11) Outputs the dummy HD when no-input. The dummy HD/VD output’s frequency depends on HV FREQ2 setting (when A-SYNC = OFF) or H,V FORMAT (when A-SYNC = ON). No input detection is based on H IN result. 0: OFF 1: ON (Dummy HD output when no-input) 1: HD/VD-IN (pins 23/22) SYNC2-IN (0)
OFF (0)
H DMY
NOTE: The HD output does not synchronize with input sync when A-SYNC = OFF and when a sync is input. Outputs the dummy VD when no-input. The dummy HD/VD output’s frequency depends on HV FREQ2 setting (when A-SYNC=OFF) or H,V FORMAT (when A-SYNC=ON). No-input detection is based on V IN result. 0: OFF 1: ON (Dummy VD output when no-input)
OFF (0)
V DMY
NOTE: The VD output does not synchronize with input sync when A-SYNC = OFF and when a sync is input.
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Register Name Input format setting. Set the horizontal and vertical mode according to the format that is input. When A-SYNC = ON mode, this setting is invalid. 00000: 15.625 kHz, 50 Hz (625i) 00001: 15.75 kHz, 60 Hz (525i) 00010: 31.25 kHz, 50 Hz (625p) 00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz) 00100: 28.125 kHz, 50 Hz (1125/50i) 00101: 33.75 kHz, 60 Hz (1125/60i) 00110: 37.5 kHz, 50 Hz (750/50p) 00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz) 01000: 31.25 kHz, 50 Hz (1250i) 01001: 37.9 kHz, 60 Hz (SVGA @60 Hz) 01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz) 01011: 75 kHz, 60 Hz (UXGA @60 Hz) 01100: 56.25 kHz, 50 Hz (1125/50p) 01101 ~ 01111: Not available 10000: 15.734 kHz, 30 Hz (525/30p) 10001: 27 kHz, 24 Hz (1125/24p) 10010: 28.125 kHz, 25 Hz (1125/25p) 10011: 33.75 kHz, 30 Hz (1125/30p) 10100: 27kHz, 48 Hz (1125/24sf) 10101 ~ 11111: Not available Selects H-sync higher threshold count number for the no-input detection. 0000: 32 counts H COUNT MIN 1111: 62 counts (2 counts / step) Function Preset Value
15.625 kHz, 50 Hz (00000)
HV FREQ2
H COUNT MAX
32 counts (0000) 16 counts (000) 1 count (0000)
Selects H-sync lower threshold count number for the no-input detection. 000: 16 counts 111: 30 counts (2 counts / step)
SIG DET N
Selects the signal detection count number for input existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts ~ 1111: 30 counts (2 counts / step)
Selects the signal detection count number for input non-existence threshold of the no-input detection. SIG RESET N 0000: 1 count 0001: 2 counts ~ 1111: 30 counts (2 counts / step)
1 count (0000)
Resets the counter for no-input detection. Normal SIG RESET When 1 is sent, the counter for no-input detection is cleared. 0: Normal SIG SW 1: Reset SYNC2-IN (0) (0)
Selects the input to the counter for no-input detection. 0: SYNC2-IN (pin 11) 1: SYNC1-IN (pin 25)
Changes the internal impedance for no-input detection. SIG DET IMPE The time constant of LPF for no-input detection is changed by this function and the capacitor value of SYNC FILTER (pin10). 00: 20 kΩ 10: 10 kΩ 01: 15 kΩ 11: 6 kΩ 20 kΩ (00)
Changes the threshold for no-input detection. SIG DET LVL 00: 0.55 V 10: 1.05 V 01: 0.80 V 11: 1.30 V
0.55 V (00) all 0
TEST1,2,3
TEST modes for shipping test. Set all to zero.
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2006-11-13
TB1328FG
Read Mode
Register Name Power On Reset POR 0: Normal 1: Register preset Function
After power on, 1 is returned at first read. 0 is returned at second and subsequent reads. Horizontal format detection 2 H FM2 0: Known 1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on H FORMAT data. Vertical format detection 2 V FM2 0: Known 1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on V FORMAT data. Input detection to horizontal syncs H IN 0: No-input V IN Input detection to vertical syncs 0: No-input V-SYNC width detection 0: Wide V-SYNC-W 1: Narrow 1: Signal detected 1: Signal detected
Detects V-SYNC width for detecting 1250i format. Under A-SYNC=1(ON), V-SYNC-W shows 1 when VD width from VD-IN pin is narrower than approx. 69 us, or when V-SYNC width from SYNC-IN pin is narrower than approx. 54 us. Polarity detection to HD-IN
HD-POL
0: Positive
1: Negative
Detects the width from the HD-IN pin to determine whether it is negative or not. When the High level of the input is wider than approx. 13.5 us, HD-POL shows 1. Polarity detection to VD-IN VD-POL 0: Positive 1: Negative
Detects the width from the VD-IN pin to determine whether it is negative or not. When the High level of the input is wider than approx. 4.5 ms, VD-POL shows 1. Horizontal format detection H FORMAT 0000: 15.625/15.75 kHz 0001: 28.125 kHz 0010: 31.25/31.5 kHz 0100: 37.5/37.9 kHz 0101: 45/48 kHz 0110: 56.25 kHz 1000: 75 kHz 1001 ~ 1111: Undefined Detects the horizontal format (horizontal frequency). Vertical format detection V FORMAT 000: 50 Hz 100: 25 Hz 001: 60 Hz 101: 24 Hz 010: 48 Hz 110 ~ 111: Undefined 011: 30 Hz 0011: 33.75 kHz 0111: 64/67.5 kHz
Detects the vertical format (horizontal frequency) according to V FREQ DET data. No-input detection. SIG DET 0: No-input 1: A signal detected
The signal to the no-input detection circuit is selected by SIG SW. Refer to relevant functions, H COUNT MAX, H COUNT MIN, SIG DET N, SIG RESET N, SIG RESET, SIG DET IMPE and SIG DET LVL. Format detection result. H and V dummy output frequencies depend on this result. 00000: 15.625 kHz, 50 Hz (625i) 00010: 31.25 kHz, 50 Hz (625p) 00100: 28.125 kHz, 50 Hz (1125/50i) 00110: 37.5 kHz, 50 Hz (750/50p) 01000: 31.25 kHz, 50 Hz (1250i) 01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz) 01100: 56.25 kHz, 50 Hz (1125/50p) 01101 ~ 01111: Not available 10000: 15.734 kHz, 30 Hz (525/30p) 10010: 28.125 kHz, 25 Hz (1125/25p) 10100: 27 kHz, 48 Hz (1125/24sf) 10101 ~ 11111: Not available 00001: 15.75 kHz, 60 Hz (525i) 00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz) 00101: 33.75 kHz, 60 Hz (1125/60i) 00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz) 01001: 37.9 kHz, 60 Hz (SVGA @60 Hz) 01011: 75 kHz, 60 Hz (UXGA @60 Hz) 10001: 27 kHz, 24 Hz (1125/24p) 10011: 33.75 kHz, 30 Hz (1125/30p)
HV-OUT FORMAT
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2006-11-13
TB1328FG
Register Name DC voltage detection for D-pin or S-pin 00: Low (0 V) 01: Mid (2.2 V) 10: Undefined 11: High (5 V) Function
Remark1; See below for the relationship between this function number and the pin number. DC1 - pin 1, DC2 - pin 14, DC3 - pin 27, DC4 - pin 29, DC5 - pin 31, DC6 - pin 34, DC7 - pin 49, DC8 - pin 51, DC9 - pin 53, DC10 - pin 55, DC1 ~ 10 Remark2; for D-pin SW LINE: 00: Connected LINE1: 00: 525 (480) LINE2: 00: interlace LINE3: 00: 4:3 Remark3; for S-pin 00: 4:3 Detects if S-pin is connected or not. 0: Low (not-connected) S1 ~ 6 1: Open (connected) 01: ---01: 750 (720) 01: ---01: 4:3 letter box 01: 4:3 letter box 10: ---10: ---10: ---10: ---10: ---11: Not-connected 11: 1125 (1080) 11: progressive 11: 16:9 11: 16:9
Remark1; An external circuit is necessary to use this function. Refer to Function description. Remark2; See below for the relationship between this function number and the pin number. S1 - pin 38, S2 - pin 44, S3 - pin 48, S4 - pin 50, S5 - pin 56, S6 - pin 62 Counts the vertical frequency of an input selected by SYNC SW. When V-DET=0; 00000000: over 3.5 kHz 01001111: 44 Hz or less 01010000～11111111: No input When V-DET=1; 00000000: over 3.5 kHz 10011001: 23 Hz or less 10011010～11111111: No input To calculate the vertical frequency (Y) ; Convert data read from V FREQ DET into decimal value and call it X. Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4) The error range of X is −1 to +1. Counts the horizontal frequency of an input selected by SYNC SW. When for SYNC-IN; 00000001: No input When for HD/VD-IN; 00000000: No input 11111111: over 85kHz 11111111: over 85kHz [Hz]
V FREQ DET
H FREQ DET
To calculate the horizontal frequency (Y) ; Convert data read from H FREQ DET into decimal value and call it X. Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X) The error range of X is −1 to +1. [Hz]
Note 1: In determining the decision algorithms (detection range, detection times and so on) for H/V frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as signal 2 conditions and I CBUS data transmission in the course of prototype TV set evaluation. Note 2: The READ BUS flags indicate that a certain signal is detected at a given moment. However, the detection result will not be very reliable if only one flag is checked. To obtain accuracy, it is recommended that a judgment will be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time.
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2006-11-13
TB1328FG
Function Descriptions
Output selections
Outputs are switched by I2CBUS registers, as in the following tables. YCbCr1 OUT
Register settings YCbCr OUT Reserved CbCr PIN3 CbCr PIN2 CbCr PIN1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101~1111 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Cr1 (pin 36) Cr3 (pin 54) CVBS3 (pin46) CVBS3 (pin 46) Y1 (pin 40) Y1 (pin 40) Y2 (pin 52) Y2 (pin 52 Y3 (pin 58) Y3 (pin 58) Mute Cr2 (pin 48) Cb1 (pin 38) Cb1 (pin 38) Cb2 (pin 50) Cb2 (pin 50) Cb3 (pin 56) Cb3 (pin 56) Not available Mute Mute Not available Mute Mute y y Mute Mute Cr1 (pin 36) Mute Cr2 (pin 48) Mute Cr3 (pin 54) Mute y y y y y y y y y y y y y y y y y y Not available CVBS/Y/G OUT (pin 2) Mute SY1 (pin 42) SY2 (pin 60) Outputs Cb/B OUT (pin 4) Mute SC1 (pin 44) SC2 (pin 62) Cr/R OUT (pin 6) Mute Mute Mute y y y y Available input CVBS YC YCbCr RGB
∗: Don’t care MONITOR OUT
Register settings MON OUT 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101~1111 YC MIX Reserved CbCr PIN3 CbCr PIN2 CbCr PIN1 ∗ 0 1 0 1 ∗ ∗ ∗ ∗ 0 1 0 1 0 1 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ＊ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ CVBS3 (pin46) CVBS3 (pin 46) CVBS3 (pin 46) + Cr2 (pin 48) Y1 (pin 40) Y1 (pin 40) + Cb1 (pin38) Y2 (pin 52) Y2 (pin 52) + Cb2 (pin 50) Y3 (pin 58) Y3 (pin 58) + Cb3 (pin 56) Not available Cr1 (pin 36) Cr3(pin 54) Not available Not available Outputs MONITOR OUT (pin 64) Mute SY1 (pin 42) SY1 (pin 42) + SC1 (pin 44) SY2 (pin 60) SY2 (pin 60) + SC2 (pin 62) Available input CVBS YC
y y y y y y y y y y y y y y y y y y y
∗: Don’t care
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2006-11-13
TB1328FG
Vertical sync separation for 1250i/50
When HV FREQ2 = 01000, the vertical sync separation for the 1250i/50 is accomplished through the use of a special circuit. The phase of the VD-out (pin 9) depends on the H-SYNC timing shown in the figure below. There is no VD-out when there is no H-SYNC input. In the manual sync processing mode (A-SYNC = OFF), use READ BUS functions, V-SYNC-W and H, V FORMAT (or H, V FREQ DET) to detect the 1250i/50. NOTE: The VD-OUT’s tailing edge has a jitter. Use the leading edge only.
INPUT (First field ) V-SYNC
VD OUT (Pin 9)
Leading edge
Trailing edge with a jitter
INPUT (Second field ) V-SYNC
VD OUT (Pin 9)
Leading edge
Trailing edge with a jitter
HD width
HD-OUT width is selectable by HD WIDTH as below. HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur.
1125/60p signal SYNC-IN (Y-IN)
HD-OUT (HD WIDTH=1)
0.7us (typ)
HD-OUT (HD WIDTH=0) 1.7us (typ)
HD/VD input amplitude
When a 5.6 kΩ is added before the input pin as in the following figure, 5.0 Vp-p pulse input is allowed. However, the acceptable minimum amplitude then becomes 2.0 Vp-p.
1.0 to 2.0 Vp-p Input or 100Ω
2.0 to 5.0 Vp-p Input
pin 22,23 HD/VD-IN 1uF/4.7uF
1uF/4.7uF or
pin 22,23 HD/VD-IN 5.6kΩ
Normal application
For large input application
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2006-11-13
TB1328FG
Automatic sync processing mode (A-SYNC)
Counted horizontal and vertical frequency data to input signal are returned to READ BUS functions, H,V FREQ DET. Also, the detected format is returned to H, V FORMAT and H, V FM2 when the H/V frequencies are in internally-defined ranges. Input detection results, which indicate whether there is an input or not, for H, V-SYNC or HD,VD, are returned to H,V IN. HV-OUT FORMAT indicates the active mode. In automatic sync processing mode (when A-SYNC = ON), this device operates as indicated in the following table according to these READ data. SYNC1-IN pin is also not used for detecting format. INPUT CONDITION Standard format Non-standard format HV-OUT FORMAT, H, V FORMAT status The format as input H, V FM2 status Known H, V IN status Signal HD, VD outputs The separated sync as input
The status indicates not The separated sync as the current condition Unknown Signal input but the last detected format. Dummy HD and VD, of Known: The status indicates not which the frequency the current condition The status indicates not No input No input depends on the HV-OUT but the last detected the current condition but FORMAT status the last detected format. format. NOTE 3: Dummy HD and VD may become unstable while the mode is changing form one format to another.
Manual sync processing mode (A-SYNC=OFF)
In this mode, SYNC1-IN pin is used only for detecting the input format and SYNC2-IN pin is used only for separating H and V syncs for HD and VD outputs. It is possible to detect some input’s formats by means of time-sharing while separating syncs to another input. The following is an example of how to detect H/V frequency when A-SYNC = OFF. 1. Input the signal from Yvi-OUT pin into SYNC1-IN pin. 2. Read data such as H, V FREQ DET and H, V FORMAT. 3. Detect the H/V frequency by microprocessor or similar means, depending on the data obtained. 4. Input the detected signal into SYNC2-IN pin and set HV FREQ2 and so on for SYNC2-IN pin to the detected mode. 5. Continue to monitor the obtained data for SYNC1-IN pin such as H, V FREQ DET and H, V FORMAT. When any alterations are recognized, re-set HV FREQ2 and so on for SYNC2-IN pin. Decision algorithms (for detection range, detection times and so on) for H/V frequency detection should be determined taking into account the above-mentioned errors in measuring H/V frequencies and other factors such as signal conditions and I2CBUS data transmission in the course of prototype TV set evaluation. Note also, in A-SYNC = OFF and H, V DMY = ON mode, dummy HD and VD are output according to HV FREQ2 setting when there is no input.
Fig. The signal route when A-SYNC = ON
I2CBUS
Fig. The signal route when A-SYNC = OFF
I2CBUS
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2006-11-13
TB1328FG
Sync separation level
The sync separation level is changed according to the ratio of H-sync width to one line. Typical sync separation levels for each format are as follows. HV-SEP data 625/50i 525/60i 625/50p 525/60p 1125/50i 1125/60i 750/50p 750/60p 1250/50i 1125/50p 1125/60p 525/30p 1125/24p 1125/25p 1125/30p 1125/24sf VGA/60 SVGA/60 XGA/60 SXGA/60 00 18 18 19 19 27 25 25 24 22 28 27 18 27 27 26 28 20 20 20 22 01 26 26 27 27 34 33 32 31 30 36 34 26 34 34 32 34 26 27 27 29 10 31 31 32 32 40 38 38 36 36 41 39 31 40 40 38 40 32 33 33 34 11 43 43 44 44 52 50 50 49 48 52 52 43 52 52 50 52 43 44 44 45
Unit [%] ; where 286 mVp-p sync for 525/60i and 300 mVp-p sync for others Format detection and sync separation performance are affected by the separation level set by HV-SEP setting and the value of the connected coupling capacitor. Careful evaluation is required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with V-sag and APL (Average Picture Level) fluctuations. For “Sync on G” signal, HD-OUT is not output during V-sync period because there is no H-sync during V-sync period.
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2006-11-13
TB1328FG
No input detection
This function detects if there is an input or not. It is useful for detecting no-input of 525i or 625i, including signals of weakened strength. (1)0 (no-input) 1 (detected) When Nmin ≦ N1≦ Nmax, and when N2 ≧ Ndet, SIG DET returns 1. Where, Nmin: the number set by H COUNT MIN Nmax: the number set by H COUNT MAX Ndet: the number set by SIG DET N N1: the number of H-sync into the counter during an internal window (approx. 2ms) N2: the number of condition where “Nmin ≦ N1 ≦ Nmax” is detected (2) 1 (detected) 0 (no-input) When N1 ≦ Nmin, N1 ≧ Nmax, and when N3 ≧ Nreset, SIG DET returns 0. Where, Nreset: the number set by SIG RESET N N3: the number of condition where “N1 ≦ Nmin and N1 ≧ Nmax” is detected
Fig. block diagram of no-input detection Determine the use of no-input detection following sufficient evaluations using a prototype TV set.
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2006-11-13
TB1328FG
S-pin insertion detection C-IN pins detect DC level to recognize if S-pin is inserted or not.
C-IN pin Chroma
DC DET
"S1～6"
Insertion
No-insertion
S-pin connector
Fig. an application of S-pin insertion detection
V Freq detection
Counts the vertical frequency of an input selected by SYNC SW. When V-DET=0; 00000000: over 3.5 kHz 01001111: 44 Hz or less 01010000～11111111: No input When V-DET=1; 00000000: over 3.5 kHz 10011001: 23 Hz or less 10011010～11111111: No input To calculate the vertical frequency (Y) ; Convert data read from V FREQ DET into decimal value and call it X. Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4) [Hz]
The error range of X is −1 to +1.
ＢＩＮ 0 1～110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 ＤＥＣ 0 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 ＨＥＸ 0 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F Freqｅｎｃｙ[Hz]Freqｅｎｃｙ[Hz] V-det=0 V-det=1 Over 3500 Over 3500 ～ 63.6 63.6 62.4 62.4 61.3 61.3 60.3 60.3 59.2 59.2 58.3 58.3 57.3 57.3 56.4 56.4 55.5 55.5 54.6 54.6 53.8 53.8 53.0 53.0 52.2 52.2 51.4 51.4 50.7 50.7 49.9 49.9 49.2 49.2 48.6 48.6 47.9 47.9 47.2 47.2 46.6 46.6 46.0 46.0 45.4 45.4 44.8 44.8 44Hz or less 44.2
ＢＩＮ 1010000～1101110 1101111 1110000 1110001 1110010 1110011 1110100 1110101 1110110 1110111 1111000 1111001 1111010 1111011～10000110 10000111 10001000 10001001 10001010 10001011 10001100 10001101 10001110 10001111 10010000 10010001～10011000 10011001 10011010～11111111
Freqｅｎｃｙ[Hz]Freqｅｎｃｙ[Hz] V-det=0 V-det=1 ～ No Input ～ 111 6F No Input 31.5 112 70 No Input 31.2 113 71 No Input 30.9 114 72 No Input 30.7 115 73 No Input 30.4 116 74 No Input 30.1 117 75 No Input 29.9 118 76 No Input 29.6 119 77 No Input 29.4 120 78 No Input 29.1 121 79 No Input 28.9 122 7A No Input 28.7 ～ No Input ～ 135 87 No Input 25.9 136 88 No Input 25.7 137 89 No Input 25.5 138 8A No Input 25.3 139 8B No Input 25.1 140 8C No Input 25.0 141 8D No Input 24.8 142 8E No Input 24.6 143 8F No Input 24.4 144 90 No Input 24.3 ～ No Input ～ 153 99 No Input 23Hz or less 154～255 9A～FF No Input No Input
ＤＥＣ
ＨＥＸ
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2006-11-13
TB1328FG
H Freq detection
Counts the horizontal frequency of an input selected by SYNC SW. When for SYNC-IN; 00000001: No input When for HD/VD-IN; 00000000: No input 11111111: over 85kHz 11111111: over 85kHz
To calculate the horizontal frequency (Y) ; Convert data read from H FREQ DET into decimal value and call it X. Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X) [Hz]
The error range of X is −1 to +1.
ＢＩＮ 0 1 10～101100 101101 101110 101111 110000～1010011 1010100 1010101 1010110 1010111～1011100 1011101 1011110 1011111 1100000 1100001 1100010 1100011 1100100 1100101 1100110～1101110 1101111 1110000 1110001 1110010 1110011 1110100～10000100 ＤＥＣ 0 1 45 46 47 84 85 86 93 94 95 96 97 98 99 100 101 111 112 113 114 115 ＨＥＸ 0 1 2D 2E 2F 54 55 56 5D 5E 5F 60 61 62 63 64 65 6F 70 71 72 73 Freqｅｎｃｙ[kHz] Freqｅｎｃｙ[kHz] Sync IN HD/VD IN No Input No Input 0.33 ～ 15.00 15.00 15.33 15.33 15.67 15.67 ～ 28.00 28.00 28.33 28.33 28.67 28.67 ～ 31.00 31.00 31.33 31.33 31.67 31.67 32.00 32.00 32.33 32.33 32.67 32.67 33.00 33.00 33.33 33.33 33.67 33.67 ～ 37.00 37.00 37.33 37.33 37.67 37.67 38.00 38.00 38.33 38.33 ～
ＢＩＮ 10000101 10000110 10000111 10001000 10001001 10001010～10100101 10100110 10100111 10101000 10101001 10101010 10101011～10111101 10111110 10111111 11000000 11000001 11000010 110000１1～11011110 11011111 11100000 11100001 11100010 11100011 11100100～11111110 11111111
ＤＥＣ 133 134 135 136 137 166 167 168 169 170 190 191 192 193 194 223 224 225 226 227 255
ＨＥＸ 85 86 87 88 89 A6 A7 A8 A9 AA BE BF C0 C1 C2 DF E0 E1 E2 E3 FF
Freqｅｎｃｙ[kHz] Freqｅｎｃｙ[kHz] Sync IN HD/VD IN 44.33 44.33 44.67 44.67 45.00 45.00 45.33 45.33 45.67 45.67 ～ 55.33 55.33 55.67 55.67 56.00 56.00 56.33 56.33 56.67 56.67 ～ 63.33 63.33 63.67 63.67 64.00 64.00 64.33 64.33 64.67 64.67 ～ 74.33 74.33 74.67 74.67 75.00 75.00 75.33 75.33 75.67 75.67 ～ Over 85 Over 85
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2006-11-13
TB1328FG
GCA gain
GCA gain is controlled by Y/G/CVBS OUT gain, and controls only CVBS Input signal. GCA gain is controlled by a 6bit I2C-Bus, and this LSI does not have an Input level detection circuit.. In order to perform GCA control, it is necessary to input CVBS/Y/G OUT to SYNC2 IN. By doing so, V latch starts with a Vsepa signal and GCA control becomes possible. In this case, the BUS must be set as CVBS/Y GAIN=1 (-3dB).
0.44Vp-p
-3dB CVBS input
GCA
CVBS output
100IRE 768LSB
0.7Vp-p
256LSB
1.40Vp-p
The following figure shows typical GCA gain characteristics.
0.8 0.7 0.6 Output Level 0.5 0.4 0.3 0.2 0.1 0 0.4 0.6 0.8 1 Input Level 1.2 1.4 1.6 -5 -7 Output Level（Vp-p) GAIN Typ.（ｄB） 5 3 1 -1 -3 Typ. Gain
Min Typ Max Input Level（Vp-p) 0.44 0.6605 0.881 0.9998 1.1015 1.3221 1.4 0.7 0.7 0.7 0.7 0.7 0.7 0.7 Output Level（Vp-p GAIN Typ.（ｄB） 4.0329 0.5043 -1.998 -3.096 -3.938 -5.523 -6.0206 Bin 000000 001101 011010 100001 100111 110100 111111 Dec 0 13 26 33 39 52 63 Hex 00 0D 1A 21 27 34 3F
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2006-11-13
TB1328FG
10 0 -10 -20 -30 -40 -50 0.1 1 Frequency [MHz] 10 100
Gain [dB]
f0 SW = low, BANDWIDTH = min, fc HALF = on f0 SW = low, BANDWIDTH = min f0 SW = high, BANDWIDTH = min f0 SW = high, BANDWIDTH = max
Fig. Typical pre-filter frequency characteristics
50 Cutoff frequency (-3 dB point) [MHz] fo fo fo fo SW SW SW SW = = = = high low high, fc HALF = on low, fc HALF = on
40
30
20
10
0 0 20 40 60 BANDWIDTH data 80 100 120 127
Fig. Typical cutoff frequency characteristics of pre-filter (-3 dB point)
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2006-11-13
TB1328FG
250 fo fo fo fo SW SW SW SW = = = = high low high, fc HALF = on low, fc HALF = on
200
Delay time [ns]
150
100
50
0 0 20 40 60 BANDWIDTH data 80 100 120 127
Fig. Typical delay-time characteristics of pre-filter (group delay @ 1MHz)
Recommended crystal oscillator
When a connected crystal oscillator is used for the XO, the following oscillation specifications are required. Oscillation frequency (fundamental): 3.579545MHz (for NTSC decoding) Frequency tolerance: +/- 50ppm
External CW input into crystal oscillator pin
Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 28 through a capacitor as below. The required specs on the CW are as follows. Input frequency (fundamental): 3.579545MHz +/- 50ppm Input amplitude: 1.0Vp-p +/- 0.5Vp-p
CW
20 XTAL
220pF
28
2006-11-13
TB1328FG
How to deal with unused pins
Unused pins should be dealt with as below. Pins not mentioned below should be connected properly.
Pin No. 1 2 3 4 5 6 8 9 10 11 13 14 15 22 23 25 26 27 28 29 30 31 32 33 34 35 36 37
Pin Name DC1(S2) CVBS/Y/G OUT AL1 OUT Cb/B OUT AR1 OUT Cr/R OUT HD OUT VD OUT SYNC FILTER SYNC2 IN AL2 OUT DC2(S1) AR2 OUT VD IN HD IN SYNC1 IN AR1 IN DC3(SW LINE1) AL1 IN DC4(LINE3-1) AR2 IN DC5(LINE2-1) AL2 IN AR3 IN DC6(LINE1-1) AL3 IN Cr1/R1 IN AR4 IN
Procedure
Procedure 2 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 1 Procedure 3 Procedure 2 Procedure 3 Procedure 4 Procedure 4 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 1
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pin Name Cb1/B1 IN AL4 IN Y1/G1 IN AR5 IN SY1 IN AL5 IN SC1 IN AR6 IN CVBS3 IN AL6 IN Cr2/R2 IN DC7(SW LINE2) Cb2/B2 IN DC8(LINE3-2) Y2/G2 IN DC9(LINE2-2) Cr3/R3 IN DC10(LINE1-2) Cb3/B3 IN AR7 IN Y3/G3 IN AL7 IN SY2 IN AR8 IN SC2 IN AL8 IN MONITOR OUT
Procedure
Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 3
−
−
−
Procedure 1: Connect a 0.01 µF capacitor between this pin and GND. Procedure 2: Connect to GND. Procedure 3: Leave open. Procedure 4: Connect a 10 kΩ resistor between this pin and GND.
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2006-11-13
TB1328FG
How To Start I CBUS
The following describes how to send bus data after power on. Use software to handle the procedure. 1. Turn power on. 2. Transmit all write data.
2
How To Transmit/Receive Via I CBUS
Slave Address: DEH / DFH
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 1 W/R 0/1
2
Start and Stop Conditions
SDA
SCL S Start condition P Stop condition
Bit Transmission
SDA
SCL
SDA must not be changed
SDA may be changed
Acknowledgement
SDA from transmitter SDA from receiver Low impedance at bit 9 only SCL from master S Clock pulse for acknowledgement 1 8 9
High impedance at bit 9
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2006-11-13
TB1328FG
Data Transmit Format 1
S Slave address 7-bit 0A Sub address 8-bit A Transmit data 8-bit MSB P: End condition AP
MSB S: Start condition
MSB A: Acknowledgement
Data Transmit Format 2
S Slave address 0A Sub address ･･････ A Transmit data 1 A A ･･････ AP
Sub address
Transmit data n
Data Receive Format
S Slave address 7-bit MSB 1A Receive data 1 8-bit MSB ･････････ Receive data n AP
MSB
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The slave receiver changes to a transmitter. The end condition is always created by the master.
Optional Data Transmit Format (Automatic Increment Mode)
S Slave address 7-bit MSB 0A1 Sub address 7-bit A Transmit data 1 8-bit MSB ････ Transmit data n 8-bit MSB AP
MSB
In this way, sub addresses are automatically incremented from the specified sub address and data are set.
I2CBUS Conditions
Parameter Low level input voltage High level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH Vhys VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min. 0 2.4 − 0 -10 − 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 Typ. − − 0.7 − − − − − − − − − − − − Max. 1.1 V/S-Vcc − 0.4 10 10 400 − − − − − − − − Unit V V V V µA pF kHz µs µs µs µs ns ns µs µs
NOTE: These parameters are not tested during production and are provided only as information to assist the design of applications.
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TB1328FG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics 9V Vcc Supply voltage 5V Vcc 3.3V Vcc Input pin voltage Y or Sync input amplitude (pin 22,23,25,36,38,40,42,46,48,50,52,54,56,58,60) Power dissipation Power dissipation reduction rate Operating temperature Storage temperature Symbol VCCmax9 VCCmax5 VCCmax3 Vin Yin PD(Note 4) 1/θja Topr Tstg Rating 12.0 6.0 6.0 GND − 0.3 ~ Vcc + 0.3 2.0 1388 11.1 −20 ~ 75 −55 ~ 150 V Vp-p mW mW/°C °C °C V Unit
Note 4: Refer to the figure below. However, these conditions apply only to the case where the device is mounted on a board (50 x 50 mm). Mount the device on a board which is larger than this.
1388
Power consumption reduction ratio PD (mW)
833
0 0
25
75
150
Ambient temperature
Ta
(°C)
Figure PD - Ta Curve
Note 5: Pins of this product are sensitive to electrostatic discharge. When handling this product, protect the environment to avoid electrostatic discharge. Note 6: Install the product correctly. Otherwise, it may result in break down, damage and/or degration to the product or equipment. The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. If any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, operation when these ratings are exceeded may cause break down, damage and/or degradation to any other equipment. Applications using the device should be designed such that each maximum rating will never be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this document.
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TB1328FG
Operating conditions
Characteristic Pin 16 Supply voltage (VCC) Pin 7 Pin 21; Supply power from V/S Vcc (pin 7) via a resistor. Y/G signal input amplitude CVBS/SY input amplitude Y/G signal input frequency CVBS/SY input frequency SC (Chroma) signal input amplitude Cb, Cr, Pb, Pr signal input amplitude Cb, Cr, Pb, Pr signal input frequency R, G, B signal input amplitude R, G, B signal input frequency HD, VD signal input amplitude HD input frequency VD input frequency Pins40,52,58; with sync Pins42,46,60,(36,54); with sync Pins 40,52,58 Pins 42,46,60,(36,54) Pin 44,62(38,48,50,56) Pins36,38,48,50,54,56; 100% color bar signal Pins 36,38,48,50,54,56 Pins36,38,40,48,50,52,54,56,58; 100% white signal without sync Pins 36,38,40,48,50,52,54,56,58 Pins 22,23 Pins 23 for freq counter Pins 22 for freq counter H DC detection input voltage DC1~10 Pins 1,14,27,29,31,34,49,51,53,55 M L S1~6 SDA input current Pins 38,44,48,50,56,62 Pins 17 L Description Min. 8.5 4.7 3.1 − − 0 0 − − 0 − 0 1.0 0 23 3.5 1.4 GND GND − Typ. 9.0 5.0 3.3 1.0 1.0 − 0.7 0.7 ⎯ ⎯ ⎯ ⎯ 2.2 ⎯ ⎯ − Max. 9.5 5.3 3.5 − − 60 8 2 − 60 − 60 2.0 85 3500 V/S Vcc 2.4 0.6 0.6 3 V mA V Vp-p Vp-p MHz MHz Vp-p Vp-p MHz Vp-p MHz Vp-p kHz Hz V Unit
Remark: Supply power to all Vcc pins (pin 7,16,21).
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2006-11-13
TB1328FG
Electrical Characteristics
(Unless otherwise specified, AU VCC = 9 V, V/S VCC = 5 V, Vdd = 3.3 V, Ta = 25°C, I2CBUS data: preset values)
Current Consumption (f0 SW1/2 = 1, BANDWIDTH1/2 = max)
Pin Name AU VCC (pin16) V/S VCC (pin7) Vdd (pin21) Symbol ICCAU ICCVS ICCD Test Conditions − − Resistance to 5 V; R = 180 Ω Min 6.1 54.3 6.2 Typ. 7.8 67.9 9.3 Max 10.3 89.6 12.7 mA Unit
Pin Voltage (test condition: no signal input)
Pin No. 1 2 3 4 5 6 10 11 13 14 15 20 22 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DC1(S2) CVBS/Y1/G1 OUT AL1 OUT Cb1/B1 OUT AR1 OUT Cr1/R1 OUT SYNC FILTER SYNC2 IN AL2 OUT DC2(S1) AR2 OUT XTAL VD IN HD IN SYNC1 IN AR1 IN DC3(SWLINE1) AL1 IN DC4(LINE3-1) AR2 IN DC5(LINE2-1) AL2 IN AR3 IN DC6(LINE1-1) AL3 IN Cr1/R1 IN AR4 IN Cb1/B1 IN AL4 IN Y1/G1 IN AR5 IN SY1 IN Pin Name Symbol V1 V2 V3 V4 V5 V6 V10 V11 V13 V14 V15 V20 V22 V23 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 Test Conditions − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − Min − 1.0 3.8 1.0 3.8 1.0 3.0 1.5 3.8 − 3.8 3.8 1.2 1.2 1.5 4.2 − 4.2 − 4.2 − 4.2 4.2 − 4.2 2.6 4.2 2.6 4.2 2.0 4.2 2.0 Typ. 0.1 1.3 4.1 1.3 4.1 1.3 3.3 1.8 4.1 0.1 4.1 4.05 1.5 1.5 1.8 4.4 0.2 4.4 0.2 4.4 0.1 4.4 4.4 0.1 4.4 2.9 4.4 2.9 4.4 2.3 4.4 2.3 Max − 1.6 4.4 1.6 4.4 1.6 3.6 2.1 4.4 − 4.4 4.3 1.8 1.8 2.1 4.6 − 4.6 − 4.6 − 4.6 4.6 − 4.6 3.2 4.6 3.2 4.6 2.6 4.6 2.6 V Unit
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TB1328FG
Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AL5 IN SC1 IN AR6 IN CVBS3 IN AL6 IN Cr2/R2 IN DC7(SWLINE2) Cb2/B2 IN DC8(LINE3-2) Y2/G2 IN DC9(LINE2-2) Cr3/R3 IN DC10(LINE1-2) Cb3/B3 IN AR7 IN Y3/G3 IN AL7 IN SY2 IN AR8 IN SC2 IN AL8 IN MONITOR OUT Pin Name Symbol V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 V64 Test Conditions − − − − − − − − − − − − − − − − − − − − − − Min 4.2 2.6 4.2 2.0 4.2 2.6 − 2.6 − 2.0 − 2.6 − 2.6 4.2 2.0 4.2 2.0 4.2 2.6 4.2 0.9 Typ. 4.4 2.9 4.4 2.3 4.4 2.9 0.1 2.9 0.1 2.3 0.1 2.9 0.1 2.9 4.4 2.3 4.4 2.3 4.4 2.9 4.4 1.2 Max 4.6 3.2 4.6 2.6 4.6 3.2 − 3.2 − 2.6 − 3.2 − 3.2 4.6 2.6 4.6 2.6 4.6 3.2 4.6 1.5 V Unit
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2006-11-13
TB1328FG
Audio Block
Characteristic I/O gain (AL/AR1, AL/AR2,) I/O frequency characteristic Total harmonic distortion (AL/AR1, AL/AR2,) Input dynamic range Output offset voltage Ripple rejection ratio Mute mode attenuation Crosstalk among inputs S/N ratio Input impedance of input pins Symbol Gauf Fau thd Vdyau Vauswof Vrrr Gaumute Gaucrs Gausn Imau Test Conditions input = 2.8Vp-p, 1 kHz, input resistance 5.6 kΩ -3 dB point, NOTE A input = 2.8 Vp-p 1 kHz, NOTE A NOTE A, NOTE B Offset on AU1(2) OUT between AU1(2) OUT = 0000 to 1000 100Hz and 100mVp-p ripple is added to AU Vcc, NOTE A input = 2.8Vp-p, 1 kHz, NOTE A input = 2.8Vp-p, 1 kHz, NOTE A input = 2.8Vp-p, 1 kHz, NOTE A Pins 26,28,30,32,33,35,37,39,41,43,45,47 ,57,59,61,63 Min -1.0 100 ⎯ 5.6 -30 30 75 75 80 65 Typ 0 ⎯ 0.02 6.5 0 45 85 85 90 87 Max 1.0 ⎯ 0.05 ⎯ +30 ⎯ ⎯ ⎯ ⎯ 109 Unit dB kHz % Vp-p mV dB dB dB dB kΩ
NOTE A: These parameters are not tested during production and are provided only as information to assist the design of applications. NOTE B: Input = 1kHz, the amplitude at which the total harmonic distortion becomes 1%.
Video Block
Characteristic Sync-tip clamp mode Input dynamic range Sync-tip clamp GCA mode Bias mode Monitor out GAIN = -3dB GAIN = 0dB GAIN = +3dB I/O gain GAIN = +6dB GCA min GCA cnt GCA max Symbol Vdsync Vdsyncgca Vdbias Vdmoni G-3 G0 G+3 G+6 Gmin Input = 0.2Vpp 10kHz Gcnt Gmax Gycmy YC MIX gain Gycmc SC-IN to MONITOR-OUT, No input into SY-IN, YC MIX = 1 5.5 6.0 6.5 SY-IN to MONITOR-OUT, No input into SC-IN, YC MIX = 1 BUS setting Y/CVBS GAIN=-3dB YCbCr-OUT FILPASS = 0/1, input = 0.2Vp-p 10 kHz, BANDWIDTH = cnt, f0 SW = 1 MONITOR OUT FILPASS = 0, BANDWIDTH = max, Sine wave input for Bias mode, Y with sync for others. Test Conditions Min 1.5 1.5 1.4 1.35 -3.5 -0.5 2.5 5.5 − − 4.5 5.5 Typ. 1.7 1.7 2.1 1.5 -3.0 0 3.0 6.0 − -3.3 − 6.0 Max − − − − -2.5 0.5 3.5 6.5 -6.5 − − 6.5 dB dB Vp-p Unit
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TB1328FG
Characteristic I/O frequency characteristic 1-1 (YCbCr) I/O frequency characteristic 1-2 (YCbCr) I/O frequency characteristic 1-3 (YCbCr) I/O frequency characteristic 1-4 (CbCr) I/O frequency characteristic 1-5 (CbCr) Differential 1-1 of frequency characteristic among YCbCr outputs Differential 1-2 of frequency characteristic among YCbCr outputs Differential 1-3 of frequency characteristic among YCbCr outputs I/O delay time 1-1 (YCbCr)
YCbCr GAIN = 0dB YCbCr GAIN = +3dB YCbCr GAIN = -3dB YCbCr GAIN = 0dB YCbCr GAIN = +3dB
Symbol fg-3 Fg0 fg+3 fLmax fLcnt fLmin fHmax fHcnt fHmin fhfLmax fhfLcnt fhfLmin fhfHmax fhfHcnt fhfHmin Fdg-3 Fdg0 Fdg+3 fdHmax fdLcnt fdHmin fdHmax fdHcnt fdHmin TdL-3 TdL0 TdL+3 TdLmax TdLcnt TdLmin TdHmax TdHcnt TdHmin
Test Conditions
Min 80
Typ. 100 100 100 16.5 10.5 4.5 46 30.3 13.4 8.3 5.2 2.4 24.1 15.7 6.8 0 0 0 0 0 0 0 0 0 4 4 4 33 48 107 16 20 39
Max − − − 18.0 11.5 5.0 51 34 15 9.1 5.8 2.6 27 18 8.0 − − − 0.90 0.5 0.23 3.2 1.05 0.70 10 10 10 38 55 120 20 25 45
Unit
FILPASS = 1, 0.2 Vp-p input, -3 dB point, NOTE A
80 80 14.0
MHz
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min
YCbCr GAIN = -3dB YCbCr GAIN = 0dB YCbCr GAIN = +3dB
FILPASS = 0, GAIN = 00, f0 SW =0, 0.2 Vp-p input, -3 dB point, NOTE A
9.5 4.0 41
MHz
FILPASS = 0, GAIN = 00, f0 SW = 1, 0.2 Vp-p input, -3 dB point, NOTE A
27 12 7.4
MHz
FILPASS = 0, GAIN = 00, f0 SW = 0, fc HALF = 1, -3 dB point, NOTE A
4.6 2.1
MHz
FILPASS = 0, GAIN = 00, f0 SW = 1, fc HALF = 1, 0.2 Vp-p input, -3 dB point, NOTE A
21 14 6.0 −
MHz
FILPASS = 1, 0.2 Vp-p input, -3 dB point, NOTE A
− − -0.90
MHz
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min
YCbCr GAIN = -3dB
FILPASS = 0, f0 SW = 0, 0.2 Vp-p input, -3 dB point, NOTE A
-0.5 -0.23 -3.2
MHz
FILPASS = 0, f0 SW = 1, 0.2 Vp-p input, -3 dB point, NOTE A
-1.05 -0.70 −
MHz
FILPASS = 1, 1 MHz, NOTE A
− − 28
ns
BANDWIDTH = max I/O delay time 1-2 (YCbCr) BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O delay time 1-3 (YCbCr) BANDWIDTH = cnt BANDWIDTH = min
FILPASS = 0, GAIN = 00, f0 SW = 0, 1 MHz, NOTE A
45 96 10
ns
FILPASS = 0, GAIN = 00, f0 SW = 1, 1 MHz, NOTE A
15 35
ns
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TB1328FG
Characteristic I/O delay time 1-4 (CbCr) BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O delay time 1-5 (CbCr) BANDWIDTH = cnt BANDWIDTH = min Differential 1-1 of delay time among YCbCr outputs
YCbCr GAIN = -3dB YCbCr GAIN = 0dB YCbCr GAIN = +3dB
Symbol TdhfLmax TdhfLcnt TdhfLmin TdhfHmax TdhfHcnt TdhfHmin Tddg-3 Tddg0 Tddg+3 TddHmax TddHcnt TddHmin TddHmax TddHcnt TddHmin TddHmax TddHcnt TddHmin fdgcamin fdgcacnt fdgcamax TgdLmin TgdLcnt TgdLmax fgm Gmute Gcrschs
Test Conditions
Min 55
Typ. 60 91 220 24 34 72 0 0 0 0 0 0 8 14 33 0 0 0 30 30 30 10 10 10 80 -70 -70 -60 3.4
Max 65 100 260 30 39 80 10 10 10 10 10 10 20 20 45 10 10 20 − − − 20 20 20 − -60 -60
Unit
FILPASS = 0, GAIN = 00, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE A
80 190 20
ns
FILPASS = 0, GAIN = 00, f0 SW = 1, fc HALF = 1, 1 MHz, NOTE A
29 66 -10
ns
FILPASS = 1, 1 MHz, NOTE A
-10 -10 -10
ns
Differential 1-2 of delay time among YCbCr outputs Differential 1-3 of delay time between Y and Cb/Cr outputs Differential 1-4 of delay time between Cb and Cr outputs I/O frequency characteristic 2 (CVBS,GCA)
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min GCA GAIN = min GCA GAIN = cnt GCA GAIN = max GCA GAIN = min
FILPASS = 0, f0 SW = 0, 1 MHz, NOTE A
-10 -10 0
ns
FILPASS = 0, f0 SW = 1, fc HALF = 1, 1 MHz, NOTE A
5 25 -10
ns
FILPASS = 0, f0 SW = 0, fc HALF = 1, 1 MHz, NOTE A
-10 -20 −
ns
FILPASS = 1, 0.2 Vp-p input, -3 dB point, NOTE A
− − −
MHz
I/O delay time 2 (CVBS,GCA) GCA GAIN = cnt GCA GAIN = max I/O frequency characteristic 3 (MONITOR) Mute mode attenuation Among input channels Crosstalk Among inputs in a channel HD/VD/ SYNC-in to Video-out FILPASS = 1, 1 MHz, NOTE A
− −
ns
0.2 Vp-p input, -3 dB point, NOTE A 5 MHz sin wave input, NOTE A 5 MHz sin wave input, NOTE A
60 − − − −
MHz dB dB
Gcrsins Gcrsync BANDWIDTH=min, NOTE A
-55 − mV
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2006-11-13
TB1328FG
Synchronization Block (Test condition: A-SYNC = 1 (ON))
Characteristic Symbol Vsep100 525/60i Vsep101 Vsep110 Vsep111 Vsep200 H/V-sync separation level Vsep201 1125/60i Vsep210 Vsep211 Vsep300 Vsep301 SVGA/60 Vsep310 Vsep311 Threshold amplitude for HD input Threshold amplitude for VD input HD-OUT voltage VthHD VthVDn VhdH VhdL HD-OUT width Thdw0 Thdw1 H sync-in to HD-out HD-OUT phase HD-in to HD-out VD-OUT voltage Sync sep 1250i ODD VD-OUT width 1250i EVEN Free-run 1 Free-run 2 V sync-in to VD-out VD-OUT phase H sync-in to VD-out VD-in to VD-out Thdp2 VvdH VvdL Tvdws Tvdwodd When 1250i input Tvdweven Tvdwfi Tvdwfp Tvdp Tvdp1250 Tvdphv Free-run VD-OUT in interlace mode Free-run VD-OUT in progressive mode Except 1250/50i input, NOTE D 1250/50i input, H sync-in to VD-out, NOTE D HV OUT = 1, NOTE A Thdp1 HV-SEP = 10, NOTE A, NOTE C HV-SEP = 11, NOTE A, NOTE C HV OUT = 1 HV OUT = 1 High level Low level HD WIDTH = 0 HD WIDTH = 1 HV OUT = 0, 1125/60p input, NOTE D HV OUT = 1, NOTE A High level Low level Separated VD-OUT 25 37 0.8 0.9 1.0 − 1.0 − − − − − − − − − 33 44 − − 1.2 0.1 1.7 0.7 90 20 1.2 0.1 290 285 270 4 8 0.20 320 20 39 50 − − 1.4 0.4 1.4 0.4 − − − − − − − − H us us ns ns V us Vp-p Vp-p V HV-SEP = 10, NOTE A, NOTE C HV-SEP = 11, NOTE A, NOTE C HV-SEP = 00, NOTE A, NOTE C HV-SEP = 01, NOTE A, NOTE C 33 45 14 21 38 50 20 27 45 55 26 33 % Test Conditions HV-SEP = 00, NOTE A, NOTE C HV-SEP = 01, NOTE A, NOTE C HV-SEP = 10, NOTE A, NOTE C HV-SEP = 11, NOTE A, NOTE C HV-SEP = 00, NOTE A, NOTE C HV-SEP = 01, NOTE A, NOTE C Min 12 20 26 38 20 27 Typ 18 26 31 43 25 33 Max 24 32 38 50 30 38 % % Unit
H ns ns
NOTE C: 286 mVp-p sync input for 525/60i, 0.3 Vp-p sync input for 1125/60i and SVGA/60. NOTE D: See the following figures.
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TB1328FG
Characteristic Symbol fh156 fh157/60i fh312 fh315 fh281/50i fh337/60i fh375 fh450 Dummy HD-OUT frequency fh1250 fh379 fh640 fh750 fh562 Test Conditions HV FREQ2 = 00000, H DMY = 1 HV FREQ2 = 00001, H DMY = 1 HV FREQ2 = 00010, H DMY = 1 HV FREQ2 = 00011, H DMY = 1 HV FREQ2 = 00100, H DMY = 1 HV FREQ2 = 00101, H DMY = 1 HV FREQ2 = 00110, H DMY = 1 HV FREQ2 = 00111, H DMY = 1 HV FREQ2 = 01000, H DMY = 1 HV FREQ2 = 01001, H DMY = 1 HV FREQ2 = 01010, H DMY = 1 HV FREQ2 = 01011, H DMY = 1 HV FREQ2 = 01100, H DMY = 1 Min − − − − − − − − − − − − − − Typ. 15.564 15.701 31.401 31.401 27.966 33.771 37.288 44.746 31.401 37.288 66.288 74.577 55.932 15.700 27.117 27.965 33.769 27.117 312.5 262.5 625 525 562.5 562.5 750 750 624.5 625.5 628 1066 1250 1125 525 1125 1125 1125 562.5 Max − − − − − − − − − − − − − kHz Unit
fh157/30p HV FREQ2 = 10000, H DMY = 1 fh270 HV FREQ2 = 10001, H DMY = 1
− − − − −
− − − − − − − − − − − − − − − H
− − − −
− − − − − − − − − − − − − − −
fh281/25p HV FREQ2 = 10010, H DMY = 1 fh337/30p HV FREQ2 = 10011, H DMY = 1 fh270/48sf HV FREQ2 = 10100, H DMY = 1 fv625i fv525i fv625p fv525p fv1125i50 fv1125i60 fv750p50 fv750p60 fv1250iO Dummy VD-OUT frequency fv1250iE fvsvga fvsxga fvuxga HV FREQ2 = 00000, V DMY = 1 HV FREQ2 = 00001, V DMY = 1 HV FREQ2 = 00010, V DMY = 1 HV FREQ2 = 00011, V DMY = 1 HV FREQ2 = 00100, V DMY = 1 HV FREQ2 = 00101, V DMY = 1 HV FREQ2 = 00110, V DMY = 1 HV FREQ2 = 00111, V DMY = 1 HV FREQ2 = 01000, V DMY = 1, ODD HV FREQ2 = 01000, V DMY = 1, EVEN HV FREQ2 = 01001, V DMY = 1 HV FREQ2 = 01010, V DMY = 1 HV FREQ2 = 01011, V DMY = 1
fv1125p50 HV FREQ2 = 01100, V DMY = 1 fv525p30 HV FREQ2 = 10000, V DMY = 1
fv1125p24 HV FREQ2 = 10001, V DMY = 1 fv1125p25 HV FREQ2 = 10010, V DMY = 1 fv1125p30 HV FREQ2 = 10011, V DMY = 1 fv1125s24 HV FREQ2 = 10100, V DMY = 1
− − − −
− − − −
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2006-11-13
TB1328FG
Other Blocks
Characteristic XTAL oscillation amplitude No signal detection filter Symbol Vosc tnsfil1 Test Conditions NOTE A, NOTE E SIG LPF = 1, NOTE F, NOTE A Min − 0.5 14 11 7 4.2 0.45 0.70 0.90 1.15 0.8 Pins 1,14,27,29,31,34,49,51,53,55 VdcthMH VdcthS Imdc Pins 38,44,48,50,56,62 Pins 1,14,27,29,31,34,49,51,53,55 2.8 0.8 100 3.0 1.0 150 3.2 1.2 V kΩ Typ. 0.4 1.5 20 15 10 6.0 0.55 0.80 1.05 1.30 1.0 Max − 2.0 26 19 13 7.8 0.65 0.90 1.15 1.40 1.2 V V kΩ Unit Vp-p µs
Imnsfil200 SIG DET IMPE = 00, NOTE G Imnsfil201 SIG DET IMPE = 01, NOTE G Impedance for no signal detection filter Imnsfil210 SIG DET IMPE = 10, NOTE G Imnsfil211 SIG DET IMPE = 11, NOTE G Vthns00 No signal detection threshold voltage Vthns01 Vthns10 Vthns11 L⇔M DC detection threshold (DC) DC detection threshold (S) Input impedance of DC detection pins M⇔H VdcthLM SIG DET LVL = 00, NOTE H SIG DET LVL = 01, NOTE H SIG DET LVL = 10, NOTE H SIG DET LVL = 11, NOTE H
NOTE E: The amplitude of oscillation wave at the point between the crystal and the series capacitor. NOTE F: Remove the external capacitor connected to SYNC FILTER pin (pin 10), HV SEP1 = 00, SIG DET SW = 1(SYNC-1IN), SIG DET IMPE=11. The delay time from SYNC1-IN input (525/60i) to SYNC FILTER wave form. NOTE G: Remove the external capacitor connected to SYNC FILTER pin (pin 10). Connect 10 kΩ resistor between SYNC FILTER pin and GND. No input into SYNC1-IN. Measure the current (Ir) on the resistor. Imnsfil2xx = 3.3 / Ir - 10kΩ. NOTE H: Remove the external capacitor connected to SYNC FILTER pin (pin 10). Input a 0V - Vthnsxx [V] pulse of 15.7 kHz into SYNC FILTER pin. The pulse voltage when SIG DET status changes.
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2006-11-13
TB1328FG
Test circuit
Vcc 5V Vcc 9V
100μF 100μF 0.01μF 0.01μF 100μF
+ + +
AR2 IN
AL2 IN
AL1 IN
AR1 IN
SYNC1 IN
HD IN
75Ω
DC5
DC4
DC3
VD IN
47μF 1/2W 180Ω 0.01μF
100pF 10kΩ
5.6kΩ
1μF 5.6kΩ
10kΩ
1μF 5.6kΩ
5.6kΩ
10kΩ
0.1μF
100Ω
100Ω
10pF
1μF
#32
#30
#28
#26
#25
#23
4.7μF
1μF
#22
#21
#20
3.579545MHz
0.1μF
0.1μF
100pF
0.1μF
100pF
100pF
1μF
470Ω
SDA SDA 17
470Ω
32
DC5(LINE2-1) 31
30
DC4(LINE3-1) 29
28
27
26
SYNC1 IN 25
AU GND 24
HD IN 23
VD IN 22
Vdd (3.3V) 21
XTAL 20
Vss 19
DC3 (SW LINE1)
AL2 IN
AR2 IN
AL1 IN
AR1 IN
SCL 18
SCL
100pF #33
33
5.6kΩ 1μF 10kΩ 0.1μF 100pF 5.6kΩ 1μF 75Ω 100pF 1μF #37 #36 #35
AU Vcc (9V) AR2 OUT DC2(S1) AL2 OUT V/S GND SYNC2 IN SYNC FILTER
34
DC6(LINE1-1) AL3 IN Cr1/R1 IN AR4 IN Cb1/B1 IN AL4 IN
15
DC6 AL3 IN
Cr1/R1 IN
16
AR3 IN
AR3 IN
0.01μF
+
AR2 OUT
10kΩ
35
14
FB OUT AL2 OUT
36
37
38
Cb1/B1 IN
1μF 100pF 5.6kΩ 1μF #40 #39
11
75Ω
#38
#11
0.1μF
75Ω
5.6kΩ
1μF
12
AR4 IN
13
0.1μF
SYNC2 IN
#10
39
Y1/G1 IN
40
75Ω 100pF 1μF 5.6kΩ 1μF 75Ω 1μF 100pF 5.6kΩ 1μF 75Ω
TB1328FG
Y1/G1 IN AR5 IN SY1 IN AL5 IN SC1 IN AR6 IN CVBS3 IN AL6 IN Cr2/r2 IN
49 DC7(SW LINE2) 55 DC10(LINE1-2) 53 DC9(LINE2-2) 51 DC8(LINE3-2) 50 Cb2/B2 IN 56 Cb3/B3 IN
VD OUT HD OUT V/S Vcc (5V) Cr1/R1 OUT AR1 OUT Cb1/B1 OUT AL1 OUT CVBS/Y1/G1 OUT DC1(S2)
64 MONITOR OUT
10
AL4 IN
180pF
VD OUT HD OUT
#7 0.01μF 0.01μF 47μF
+
#41
41
AR5 IN SY1 IN AL5 IN SC1 IN
#42
42
7
8
9
#43
#6
43
47μF
+
6
10Ω 510Ω
44
100pF
5
#44
AR1 OUT
#4 10Ω 510Ω
45
1μF 75Ω 1μF #47 #46
46
AR6 IN
5.6kΩ
#45
Cb1/B1 OUT
AL1 OUT
#2 10Ω CVBS/Y1/G1 OUT
47
CVBS3 IN
2
48
10kΩ
AL6 IN
100pF 5.6kΩ 1μF
DC1
510Ω
1
0.1μF
54 Cr3/R3 IN
52 Y2/G2 IN
58 Y3/G3 IN
57 AR7 IN
62 SC2 IN
59 AL7 IN
60 SY2 IN
61 AR8 IN
Cr2/R2 IN
75Ω 1μF
#48
#56
#61
#62
63 AL8 IN
#57
#58
#50 1μF
#52
1μF
#54
1μF
1μF
1μF
#59
#60
100pF
5.6kΩ 1μF
5.6kΩ 1μF
100pF
5.6kΩ 1μF
1μF
100pF
100pF
#63
10kΩ 0.1μF
10kΩ 0.1μF
10kΩ
10kΩ
75Ω
DC7
75Ω
5.6kΩ 1μF
0.1μF
75Ω
75Ω
0.1μF
75Ω
75Ω
Components in the test circuits are only used to obtain and confirm the device characteristics. These components and circuits do not warrant to prevent the application equipment from malfunction or failure.
MONITOR OUT
DC8
DC9
DC10
Cr2/R2 IN
Cb2/B2 IN
Cr2/R2 IN
Y2/G2 IN
AR7 IN
AR8 IN
AL7 IN
SC2 IN
SY2 IN
Y3/G3 IN
AL8 IN
100pF
75Ω
42
2006-11-13
Main out
100pF
Cr1/R1 OUT
3
4
Audio 6 AR4 IN AL4 IN AR3 IN AL3 IN CVBS3 IN D-pin DC(LINE1-1)
14 7 13 6 12 5 11 4 10 3 9 2 8 1
Audio 5 Audio 3 AR5 IN AL5 IN
Audio 4
AL6 IN Y SY1 IN SC1 IN Cr Cb
Cb1/B1 IN Cr1/R1 IN
AR6 IN DC(SW LINE1)
Y1/G1 IN DC6(LINE1-1) 100pF 5.6kΩ R41 5.6kΩ 100pF 100pF 100pF 100pF 5.6kΩ 5.6kΩ 5.6kΩ 100pF 5.6kΩ 75Ω 75Ω 75Ω 75Ω 1μF 5.6kΩ 1μF 1μF 1μF 75Ω 100pF 100pF 0;1μF 10kΩ 75Ω
5.6kΩ 1μF
1μF
1μF 100pF
1μF
1μF
1μF
1μF
DC(LINE2-1)
DC(LINE3-1)
1μF
1μF
Cr2/R2 IN
1μF 75Ω #43 #36 #34 #40 #39 #38 #37 #35 #33 #48 #42 #47 #46 #45 #44 #41
DC(SW LINE2)
48
7 14
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
#49 10kΩ 0;1μF #50 1μF
6 5 4
AL4 IN
AL6 IN
AL5 IN
AL3 IN
AR6 IN
AR5 IN
AR4 IN
SC1 IN
SY1 IN
AR3 IN
CVBS3 IN
Cr2/r2 IN
Cr1/R1 IN
Y1/G1 IN
Cb1/B1 IN
13 12 11
49 DC7(SW LINE2) 50 Cb2/B2 IN
AL2 IN
32
#32
1μF
5.6kΩ
DC6(LINE1-1)
Application circuit 1 (Typical values)
Audio 2
100pF 10kΩ
AL2 IN AR2 IN
31
#31 1μF 5.6kΩ 0;1μF 10kΩ
D-pin
3 10
DC5(LINE2-1) AR2 IN
Cb2/B2 IN
#51
75Ω
9
2
C
changed by CbCrPIN1=”1"
YorCVBS
CVBS
Y
C
CVBS
DC5(LINE2-1)
8
1
10kΩ DC(LINE3-2) 0;1μF DC(LINE2-2) DC(LINE1-2) 10kΩ 0;1μF #54 #52
51 DC8(LINE3-2)
C
changed by CbCrPin2=”1" changed by CbCrPin2=”1"
30
#30
0;1μF 100pF
DC4(LINE3-1)
52 Y2/G2 IN 53 DC9(LINE2-2) 54 Cr3/R3 IN
DC4(LINE3-1) 29
#29
Y2/G2 IN Y or CVBS CVBS
75Ω
1μF#53
1μF
AL1 IN DC3 (SW LINE1) AR1 IN
28
#28 100pF
5.6kΩ
AL1 IN AR1 IN
10kΩ
Audio 1
27
#27 1μF 5.6kΩ 0;1μF
DC9 Cr3/R3 IN D-SUB15
75Ω 1μF 10kΩ
5 15 10
DC3(SW LINE1)
Input video signals, which are driven with low impedance.
1.5kΩ
DC10
#55
0;1μF
55 DC10(LINE1-2)
26
#26
4
14 9 3 13 8
B G
#56 75Ω 1μF
56 Cb3/B3 IN
SYNC1 IN 25 C
#25
100pF 0.1μF SYNC1 IN
2
12 7
1.5kΩ
AR7 IN AL7 IN SY2 IN
5.6kΩ 1μF 100pF 75Ω 5.6kΩ #61 100pF 100pF 10kΩ #62 1μF #60 75Ω 1μF #59
60 SY2 IN
CVBS
Vdd (3.3V) 21 XTAL 20 Vss 19 SCL 18
470Ω
1/2W 180Ω 0.01μF 10pF #20 3.579545MHz
SC2 IN
61 AR8 IN 62 SC2 IN
#1 #63
AR8 IN
0;1μF 5.6kΩ 1μF
63 AL8 IN 64 MONITOR OUT
Audio 8 AL8 IN
100pF
CVBS/Y1/G1 OUT
SYNC FILTER
Cr1/R1 OUT
V/S GND
AU Vcc (9V)
V/S Vcc (5V)
Cb1/B1 OUT
AL1 OUT
SYNC2 IN
AR1 OUT
AR2 OUT
DC1(S2)
DC2(S1)
VD OUT
AL2 OUT
HD OUT
MONITOR OUT
1 2 3
SDA 17
470Ω
4
5
6
7
8
9
10
11
12
13
14
15
16
2kΩ 1kΩ
47μF 510Ω 510Ω 510Ω 0.01μF
+
100μF
100μF
0.01μF
100μF
0.01μF
AL1 OUT
AR1 OUT
Cr1/R1 OUT
Cb1/B1 OUT
CVBS/Y1/G1 OUT
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits.
Cb3/B3 IN
5.6kΩ 1μF
TB1328FG
2006-11-13
Main out
+
AR2 OUT AL2 OUT
+
+
0.01μF
47μF
+
0.01μF
+
43
1 11
Z2.0V
Z30
R
57 AR7 IN
#57 100pF 75Ω #58 1μF changed by CbCrPin3=”1"
AU GND 24 HD IN 23
#23 1μF 100Ω
6
Z2.0V
Z31
Y3/G3 IN
58 Y3/G3 IN 59 AL7 IN
TB1328FG
V-SYNC
H-SYNC
H-SYNC 4.7μF 100Ω
Y or CVBS
Audio 7
#2 #4 #6 2kΩ 10Ω 10Ω 10Ω
VD IN 22
V-SYNC #22 47μF
S-pin 2
SCL SDA
#10 180pF
#11
0.1μF
#14
Vcc 5V
Vcc 9V
0;1μF 10kΩ
VD OUT
HD OUT
TB1328FG
Application circuit 2 (Examples of Connectors)
39kΩ 22kΩ
5.6kΩ 1μF
5.6kΩ 1μF
75Ω
75Ω
75Ω
100pF
100pF
1μF
1μF
1μF
1μF
DC5(LINE2-1)
DC4(LINE3-1)
Cr1/R1 IN
AL2 IN
DC6(LINE1-1)
8 1 9 2
Y1/G1 IN
10 3 4
Cb1/B1 IN
DC3(SW LINE1)
AR2 IN
SY1 IN
SCART
D
11 5 6 7 6 1 7 2 8 3 9 4 10 5 12 13 14 15
11
12
13
14
D-SUB15
Z2.0V
Z2.0V
5V 100Ω 1μF
100Ω 4.7μF
75Ω
75Ω
0.1μF
1μF
1μF
1μF
34
40
31
38
29
36
27
34
40
31
38
29
36
27
23
22
DC5(LINE2-1)
DC4(LINE3-1)
Cr1/R1 IN
DC6(LINE1-1)
Y1/G1 IN
Cb1/B1 IN
DC3(SW LINE1)
HD IN
VD IN
D-pin
D-SUB15
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits.
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2006-11-13
TB1328FG
Application circuit 3 (system configuration)
(1) For non-standard signals such as CVBS, YC (S-video), 525i, 625i, etc.
TB1328
Video SW Video block Video-in
Color decoder / IP converter / ...
PAL/NTSC/SECAM Color decoder Sync processor
ADC PLL
Sync-in
Sync block
Freq counting block HD/VD-in I/P converter Scaler
Sync SW
The TB1328FG cannot be used for non-standard signals such as weak strength signals, ghost signals, etc. Therefore, these signals should be dealt with through the use of another device such as a color-decoder which is capable of handling these signals. In such cases, the signal switcher and the video circuits of the TB1328FG can be used. Exceptionally, “the no signal detection” can be also used for those signals. The TB1328FG cannot distinguish between component and RGB video. The different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for RGB video input only or component video input only.
(2) For standard component video (SMPTE STANDARD) and standard RGB video (VESA STANDARD)
TB1328
Video SW Video block Video-in
Color decoder / IP converter / ...
PAL/NTSC/SECAM Color decoder Sync processor
ADC PLL
Sync-in
Sync block
Freq counting block HD/VD-in I/P converter Scaler
Sync SW
The TB1328FG can detect the format type of standard signal inputs.
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
45
2006-11-13
TB1328FG
Package dimensions
LQFP64-P-1010-0.50A Unit: mm
Weight: 0.34 g (Typ.)
46
2006-11-13
TB1328FG
About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux
RESTRICTIONS ON PRODUCT USE
• The information contained herein is subject to change without notice. 021023_D
060116EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.021023_C • The products described in this document are subject to the foreign exchange and foreign trade control laws.
021023_E
47
2006-11-13
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