SI9100DJ02-E3

Si9100 Vishay Siliconix 3-W High-Voltage Switchmode Regulator FEATURES D 10- to 70-V Input Range D Current-Mode Control D On-Chip 150-V, 5-W MOSFET Switch D Reference Selection Si9100 − "1% D High Efficiency Operation (> 80%) D Internal Start-Up Circuit D Internal Oscillator (1 MHz) D SHUTDOWN and RESET DESCRIPTION The Si9100 high-voltage switchmode regulators are monolithic BiC/DMOS integrated circuits which contain most of the components necessary to implement high-efficiency dc-to-dc converters up to 3 watts. They can either be operated from a low-voltage dc supply, or directly from a 10- to 70-V unregulated dc power source. The Si9100 may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward), or by using a level shift circuit can generate a +5-V or a −5-V non-isolated output from a −48-V source. The Si9100 is available in both standard and lead (Pb)-free 14-pin plastic DIP and 20-pin PLCC packages which are specified to operate over the industrial temperature range of −40 _C to 85 _C. FUNCTIONAL BLOCK DIAGRAM FB 14 (20) Error Amplifier VREF 10 (14) − + 4 V (1%) Ref Gen 2V − + + − 1.2 V BIAS 1 (2) Current Sources To Internal Circuits C/L Comparator Current-Mode Comparator COMP 13 (18) DISCHARGE 9 (12) OSC IN 8 (11) OSC OUT 7 (10) OSC Clock (1/2 OSC) R Q S 3 (5) 5 (8) DRAIN −VIN (BODY) 4 (7) VCC 11 (16) 12 (17) VCC 6 (9) SOURCE +VIN 2 (3) 8.8 V − + 9.4 V − + Undervoltage Comparator Q S R SHUTDOWN RESET Note: Figures in parenthesis represent pin numbers for 20-pin package. Applications information, see AN702 and AN713. Document Number: 70000 S-42041—Rev. G, 15-Nov-04 www.vishay.com 1 Si9100 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to −VIN (VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 V ID (Peak) (Note: 300 ms pulse, 2% duty cycle) . . . . . . . . . . . . . . . . . . . . 2.5 A ID (rms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA Logic Inputs (RESET, SHUTDOWN, OSC IN) . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SOURCE) . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 3 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 125_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 85_C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 20-Pin PLCC (N Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400 mW Thermal Impedance (QJA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167_C/W 20-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/_C above 25_C c. Derate 11.2 mW/_C above 25_C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Voltages Referenced to −VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 70 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 kW to 1 MW Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 7 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC SPECIFICATIONSa Test Conditions UnlessOtherwise Specified p Parameter Reference Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye VR ZOUT ISREF TREF VREF = −VIN OSC IN = − VIN (OSC Disabled), RL = 10 MW Room Room Room Full 3.92 15 70 4.0 30 100 0.5 4.08 45 130 1.0 V kW mA mV/_C Limits Tempb Minc Typd Maxc Unit Symbol DISCHARGE = −VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 kW , ROSC = 330 kW Oscillator Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente fMAX fOSC Df/f TOSC ROSC = 0 ROSC = 330 kW, See Note f ROSC = 150 kW, See Note f Df/f = f(13.5 V) − f, (9.5 V)/f(9.5 V) Room Room Room Room Full 1 80 160 3 100 200 10 200 120 240 15 500 MHz kHz % ppm/_C Error Amplifier Feedback Input Voltage Input BIAS Current Input OFFSET Voltage Open Loop Voltage Gaine Unity Gain Bandwidthe Dynamic Output Impedancee Output Current Power Supply Rejection www.vishay.com VFB IFB VOS AVOL BW ZOUT IOUT PSRR SOURCE (VFB = 3.4 V) SINK (VFB = 4.5 V) OSC IN = − VIN, (OSC Disabled) OSC IN = − VIN, (OSC Disabled) (OSC FB Tied to COMP OSC In = −VIN (OSC Disabled) OSC IN = −VIN, VFB = 4 V Room Room Room Room Room Room Room Room Room 0.12 50 60 3.96 4.00 25 "15 80 1 1000 −2.0 0.15 70 2000 −1.4 4.04 500 "40 V nA mV dB MHz W mA dB 2 Document Number: 70000 S-42041—Rev. G, 15-Nov-04 Si9100 Vishay Siliconix SPECIFICATIONSa Test Conditions UnlessOtherwise Specified Parameter Parameter Current Limit Threshold Voltage Delay to Outpute VSOURCE td RL = 100 W from DRAIN to VCC VFB = 0 V RL = 100 W from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1 Room Room 1.0 1.2 100 1.4 200 V ns Limits Tempb Minc Typd Maxc Unit Symbol DISCHARGE = −VIN = 0 V VCC = 10 V, +VIN = 48 V RBIAS = 390 kW , ROSC = 330 kW Pre-Regulator/Start-Up Input Voltage Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG −VUVLO +VIN +IIN ISTART VREG VUVLO VDELTA IIN = 10 mA VCC w 10 V Pulse Widthv300 ms VCC = VUVLO IPRE-REGULATOR = 10 mA RL = 100 W from DRAIN to VCC See Detailed Description Room Room Room Room Room Room 8 7.8 7.0 0.3 15 9.4 8.8 0.6 9.7 9.2 V 70 10 V mA mA Supply Supply Current Bias Current ICC IBIAS Room Room 0.45 10 0.6 15 1.0 20 mA mA Logic SHUTDOWN Delaye SHUTDOWN Pulse Widthe RESET Pulse Widthe Latching Pulse Widthe SHUTDOWN and RESET Low Input Low Voltage Input High Voltage Input Current, Input Voltage High Input Current, Input Voltage Low tSD tSW tRW tLW VIL VIH IIH IIL VIN = 10 V VIN = 0 V See Figure 3 Figure VSOURCE = −VIN, See Figure 2 Room Room Room Room Room Room Room Room −35 8.0 1 −25 5 50 50 25 2.0 ns 50 100 V mA MOSFET Switch Breakdown Voltage Drain-Source On Resistanceg Drain Off Leakage Current Drain Capacitance V(BR)DSS rDS(on) IDSS CDS VSOURCE = SHUTDOWN = 0 V IDRAIN = 100 mA VSOURCE = 0 V, IDRAIN = 100 mA VSOURCE = SHUTDOWN = 0 V VDRAIN = 100 V VSOURCE = SHUTDOWN = 0 V Full Room Room Room 35 150 180 3 5 10 V W mA pF Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = v 5 pF g. Temperature coefficient of rDS(on) is 0.75% per _C, typical. Document Number: 70000 S-42041—Rev. G, 15-Nov-04 www.vishay.com 3 Si9100 Vishay Siliconix TIMING WAVEFORMS SOURCE 0 VCC DRAIN 0 − 1.5 V − 50% td tr v 10 ns VCC SHUTDOWN 0 VCC DRAIN 0 50% − − tSD tf v 10 ns 10% 10% FIGURE 1. FIGURE 2. VCC SHUTDOWN 0 VCC RESET 0 − − tSW 50% tLW 50% 50% tRW 50% 50% tr, tf v 10 ns FIGURE 3. TYPICAL CHARACTERISTICS 140 120 100 +V IN (V) 80 60 40 20 0 10 +VIN vs +IIN at Start-Up VCC = −VIN Output Switching Frequency vs. Oscillator Resistance 1M f OUT (Hz) 15 +IIN (mA) 20 100 k 10 k 10 k 100 k rOSC − Oscillator Resistance (W) 1M FIGURE 4. FIGURE 5. www.vishay.com 4 Document Number: 70000 S-42041—Rev. G, 15-Nov-04 Si9100 Vishay Siliconix PIN CONFIGURATIONS PDIP-14 1 2 3 4 5 6 7 Top View 14 13 12 11 10 9 8 PIN DESCRIPTION Pin Function BIAS +VIN DRAIN SOURCE −VIN VCC OSC OUT OSC IN DISCHARGE 14-Pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20-Pin PLCC* 2 3 5 7 8 9 10 11 12 14 16 17 18 20 PLCC-20 3 2 1 20 19 4 5 6 7 8 9 10 11 12 13 Top View 18 17 16 15 14 VREF SHUTDOWN RESET COMP FB *Pins 1, 4, 6, 13, 15, and 19 = N/C ORDERING INFORMATION Standard Part Number Si9100DJ02 Si9100DN02 Lead (Pb)-Free Part Number Si9100DJ02—E3 Si9100DN02—E3 Temperature Range −40 to 85 _C Package PDIP-14 PLCC-20 DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9100 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary “bootstrap” winding on the output inductor or transformer. When power is first applied during start-up, +VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is Document Number: 70000 S-42041—Rev. G, 15-Nov-04 disabled when VCC exceeds 9.4 V. If VCC is not forced to exceed the 9.4-V threshold, then VCC will be regulated to a nominal value of 9.4 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.8 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. www.vishay.com 5 Si9100 Vishay Siliconix DETAILED DESCRIPTION (CONT’D) Note: During start-up or when VCC drops below 9.4 V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48-V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 4 gives the typical pre-regulator current at start-up as a function of input voltage. external resistor between the OSC IN and OSC OUT pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to −VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to v 50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization is accomplished by capacitive coupling of a positive SYNC pulse into the OSC IN terminal. For a 5-V pulse amplitude and 0.5-ms pulse width, typical values would be 100 pF in series with 3 kW to OSC IN. BIAS To properly set the bias for the Si9100, a 390-k W resistor should be tied from BIAS to −VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 mA. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Table 1. Truth Table for the SHUTDOWN and RESET Pins RESET H Reference Section The reference section of the Si9100 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. During the reference trimming procedure the error amplifier is connected for unity gain in order to compensate for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. SHUTDOWN Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with “around-the-amplifier” compensation. A MOS differential input stage provides for low input leakage current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. H H L L Output Normal Operation Normal Operation (No Change) H L L Off (Not Latched) Off (Latched) Off (Latched, No Change) Output Switch Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an The output switch is a 5-W , 150-V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic body-drain diode. However, the body contact in the Si9100 is connected internally to −VIN and is independent of the SOURCE. www.vishay.com 6 Document Number: 70000 S-42041—Rev. G, 15-Nov-04 Si9100 Vishay Siliconix APPLICATIONS GND L1 150 mH @ 0.2 ADC C5 220 mF 10 V 1N5806 8 R3 150 k C1 20 mF C2 0.1 mF 6 3 C3 1 mF R4 3.3 k 14 CR1 Q1 MPSA93 R7 3.9 k R8 10 k 1% R9 10 k 1% 2 C6 0.1 mF +5 V 200 mA 7 13 R10 5k Si9100DJ U1 R5 300 k C7 0.1 mF 10 C8 0.1 mF 4 R2 1W W R6 10 k TL 431C U2 R1 390 k 1 5 9 1/ 2 −48 V FIGURE 6. Buck-Boost, Non-Isolated 1-W Supply GND C5 220 mF 10 V L1 150 mH @ 0.2 ADC C3 1 mF R4 3.3 k 14 C7 0.1 mF 10 C8 0.1 mF 4 R2 1W 1/ W 2 R6 10 k R5 300 k Q1 MPSA93 R7 3.9 k R10 5k R8 10 k 1% R9 10 k 1% 2 8 R3 150 k C1 20 mF C2 0.1 mF 1N5806 CR1 3 C6 0.1 mF −5 V 200 mA 7 Si9100DJ 6 U1 13 R1 390 k 1 5 9 TL 431C U2 −48 V −5 V FIGURE 7. Non-Isolated 1-W Supply (Buck) Document Number: 70000 S-42041—Rev. G, 15-Nov-04 www.vishay.com 7 Si9100 Vishay Siliconix +VIN GND 100 mH 2 1N5819 3 +5 V 20 mF 150 mH 0.1 mF 220 mF 1 4 5 GND 7 18 kW 1 2 390 kW 3 4 5 6 7 1W 2W 14 13 12 240 kW 0.022 mF 8 6 1N5819 −5 V 0.1 mF 47 mF Si9100DJ 11 10 9 8 0.1 mF 12 kW 1 mF 1N4148 1/ 150 kW −VIN (−48 VDC) FIGURE 8. 1-W Flyback Converter for Telecommunications Power Supplies* * For additional information on using the Si9100 in telecommunications and ISDN power supplies, see AN713 and AN702. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70000. www.vishay.com Document Number: 70000 S-42041—Rev. G, 15-Nov-04 8