SI9105DJ02-E3

Si9105 Vishay Siliconix 1-W High-Voltage Switchmode Regulator DESCRIPTION The Si9105 high-voltage switchmode regulator is a monolithic BiC/DMOS integrated circuit which contains most of the components necessary to implement a high-efficiency dc/dc converter in ISDN terminals up to 3 watts. A 0.5 mA max supply current makes possible the design of a dc/dc converter with 60 % efficiency at 25 mW, therefore meeting the recommended performance under the CCITT I.430 specifications. This device may be used with an appropriate transformer to implement isolated flyback power converter topologies to provide single or multiple regulated dc outputs (i.e., ± 5 V). The Si9105 is available in both standard and lead (Pb)-free 16-pin wide-body SOIC, 14-pin plastic DIP and 20-pin PLCC packages which are specified to operate over the industrial temperature range of - 40 °C to 85 °C. FEATURES • • • • • • • • CCITT Compatible Current-Mode Control Low Power Consumption (less than 5 mW) 10 to 120 V Input Range 200 V, 250 mA MOSFET Internal Start-Up Circuit Current-Mode Control SHUTDOWN and RESET FUNCTIONAL BLOCK DIAGRAM FB COMP DISCHARGE OSC IN OSC OUT Error Amplifier VREF + 4 V (1 %) Ref Gen 2V + OSC Clock (½ fOSC) Current-Mode Comparator R Q S + 1.2 V C/L Comparator DRAIN - VIN (BODY) BIAS Current Sources To Internal Circuits VCC SOURCE VCC Undervoltage Comparator Q R RESET S SHUTDOWN +VIN 8.7 V + 9.3 V + Document Number: 70003 S-70497-Rev. I, 19-Mar-07 www.vishay.com 1 Si9105 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Voltages Referenced to - VIN (VCC < + VIN + 0.3 V) VCC +VIN VDS ID (Peak) (300 µs pulse, 2 % duty cycle) ID (rms) Logic Inputs (RESET, SHUTDOWN, OSC IN) Linear Inputs (FEEDBACK, SOURCE) HV Pre-Regulator Input Current (continuous) Storage Temperature Operating Temperature Junction Temperature (TJ) Power Dissipation (Package) a Limit 15 120 200 2 250 - 0.3 V to VCC + 0.3 V - 0.3 V to 7 V 5 - 65 to 125 - 40 to 85 150 750 900 1400 167 140 90 Unit V A mA V mA °C Thermal Impedance (ΘJA) 14-Pin Plastic DIP (J Suffix)b 16-Pin Plastic Wide-Body SOIC (W Suffix)c 20-Pin PLCC (N Suffix)d 14-Pin Plastic DIP 16-Pin Plastic Wide-Body SOIC 20-Pin PLCC mW °C/W Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 6 mW/°C above 25 °C. c. Derate 7.2 mW/°C above 25 °C. d. Derate 11.2 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Voltages Referenced to - VIN VCC + VIN fOSC ROSC Linear Inputs Digital Inputs Limit 10 to 13.5 10 to 120 40 kHz to 1 MHz 25 kΩ to 1 MΩ 0 to VCC - 3 V 0 to VCC Unit V V SPECIFICATIONSa Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 820 kΩ, ROSC = 910 kΩ OSC IN = - VIN (OSC Disabled) R L = 1 0 MΩ OSC IN = - VIN OSC IN = - VIN, VREF = - VIN OSC IN = - VIN t = 1000 h, TA = 125 °C ROSC = 0 See Note e Δf/f = f(13.5 V) - f(9.5 V)/f(9.5 V) Limits Parameter Reference Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye Long Term Stabilitye Oscillator Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente www.vishay.com 2 Symbol Tempb Minc Typd Maxc Unit VR ZOUT ISREF TREF Room Room Room Full Room Room Room Room Full 3.92 15 70 4.00 300 100 0.25 5.00 3 40 10 200 4.08 45 130 1.0 25.00 V kΩ µA mV/°C mV MHz kHz % ppm/°C fMAX fOSC Δf/f TOSC 1 32 48 15 500 Document Number: 70003 S-70497-Rev. I, 19-Mar-07 Si9105 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 820 kΩ, ROSC = 910 kΩ FB Tied to COMP OSC IN = - VIN (OSC Disabled) OSC IN = - VIN, VFB = 4 V OSC IN = - VIN (OSC Disabled) OSC IN = - VIN Source (VFB = 3.4 V) Sink (VFB = 4.5 V) 10 V ≤ VCC ≤ 13.5 V RL = 100 Ω from DRAIN to VCC VFB = 0 V RL = 100 Ω from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1 IIN = 10 µA VCC ≥ 10 V Pulse Width ≤ 300 µs, VCC = 7 V IPRE-REGULATOR = 10 µA RL = 100 Ω from DRAIN to VCC See Detailed Description Limits Parameter Error Amplifier Feedback Input Voltage Input BIAS Current Open Loop Voltage Gain Input OFFSET Voltage e Symbol Tempb Minc Typd Maxc Unit VFB IFB AVOL VOS BW ZOUT IOUT PSRR Room Room Room Room Room Room Room Room Room 3.96 4 25 4.04 500 ± 40 V nA dB mV MHz kΩ 60 0.5 80 ± 15 0.8 1 - 1.2 - 0.32 Unity Gain Bandwidthe Dynamic Output Impedance Output Current Power Supply Rejection Current Limit Threshold Voltage Delay to Outpute Input Voltage Input Leakage Current Pre-Regulator Start-Up Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG - VUVLO Supply Supply Current Bias Current SHUTDOWN Delay SHUTDOWN Pulse Width RESET Pulse Width Latching Pulse Width SHUTDOWN and RESET Low Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low MOSFET Switch Breakdown Voltage Drain-Source On Resistanceg Drain Off Leakage Current 0.05 0.08 70 mA dB VSOURCE td + VIN + IIN ISTART VREG VUVLO VDELTA ICC IBIAS tSD tSW tRW tLW VIL VIH IIH IIL V(BR)DSS rDS(on) IDSS Room Room Room Room Room Room Room Room Room Room 0.8 1.0 200 1.2 300 V ns V 120 10 8 7.5 7.0 0.25 15 9.3 8.7 0.5 0.35 7.5 50 50 50 25 2.0 8.0 1 - 35 200 - 25 220 5 7 10 5 100 0.5 9.7 9.2 µA mA V mA µA VSOURCE = - VIN, See Figure 2 Room Room Room Room Room Room See Figure 3 ns V µA VIN = 10 V VIN = 0 V IDRAIN = 100 µA IDRAIN = 100 mA VDRAIN = 100 V Room Room Full Room Room V Ω µA CDS Room 35 pF Drain Capacitance Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = ≤ 5 pF. g .Temperature coefficient of rDS(on) is 0.75 % per °C, typical. Document Number: 70003 S-70497-Rev. I, 19-Mar-07 www.vishay.com 3 Si9105 Vishay Siliconix TIMING WAVEFORMS 1.5 V SOURCE 0 VCC DRAIN 0 50 % td tr ≤ 10 ns VCC SHUTDOWN 0VCC DRAIN 0 50 % tSD tf ≤ 10 ns 10 % 10 % Figure 1. Figure 2. tSW VCC SHUTDOWN 0VCC RESET 050 % 50 % tRW 50 % 50 % tLW 50 % tr, tf ≤ 10 ns Figure 3. TYPICAL CHARACTERISTICS 1M f OUT (Hz) 100 k 10 k 10 k 100 k rOSC - Oscillator Resistance (Ω) 1M Figure 4. Output Switching Frequency vs. Oscillator Resistance www.vishay.com 4 Document Number: 70003 S-70497-Rev. I, 19-Mar-07 Si9105 Vishay Siliconix PIN CONFIGURATIONS PDIP-14 1 2 3 4 5 6 7 8 Top View SO-16 (Wide-Body) 3 16 15 14 13 12 11 10 9 9 Top View 4 5 6 7 8 PLCC-20 2 1 20 19 1 2 3 4 5 6 7 14 13 12 11 10 9 8 18 17 16 15 14 10 11 12 13 Top View PIN DESCRIPTION Function SOURCE - VIN VCC OSCOUT OSCIN DISCHARGE VREF SHUTDOWN RESET COMP FB BIAS + VIN DRAIN NC Pin Number 14-Pin Plastic DIP 4 5 6 7 8 9 10 11 12 13 14 1 2 3 16-Pin SOIC 1 2 4 5 6 7 8 9 10 11 12 13 14 16 3, 15 20-Pin PLCC 7 8 9 10 11 12 14 16 17 18 20 2 3 5 1, 4, 6, 13, 15, 19 ORDERING INFORMATION Standard Part Number Si9105DJ02 Si9105DW Si9105DW-T1 (With Tape and Reel) Si9105DN02 Si9105DN02-T1 (With Tape and Reel) Si9105DW-T1-E3 (With Tape and Reel) Si9105DN02-E3 Si9105DN02-T1-E3 (With Tape and Reel) PLCC-20 SOIC-16 (WB) - 40 to 85 °C Lead (Pb)-free Part Number Si9105DJ02-E3 Temperature Range Package PDIP-14 Document Number: 70003 S-70497-Rev. I, 19-Mar-07 www.vishay.com 5 Si9105 Vishay Siliconix DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9105 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated lowvoltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, + VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between + VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 9.3 V. If VCC is not forced to exceed the 9.3 V threshold, then VCC will be regulated to a nominal value of 9.3 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.7 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the Si9105 brings the output of the error amplifier (which is configured for unity gain during trimming) to within ± 1 % of 4 V. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, whose 1 kΩ dynamic output impedance enables it to be used with feedback compensation (unlike transconductance amplifiers). A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section BIAS To properly set the bias for the Si9105, a 820 kΩ resistor should be tied from BIAS to - VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 7.5 µA. The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics graph of resistor value vs. frequency.) The DISCHARGE pin should be tied to - VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to a maximum of 50 % by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5 V pulse amplitude and 0.5 µs pulse width, typical values would be 100 pF in series with 3 kΩ to OSC IN. Reference Section The reference section of the Si9105 consists of a temperature compensated buried zener and trimmable divider network. www.vishay.com 6 Document Number: 70003 S-70497-Rev. I, 19-Mar-07 Si9105 Vishay Siliconix DETAILED DESCRIPTION (CONT’D) SHUTDOWN and RESET Output Switch The output switch is a 7 Ω , 200 V lateral DMOS transistor. Like discrete MOSFETs, the switch contains an intrinsic body-drain diode. However, the body contact in the Si9105 is connected internally to - VIN and is independent of the SOURCE. Table 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN H H L L H L L RESET H Output Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change) SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and can be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN pin to provide variable shutdown time. APPLICATIONS +VIN 7 NC Lp = 3.8 mH 2 8 910 k 7 + 20 µF 6 Si9105DJ 0.1 µF NC 12 14 15 k 10 13 0.22 µF 1 0.1 µF 0.1 µF 820 k 5 9 3.9 Ω 47.5 k 1% 4 12 V 71.5 k 1% 9 4 1N5819 11 8 3 1N4148 10 0.1 µF 150 k 47 µF 3 0.1 µF 220 µF 5.6 V OUTPUT 1N5819 2 +5V - - 5V 1 µF INPUT GND (GND Plane) Figure 5. CCITT Compatible ISDN Terminal Power Supply Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70003. Document Number: 70003 S-70497-Rev. I, 19-Mar-07 www.vishay.com 7 Package Information Vishay Siliconix SOIC (WIDE-BODY): 16-LEAD (POWER IC ONLY) 0.2025$0.001 0.06$0.002D CAVITY NO. ECN: S-40079—Rev. A, 02-Feb-04 DWG: 5910 0.334$0.005 R0.004 16 15 14 13 12 0.1475$0.001 0.070$0.005 11 10 9 0.010 R0.008 R0.009 0.295$0.001 R0.004 1 23 4 5 6 7 8 0.032$0.005 DETAIL A 4°$2° 0.055$0.005 PIN 1 INDICATOR 0.0470.007$0.001 dp SURFACE POLISHED 0.334$0.005 0.291$0.001 0.02045° 0.405$0.001 0.091$0.001 0.098$0.002 7°(4) R0.004 0.041$0.001 0.050 TYP. 0.006$0.002 0.017$0.0003 0.295$0.001 0.406$0.004 DETAIL A All Dimensions In Inches Document Number: 72805 28-Jan-04 www.vishay.com 1 Package Information Vishay Siliconix PLCC: 2O-LEAD (POWER IC ONLY) D−SQUARE D1−SQUARE B1 A2 MILLIMETERS Dim A A1 A2 B B1 D D1 D2 e1 Min 4.20 2.29 0.51 0.331 0.661 9.78 8.890 7.37 INCHES Min 0.165 0.090 0.020 0.013 0.026 0.385 0.350 0.290 Max 4.57 3.04 − 0.553 0.812 10.03 9.042 8.38 Max 0.180 0.120 − 0.021 0.032 0.395 0.356 0.330 B e1 D2 1.27 BSC 0.050 BSC A1 A ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5917 0.101 mm 0.004″ Document Number: 72812 28-Jan-04 www.vishay.com 1 Package Information Vishay Siliconix PDIP: 14-LEAD (POWER IC ONLY) 14 13 12 11 10 9 8 E1 E 1 2 3 4 5 6 7 D S Q1 A A1 L 15° MAX eA B1 e1 B C Dim A A1 B B1 C D E E1 e1 eA L Q1 S MILLIMETERS Min Max 3.81 0.38 0.38 0.89 0.20 17.27 7.62 5.59 2.29 7.37 2.79 1.27 1.02 5.08 1.27 0.51 1.65 0.30 19.30 8.26 7.11 2.79 7.87 3.81 2.03 2.03 INCHES Min Max 0.150 0.015 0.015 0.035 0.008 0.680 0.300 0.220 0.090 0.290 0.110 0.050 0.040 0.200 0.050 0.020 0.065 0.012 0.760 0.325 0.280 0.110 0.310 0.150 0.080 0.080 ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5919 Document Number: 72814 28-Jan-04 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1