SIHFB18N50K

IRFB18N50K, SiHFB18N50K Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 120 34 54 Single D FEATURES 500 0.26 • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness Available RoHS* COMPLIANT • Fully Characterized Capacitance and Avalanche Voltage and Current • Low RDS(on) • Lead (Pb)-free Available TO-220 APPLICATIONS G S G D S N-Channel MOSFET • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High Speed Power Switching • Hard Switched and High Frequency Circuits ORDERING INFORMATION Package Lead (Pb)-free SnPb TO-220 IRFB18N50KPbF SiHFB18N50K-E3 IRFB18N50K SiHFB18N50K ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM Energyb LIMIT 500 ± 30 17 11 68 1.8 EAS IAR EAR TC = 25 °C PD dV/dt TJ, Tstg for 10 s 6-32 or M3 screw 370 17 22 220 7.8 - 55 to + 150 300d 10 W/°C mJ A mJ W V/ns °C N A UNIT V Linear Derating Factor Single Pulse Avalanche Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Starting TJ = 25 °C, L = 2.5 mH, RG = 25 Ω, IAS = 17 A. c. ISD ≤ 17 A, dI/dt ≤ 376 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91100 S-80567-Rev. A, 20-Jun-08 www.vishay.com 1 WORK-IN-PROGRESS IRFB18N50K, SiHFB18N50K Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambienta SYMBOL RthJA RthCS RthJC TYP. 0.50 MAX. 58 0.56 °C/W UNIT Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain)a Note a. Rth is measured at TJ approximately 90 °C. SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 1 0 A b 500 3.0 6.4 0.59 0.26 - 5.0 ± 100 50 250 0.29 - V V/°C V nA µA Ω S VDS = 50 V, ID = 10 A VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 400 V, f = 1.0 MHz VDS = 0 V to 400 Vc - 2830 330 38 3310 93 155 22 60 45 30 120 34 54 ns nC pF ID = 17 A, VDS = 400 V, see fig. 6 and 13b VGS = 10 V VDD = 250 V, ID = 17 A, RG = 7.5 Ω, see fig. 10b - - 520 5.3 17 A 68 1.5 780 8.0 V ns µC G S TJ = 25 °C, IS = 17 A, VGS = 0 Vb TJ = 25 °C, IF = 17 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that givs the same charging time as Coss while VDS is rising from 0 to 80 % VDS. www.vishay.com 2 Document Number: 91100 S-80567-Rev. A, 20-Jun-08 IRFB18N50K, SiHFB18N50K Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 100 VGS 15V 12V 10V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V TOP 100.00 ID, Drain-to-Source Current (A) 10 ID, Drain-to-Source Current (A) TJ = 150°C 10.00 1 1.00 0.1 TJ = 25°C 5.0V 0.10 0.01 20µs PULSE WIDTH Tj = 25°C 0.001 0.1 1 10 100 0.01 5.0 6.0 7.0 VDS = 100V 20µs PULSE WIDTH 8.0 9.0 10.0 VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics VGS , Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics RDS(on) , Drain-to-Source On Resistance (Normalized) 100 3.0 ID, Drain-to-Source Current (A) 10 VGS 15V 12 V 10 V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V TOP ID = 17A 2.5 2.0 5.0V 1 1.5 1.0 0.1 20µs PULSE WIDTH Tj = 150°C 0.01 0.1 1 10 100 0.5 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics TJ , Junction Temperature ( ° C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91100 S-80567-Rev. A, 20-Jun-08 www.vishay.com 3 IRFB18N50K, SiHFB18N50K Vishay Siliconix 100000 ISD , Reverse Drain Current (A) VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd 100 C, Capacitance(pF) 10000 TJ = 150 ° C 10 Ciss 1000 TJ = 25 ° C 1 Coss 100 Crss 10 1 10 100 1000 0.1 0.2 V GS = 0 V 0.5 0.8 1.1 1.4 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage VSD ,Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage 20 ID = 17A 1000 VGS , Gate-to-Source Voltage (V) 16 V DS= 400V V DS= 250V V DS= 100V OPERATION IN THIS AREA LIMITED BY RDS(on) ID , Drain Current (A) 100 10us 100us 1ms 1 10ms 12 10 8 4 0 0.1 TC = 25 °C TJ = 150 °C Single Pulse 10 100 1000 10000 0 30 60 90 120 150 QG , Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage VDS , Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 91100 S-80567-Rev. A, 20-Jun-08 IRFB18N50K, SiHFB18N50K Vishay Siliconix RD 20 VGS RG VDS D.U.T. + - VDD ID , Drain Current (A) 15 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 10 Fig. 10a - Switching Time Test Circuit VDS 90 % 5 0 25 50 75 100 125 150 TC , Case Temperature ( °C) Fig. 9 - Maximum Drain Current vs. Case Temperature 1 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Thermal Response (Z thJC ) D = 0.50 0.20 0.1 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 0.01 0.001 0.00001 t1 , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case 15 V VDS tp VDS L Driver RG 20 V tp D.U.T. IAS 0.01 Ω + A - VDD IAS Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91100 S-80567-Rev. A, 20-Jun-08 Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 IRFB18N50K, SiHFB18N50K Vishay Siliconix EAS , Single Pulse Avalanche Energy (mJ) 750 600 ID 7.6A 11A BOTTOM 17A TOP 450 300 150 0 25 50 75 100 125 150 Starting T J, Junction Temperature ( ° C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ 12 V VGS QGS QG 0.2 µF 0.3 µF QGD D.U.T. + - VDS VG VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91100 S-80567-Rev. A, 20-Jun-08 IRFB18N50K, SiHFB18N50K Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91100. Document Number: 91100 S-80567-Rev. A, 20-Jun-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. 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