SIHFP32N50K

IRFP32N50K, SiHFP32N50K Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 190 59 84 Single D FEATURES 500 0.135 • Low Gate Charge Qg Results in Simple Drive Requirement Ruggedness Available • Improved Gate, Avalanche and Dynamic dV/dt RoHS* COMPLIANT • Fully Characterized Capacitance and Avalanche Voltage and Current • Low RDS(on) • Lead (Pb)-free Available TO-247 G APPLICATIONS • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply S N-Channel MOSFET S D G • High Speed Power Switching • Hard Switching and High Frequency Circuits ORDERING INFORMATION Package Lead (Pb)-free SnPb TO-247 IRFP32N50KPbF SiHFP32N50K-E3 IRFP32N50K SiHFP32N50K ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc for 10 s 6-32 or M3 screw Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque TC = 25 °C EAS IAR EAR PD dV/dt TJ, Tstg VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM LIMIT 500 ± 30 32 20 130 3.7 450 32 46 460 13 - 55 to + 150 300d 10 1.1 W/°C mJ A mJ W V/ns °C lbf · in N·m A UNIT V Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Starting TJ = 25 °C, L = 0.87 mH, RG = 25 Ω, IAS = 32 A. c. ISD ≤ 32 A, dI/dt ≤ 197 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may applyrom case. Document Number: 91221 S-81361-Rev. B, 07-Jul-08 www.vishay.com 1 IRFP32N50K, SiHFP32N50K Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.24 MAX. 40 0.26 °C/W UNIT SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Body Diode Reverse Recovery Current Forward Turn-On Time IS ISM VSD trr Qrr IRRM ton TJ = 25 °C, IF = 32 A, dI/dt = 100 A/µsb MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 150 °C VGS = 10 V ID = 3 2 A b 500 3.0 14 0.54 0.135 - 5.0 ± 100 50 250 0.16 - V V/°C V nA µA Ω S VDS = 50 V, ID = 32 A VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 400 V, f = 1.0 MHz VDS = 0 V to 400 VGS = 10 V Vc - 5280 550 45 5630 155 265 28 120 48 54 190 59 84 ns nC pF ID = 32 A, VDS = 400 Vb - VDD = 250 V, ID = 32 A, RG = 4.3 Ω, VGS = 10 Vb - - 530 9.0 30 32 A 130 1.5 800 13.5 V ns µC A G S TJ = 25 °C, IS = 32 A, VGS = 0 Vb - Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. www.vishay.com 2 Document Number: 91221 S-81361-Rev. B, 07-Jul-08 IRFP32N50K, SiHFP32N50K Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 1000 Top VGS 15 V 12 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V 1000 ID, Drain-to-Source Current (A) 100 Bottom ID, Drain-to-Source Current (A) 100 TJ = 150 °C 10 10 1 TJ = 25 °C 1 0.1 5.0 V 20 μs PULSE WIDTH TJ = 25 °C 0.01 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) 0.1 4 5 7 8 VDS = 50 V 20 μs PULSE WIDTH 9 11 12 VGS, Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On Resistance (Normalized) 100 Top ID, Drain-to-Source Current (A) 10 VGS 15 V 12 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V Bottom 5.0 V 3.0 2.5 ID = 32 A 2.0 5.0 V 1.5 1 1.0 0.5 20 μs PULSE WIDTH TJ = 150 °C 0.1 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) 0.0 - 60 - 40 - 20 0 20 40 VGS = 10 V 60 80 100 120 140 160 TJ, Junction Temperature Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91221 S-81361-Rev. B, 07-Jul-08 www.vishay.com 3 IRFP32N50K, SiHFP32N50K Vishay Siliconix 1000000 1000 10000 ISD, Reverse Drain Current (A) VGS = 0 V, Ciss = Cgs + Cgd, Cds Crss = Cgd Coss = Cds + Cgd Ciss f = 1 MHz SHORTED 100 TJ = 150 °C C, Capacitance (pF) 1000 Coss 100 10 TJ = 25 °C 1 Crss 10 1 10 100 1000 0.1 0.2 0.6 0.9 VGS = 0 V 1.3 1.6 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage 20 1000 ID = 32 A VDS = 400 V VDS = 250 V VDS = 100 V OPERATING IN THIS AREA LIMITED BY RDS(on) VGS, Gate-to-Source Voltage (V) 16 ID, Drain Current (A) 100 10 μs 12 8 100 μs 10 1 ms TC = 25 °C TJ = 150 °C Single Pulse 100 4 10 ms 1000 10000 0 0 40 160 80 120 QG, Total Gate Charge (nC) 200 1 10 VDS, Drain-to-Source Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 91221 S-81361-Rev. B, 07-Jul-08 IRFP32N50K, SiHFP32N50K Vishay Siliconix VDS 35 VGS 30 25 ID, Drain Current (A) RG RD D.U.T. + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 20 15 Fig. 10a - Switching Time Test Circuit 10 5 0 25 50 75 125 100 TC, Case Temperature (°C) 150 VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms 1 Thermal Response (ZthJC) D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t1/ t2 2. Peak TJ = PDM x ZthJC + TC 0.001 0.00001 0.0001 0.001 0.01 0.1 1 t , Rectangular Pulse Duration (sec) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp VDS L Driver RG 20 V tp D.U.T IAS 0.01 Ω + A - VDD IAS Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91221 S-81361-Rev. B, 07-Jul-08 IRFP32N50K, SiHFP32N50K Vishay Siliconix 800 TOP EAS, Single Pulse Avalanche Energy (mJ) 640 BOTTOM ID 7A 10 A 16 A 480 320 160 0 25 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ 12 V 10 V QGS QG 0.2 µF 0.3 µF QGD D.U.T. + - VDS VG VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91221 S-81361-Rev. B, 07-Jul-08 IRFP32N50K, SiHFP32N50K Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91221. Document Number: 91221 S-81361-Rev. B, 07-Jul-08 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1